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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2833 occurrences of 878 keywords
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Results
Found 2210 publication records. Showing 2210 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
22 | Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos |
A Compact Built-In Current Sensor for IDDQ Testing. |
IOLTW |
2000 |
DBLP DOI BibTeX RDF |
Bridging and Stuck-on fault testability, Design for testability, DFT, IDDQ testing, Built in current sensors, BICS, Current monitoring |
22 | Dhruva R. Chakrabarti, Ajai Jain |
An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph |
22 | Shih-Yuang Su, Cheng-Wen Wu |
Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns. |
IEEE Trans. Computers |
1994 |
DBLP DOI BibTeX RDF |
sequential faults, ILA, M-testability, constant-length test sequence, pipelined array multiplier, sequential fault testing, logic testing, logic testing, sequential circuits, test pattern generation, logic arrays, combinatorial circuits, test vectors, C-testability, iterative logic arrays, iterative logic array |
22 | Martin Rudolph |
Feedback-testing by using multiple input signature registers. |
J. Electron. Test. |
1990 |
DBLP DOI BibTeX RDF |
Bult-in self-test, design for testability, test-pattern generation, testability analysis, MISR |
22 | John Paul Shen, F. Joel Ferguson |
The Design of Easily Tastabel VLSI Array Multipliers. |
IEEE Trans. Computers |
1984 |
DBLP DOI BibTeX RDF |
design for testability, VLSI testing, Array multipliers, C-testability, exhaustive testing |
21 | Anna Bernasconi 0001, Valentina Ciriani, Rolf Drechsler, Tiziano Villa |
Logic Minimization and Testability of 2-SPP Networks. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Melvin A. Breuer |
Clarifying the record on testability cost functions. |
IEEE Des. Test Comput. |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Jason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi |
Automated Testability Enhancements for Logic Brick Libraries. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Irith Pomeranz, Sudhakar M. Reddy |
Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Irith Pomeranz, Sudhakar M. Reddy |
Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Elena Grigorescu, Tali Kaufman, Madhu Sudan 0001 |
2-Transitivity Is Insufficient for Local Testability. |
CCC |
2008 |
DBLP DOI BibTeX RDF |
error correcting codes, property testing, sublinear time algorithms |
21 | Loganathan Lingappan, Niraj K. Jha |
Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Hao-Chiao Hong |
A Design-for-Digital-Testability Circuit Structure for Sigma-Delta Modulators. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Loganathan Lingappan, Niraj K. Jha |
Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Jaroslav Skarvada, Tomas Herrman, Zdenek Kotásek |
Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Chengying Mao |
AOP-based Testability Improvement for Component-based Software. |
COMPSAC (2) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Irith Pomeranz, Sudhakar M. Reddy |
Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Wei-Tek Tsai, Jerry Gao 0002, Xiao Wei 0001, Yinong Chen |
Testability of Software in Service-Oriented Architecture. |
COMPSAC (2) |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Liangli Ma, Houxiang Wang, Yongjie Li |
Using Component Metadata based on Dependency Relationships Matrix to improve the Testability of Component-based Software. |
ICDIM |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Irith Pomeranz, Sudhakar M. Reddy |
On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Sami Beydeda |
Self-Testability in Unit Testing. |
COMPSAC (2) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Barbara Cannas, Alessandra Fanni, Augusto Montisci |
Testability evaluation for analog linear circuits via transfer function analysis. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou |
Fast, Parallel Two-Rail Code Checker with Enhanced Testability. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Loganathan Lingappan, Niraj K. Jha |
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Ethan Schuchman, T. N. Vijaykumar |
Rescue: A Microarchitecture for Testability and Defect Tolerance. |
ISCA |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Nicola Nicolici, Bashir M. Al-Hashimi |
Testability Trade-Offs for BIST Data Paths. |
J. Electron. Test. |
2004 |
DBLP DOI BibTeX RDF |
power-constrained test, BIST |
21 | José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira 0001 |
A Probabilistic Method for the Computation of Testability of RTL Constructs. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Cecilia Metra, T. M. Mak, Martin Omaña 0001 |
Are Our Design for Testability Features Fault Secure? |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Stephen K. Sunter, Adam Osseiran, Adam Cron, Neil G. Jacobson, Dave Bonnett, Bill Eklow, Carl Barnhart, Ben Bennetts |
Status of IEEE Testability Standards 1149.4, 1532 and 1149.6. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Andrzej Krasniewski |
Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya |
Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Irith Pomeranz, Sudhakar M. Reddy |
On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Haluk Konuk, Leon Xiao |
DFFT : Design For Functional Testability. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Scott Erlanger, Dilip K. Bhavsar, Richard A. Davies |
Testability Features of the Alpha 21364 Microprocessor. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Christoph Hoffmann |
A New Design Flow and Testability Measure for the Generation of a Structural Test and BIST for Analogue and Mixed-Signal Circuits. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara |
Design for Two-Pattern Testability of Controller-Data Path Circuits. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Taewoong Jeon, Sungyoung Lee, Hyonwoo Seung |
Increasing the Testability of Object-Oriented Frameworks with Built-in Tests. |
AISA |
2002 |
DBLP DOI BibTeX RDF |
|
21 | A. N. Trahtman |
A Polynomial Time Algorithm for Left [Right] Local Testability. |
CIAA |
2002 |
DBLP DOI BibTeX RDF |
locally testable, algorithm, graph, language, semigroup, deterministic finite automaton |
21 | Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada |
Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
supply current test, time-variable electric field, test pattern generation, CMOS IC, open defects |
21 | Ryoji Ishikawa, Tomonori Igarashi, Takashi Hirayama, Kensuke Shimizu |
Pseudocube-based expressions to enhance testability. |
APCCAS (2) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Laurence Tianruo Yang, Jon C. Muzio |
Redundant transformations for BIST testability metrics-based data path allocation. |
APCCAS (2) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Benoit Baudry, Yves Le Traon, Gerson Sunyé, Jean-Marc Jézéquel |
Towards a 'Safe' Use of Design Patterns to Improve OO Software Testability. |
ISSRE |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Alessandro Bogliolo, Michele Favalli, Maurizio Damiani |
Enabling testability of fault-tolerant circuits by means of IDDQ-checkable voters. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
Improving path delay testability of sequential circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
21 | A. Schubert, Walter Anheier |
On Random Pattern Testability of Cryptographic VLSI Cores. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
testing of cores, test-ready intellectual property, built-in self-test, pseudorandom testing |
21 | Rolf Drechsler, Wolfgang Günther 0001, Bernd Becker 0001 |
Testability of Circuits Derived from Lattice Diagrams. |
EUROMICRO |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Thomas W. Williams, Rohit Kapur |
Design for Testability in Nanometer Technologies; Searching for Quality. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Sanghyeon Baeg, William A. Rogers |
A cost-effective design for testability: clock line control and test generation using selective clocking. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar |
Primitive delay faults: identification, testing, and design for testability. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Huy Nguyen 0001, Rabindra K. Roy, Abhijit Chatterjee |
Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits. |
J. Electron. Test. |
1999 |
DBLP DOI BibTeX RDF |
sequential circuit BIST, built0in self-test, fault propagation analysis, BIST, partial reset |
21 | Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham |
Design For Testability Method for CML Digital Circuits. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Jacob Savir |
Design for Testability to Combat Delay Faults. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
BIST, LFSR, Delay Test, MISR, LSSD, SRL |
21 | Jacob Savir |
Random pattern testability of memory address logic. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
21 | R. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma |
Testability Features of the AMD-K6 Microprocessor. |
IEEE Des. Test Comput. |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Juan A. Prieto, Adoración Rueda, Ian Andrew Grout, Eduardo J. Peralías, José L. Huertas, Andrew Mark David Richardson |
An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth |
Synthesis of Sequential Circuits with Clock Control to Improve Testability. |
Asian Test Symposium |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik |
A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly |
Behavior and testability preservation under the retiming transformation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Franco Fummi, U. Rovati, Donatella Sciuto |
Functional design for testability of control-dominated architectures. |
ACM Trans. Design Autom. Electr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
interacting FSMs, functional testing |
21 | Dilip K. Bhavsar, John H. Edmondson |
Alpha 21164 Testability Strategy. |
IEEE Des. Test Comput. |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Xinli Gu, Erik Larsson, Krzysztof Kuchcinski, Zebo Peng |
A controller testability analysis and enhancement technique. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Wei-Kang Huang, M. Y. Zhang, Fred J. Meyer, Fabrizio Lombardi |
A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
programmable system, diagnosis, FPGA testing, XOR |
21 | Michiaki Emori, Junko Kumagai, Koichi Itaya, Takashi Aikyo, Tomoko Anan, Junichi Niimi |
ATREX : Design for Testability System for Mega Gate LSIs. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
Design for Testabilty |
21 | Irith Pomeranz, Sudhakar M. Reddy |
On Full Reset as a Design-For-Testability Technique. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka |
A Design for testability Method Using RTL Partitioning. |
Asian Test Symposium |
1996 |
DBLP DOI BibTeX RDF |
line-up structure, internally balanced structure, acyclic structure, partitioning, ATPG, DFT, RTL, isolation, balanced structure |
21 | Elena Dubrova, Jon C. Muzio |
Testability of Generalized Multiple-Valued Reed-Muller Circuits. |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
|
21 | Karl Fuchs |
Synthesis for path delay fault testability via tautology-based untestability identification and factorization. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
21 | Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly |
Testability Implications of Performance-Driven Logic Synthesis. |
IEEE Des. Test Comput. |
1995 |
DBLP DOI BibTeX RDF |
|
21 | Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel |
An observability enhancement approach for improved testability and at-speed test. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Andrew J. Bishop, André Ivanov |
On the Testability of CMOS Feedback Amplifiers. |
DFT |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
Sequential test generation and synthesis for testability at the register-transfer and logic levels. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
21 | Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer |
Delay-fault test generation and synthesis for testability under a standard scan design methodology. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
21 | Chao Feng, Jon C. Muzio, Fabrizio Lombardi |
On the testability of array structures for FFT computation. |
J. Electron. Test. |
1993 |
DBLP DOI BibTeX RDF |
Constant tetability, testing, fault detection, FFT, fault location |
21 | Khalil Drira, Pierre Azéma, B. Soulas, A. M. Chemali |
Testability of a Communicating System Through an Environment. |
TAPSOFT |
1993 |
DBLP DOI BibTeX RDF |
|
21 | Thomas Müller-Wipperfürth, Josef Scharinger, Franz Pichler |
FSM Shift Register Realization for Improved Testability. |
EUROCAST |
1993 |
DBLP DOI BibTeX RDF |
|
21 | Silvia Ercolani, Michele Favalli, Maurizio Damiani, Piero Olivo, Bruno Riccò |
Testability measures in pseudorandom testing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
|
21 | Michael J. Bryan, Srinivas Devadas, Kurt Keutzer |
Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
|
21 | Janusz Rajski, Jagadeesh Vasudevamurthy |
The testability-preserving concurrent decomposition and factorization of Boolean expressions. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1992 |
DBLP DOI BibTeX RDF |
|
21 | Mehrdad Bidjan-Irani |
A Rule-Based Design-for-Testability Rule Checker. |
IEEE Des. Test Comput. |
1991 |
DBLP DOI BibTeX RDF |
|
21 | Rajiv Gupta 0002, Rajagopalan Srinivasan, Melvin A. Breuer |
Reorganizing Circuits to Aid Testability. |
IEEE Des. Test Comput. |
1991 |
DBLP DOI BibTeX RDF |
|
21 | Gertjan J. Hemink, Berend W. Meijer, Hans G. Kerkhoff |
Testability analysis of analog systems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
21 | Weiwei Mao, Michael D. Ciletti |
DYTEST: a self-learning algorithm using dynamic testability measures to accelerate test generation. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1990 |
DBLP DOI BibTeX RDF |
|
21 | F. Darlay, Bernard Courtois |
Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
21 | Susheel J. Chandra, Janak H. Patel |
Experimental evaluation of testability measures for test generation (logic circuits). |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
|
21 | André Ivanov, Vinod K. Agarwal |
Dynamic testability measures for ATPG. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
21 | Mehmet A. Cirit |
Switch Level Random Pattern Testability Analysis. |
DAC |
1988 |
DBLP BibTeX RDF |
|
21 | Weiwei Mao, Michael D. Ciletti |
Dytest: A Self-Learning Algorithm Using Dynamic Testability Measures to Accelerate Test Generation. |
DAC |
1988 |
DBLP BibTeX RDF |
|
18 | Dong Xiang, Mingjing Chen, Jia-Guang Sun |
Scan BIST with biased scan test signals. |
Sci. China Ser. F Inf. Sci. |
2008 |
DBLP DOI BibTeX RDF |
random testability, test signal, biased random testing, scan-based BIST |
18 | Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach |
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. |
NOCS |
2008 |
DBLP DOI BibTeX RDF |
NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous |
18 | Ted Vucurevich |
3-D semiconductor's: more from Moore. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
partitioning, analysis, testability, 3-D integration |
18 | Dong Xiang, Mingjing Chen, Hideo Fujiwara |
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
Random testability, scan enable signal, weighted random testing, scan-based BIST |
18 | Irith Pomeranz, Sudhakar M. Reddy |
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
overtesting, test generation, Design-for-testability, synchronous sequential circuits, redundant faults, full-scan, fault dominance |
18 | Jee-Youl Ryu, Bruce C. Kim, Iboun Taimiya Sylla |
A Novel RF Test Scheme Based on a DFT Method. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
RF design-for-testability, known-good-die, defects, low noise amplifier, RF test |
18 | Margrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski |
Using a software testing technique to identify registers for partial scan implementation. |
SBCCI |
2006 |
DBLP DOI BibTeX RDF |
hardware testing, testability improvement, hardware description language, automatic test generation, partial scan design |
18 | Ahmad A. Al-Yamani |
DFT for controlled-impedance I/O buffers. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
I/O characterization, I/O test, built-in self test, design-for-testability |
18 | Dong Xiang, Ming-Jing Chen, Hideo Fujiwara |
Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
Test signal, random testability, weighted random testing, scan-based BIST |
18 | Muhammad Nummer, Manoj Sachdev |
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
high-performance testing, controlled-delay flip-flop, built-in self test, delay-fault testing, design for delay testability |
18 | Shiyi Xu |
Build-In-Self-Test for Software. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
Software Testing, Design for Testability, Build-In-Self-Test (BIST) |
18 | Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara |
Test Synthesis for Datapaths Using Datapath-Controller Functions. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
hierarchical test generation, non-scan design, design-for-testability, at-speed testing, RTL circuit |
18 | Taewoong Jeon, Hyonwoo Seung, Sungyoung Lee |
Embedding built-in tests in hot spots of an object-oriented framework. |
ACM SIGPLAN Notices |
2002 |
DBLP DOI BibTeX RDF |
hook classes, testability, object-oriented framework, built-in test (BIT) |
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