Search results for "pipeline"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Miodrag Potkonjak	Discrete-relaxation-based heuristic techniques for video algorithm/architecture matching and system level transformations.	ICIP	1995	DBLP DOI BibTeX RDF	discrete-relaxation-based heuristic techniques, video algorithm, system level transformations, computational transformations, throughput performance, iterative heuristic approach, behavioral transformations, rephasing, architecture matching, computational complexity, image processing, VLSI, pipelining, iterative methods, pipeline processing, retiming, integrated circuit design, system level design, video processing, video signal processing, heuristic programming, digital signal processing chips, circuit optimisation, throughput optimization
12	Jelio Todorov Yantchev, C. G. Huang, Mark B. Josephs, Ivailo M. Nedelchev	Low-latency asynchronous FIFO buffers.	ASYNC	1995	DBLP DOI BibTeX RDF	buffer circuits, low-latency asynchronous FIFO buffers, parallel asynchronous implementation, interface circuitry, inter-chip communication wires, acknowledge signal, high-throughput multiple-burst signalling scheme, packet switching, asynchronous circuits, pipeline processing, propagation delay
12	Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man	Synthesis of pipelined DSP accelerators with dynamic scheduling.	ISSS	1995	DBLP DOI BibTeX RDF	DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules
12	Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama	Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic
12	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems.	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
12	Ram K. Krishnamurthy, Ramalingam Sridhar	A CMOS wave-pipelined image processor for real-time morphology .	ICCD	1995	DBLP DOI BibTeX RDF	CMOS wave-pipelined image processor, real-time morphology, high-speed morphological image processor, wave-pipelined transmission gate logic, two-stage morphological skeleton transform filter, regular pipelined architectures, real-time systems, computational complexity, image processing, latency, pipeline processing, CMOS integrated circuits, hardware complexity
12	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
12	Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor	A comparative evaluation of software techniques to hide memory latency.	HICSS (1)	1995	DBLP DOI BibTeX RDF	comparative software evaluation, software oriented techniques, superscalar machines, superpipelined machines, software cache prefetching, data fetch request, software controlled prefetching, aggressive prefetching, memory bandwidth requirements, bus traffic, performance, parallel machines, program compilers, processor scheduling, software performance evaluation, software pipelining, pipeline processing, microarchitecture, cache storage, instruction set architecture, memory latency, loop unrolling, static scheduling, conditional branches
12	Siamak Arya, Howard Sachs, Sreeram Duvvuru	An architecture for high instruction level parallelism.	HICSS (1)	1995	DBLP DOI BibTeX RDF	high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, program control structures, branches, registers, functional units, multiple instructions, conditional execution
12	Yin Chan, Sun-Yuan Kung	Bit Level Block Matching Systolic Arrays.	ASAP	1995	DBLP DOI BibTeX RDF	bit level systolic array, video signal processing architecture, pipeline, block matching
12	N. Ranganathan, K. B. Doreswamy	A systolic algorithm and architecture for image thinning.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	image thinning, 4-distance transform, single VLSI chip, 2.59 ms, 0.327 ms, parallel algorithms, image processing, VLSI, parallelism, skeleton, systolic arrays, CMOS, pipeline processing, VLSI architecture, digital signal processing chips, processing elements, CMOS digital integrated circuits, linear time, systolic architecture, systolic algorithm, multiple objects
12	S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta	A single chip, pipelined, cascadable, multichannel, signal processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron
12	V. Visvanathan, S. Ramanathan	A modular systolic architecture for delayed least mean squares adaptive filtering.	VLSI Design	1995	DBLP DOI BibTeX RDF	modular systolic architecture, delayed least mean squares adaptive filtering, coefficient adaptation, input sampling periods, output latency, convergence behavior, systolization technique, maximum sampling rate, multiply-accumulate processor modules, systolic arrays, pipeline processing, adaptive filters, convergence of numerical methods, least mean squares methods
12	Mario Kovac, N. Ranganathan	JAGUAR: a high speed VLSI chip for JPEG image compression standard.	VLSI Design	1995	DBLP DOI BibTeX RDF	JAGUAR, high speed VLSI chip, JPEG image compression standard, pipelined single chip VLSI architecture, entropy encoder, clock rate, input rate, CMOS VLSI chip, Huffman entropy coding, 1024 pixel, 1048576 pixel, VLSI, parallel architectures, data compression, image coding, discrete cosine transforms, discrete cosine transform, pipeline processing, color images, image colour analysis, digital signal processing chips, Huffman codes, high throughput, CMOS digital integrated circuits, entropy codes, 100 MHz
12	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
12	Debabrata Ghosh, Soumitra Kumar Nandy	Wave pipelined architecture folding: a method to achieve low power and low area.	VLSI Design	1995	DBLP DOI BibTeX RDF	wave pipelined architecture folding, clock-free wave pipelining scheme, chip area reduction, VLSI, low power design, logic design, pipeline processing, integrated circuit design, digital integrated circuits
12	Behrooz Parhami	Comments on "Evaluation of A + B + K Conditions Without Carry Propagation".	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	carry-free circuit, A+B=K, negative effects, carry-save redundant numbers, (3, 2)-counters, carry propagation, carry-save numbers, pipeline processing, logic circuits, pipelined architectures, comparators, addition, parallel counters, redundant number representation, conditional branches
12	Gideon D. Intrater, Ilan Y. Spillinger	Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	decoded instruction cache, variable instruction length computers, instruction decoder, instruction pipeline stages, instruction length distribution, UNIX applications, performance evaluation, performance evaluation, computer architecture, trace driven simulations, buffer storage
12	Michael J. Corinthios	Optimal Parallel and Pipelined Processing Through a New Class of Matrices with Application to Generalized Spectral Analysis.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	general-base matrices, sampling matrices, Poles, algorithm parameters, parallel pipelined processors, memory topology, access uniformity, shuffle complexity, algorithm factorizations, generalized perfect shuffle, Chrestenson generalized Walsh transform, generalized spectral analysis, parallel processing, parallel architectures, computer architecture, pipeline processing, pipelined processing, matrix algebra, pointers, pipelined architecture, zeros, matrices, spans, matrix theory
12	Pei-Ji Yang, Sing-Ban Tien, Cauligi S. Raghavendra	Embedding of Rings and Meshes onto Faulty Hypercubes Using Free Dimensions.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	free dimensions, linear chain, torus structure, free dimension, fault tolerance, parallel, fault tolerant computing, partition, pipeline, redundancy, redundancy, meshes, mesh, hypercube networks, rings, ring, faulty hypercubes, subcubes
12	Anne Rogers, Keshav Pingali	Compiling for Distributed Memory Architectures.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	processdecomposition, locality ofreference, run-time resolution, message traffic, hydrodynamicsbenchmark, Intel iPSC/2, load balancing, parallel programming, synchronization, pipelining, synchronisation, program compilers, distributed memory systems, parallelizing compiler, pipeline processing, high-level languages, distributed memory architectures, SIMPLE
12	Steven L. Scott, James R. Goodman	The Impact of Pipelined Channels on k-ary n-Cube Networks.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	pipelined channels, bisection constraints, optimaldimensionality, pipelined-channel networks, switching overhead, performance evaluation, multiprocessor interconnection networks, pipeline processing, cycle time, k-ary n-cube networks, message lengths
12	Alok N. Choudhary, Bhagirath Narahari, David M. Nicol, Rahul Simha	Optimal Processor Assignment for a Class of Pipelined Computations.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	multitasked parallel architectures, processor assignment problem, series-parallel partial order, parallel analysis, task structure, series-parallel task system, series analysis, computer vision, resource allocation, parallel architectures, data dependencies, pipeline processing, data sets, pipelined computations
12	Michael S. Schlansker, Vinod Kathail, Sadun Anik	Height reduction of control recurrences for ILP processors.	MICRO	1994	DBLP DOI BibTeX RDF	back-substitution, blocked back-substitution, control height reduction, parallelism, software pipeline, control dependences, loop optimization, recurrences
12	Chris H. Perleberg, Alan Jay Smith	Branch Target Buffer Design and Optimization.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	branch target buffer design, branch tag, prediction information, branch target address, optimization, complexity, caching, pipeline processing, buffer storage, instructions, instruction sets, pipelined processors, branches, performance penalty, least recently used
12	Marcel Lapointe, Huu Tuê Huynh, Paul Fortier	Systematic Design of Pipelined Recursive Filters.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	systematic design, pipelined recursive filters, multiplication algorithm, most significant digit first, pipelining delays, minimum hardware, minimum latency, number system radix, second-order all-pole filter, radix-4 representation, delays, digital arithmetic, pipeline processing, multiplier, digital filters
12	Toshio Nakatani, Kemal Ebcioglu	Making Compaction-Based Parallelization Affordable.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	compaction-based parallelization, code explosion problem, software lookahead heuristic, VLIW parallelizing compiler, branch-intensive code, AIX utilities, fgrep, sed, parallel programming, parallel architectures, compress, program, sort, instruction-level parallelism, software pipelining, pipeline processing, instruction sets, loop parallelization, yacc
12	Joseph F. JáJá, Kwan Woo Ryu	Optimal Algorithms on the Pipelined Hypercube and Related Networks.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	pipelined hypercube, monotone polygon, line packing, parallel algorithms, parallel algorithms, computational geometry, pipeline processing, combinatorial problems, combinatorial mathematics, cube-connected-cycles, shuffle-exchange
12	Krishna V. Palem, Barbara B. Simons	Scheduling Time-Critical Instructions on RISC Machines.	ACM Trans. Program. Lang. Syst.	1993	DBLP DOI BibTeX RDF	RISC machine scheduling, NP-complete, latency, compiler optimization, register allocation, greedy algorithm, instruction scheduling, deadline, RISC, pipeline processor
12	Ing-Jer Huang, Alvin M. Despain	An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors.	MICRO	1993	DBLP DOI BibTeX RDF	compiler back-end generation, hardware/software tradeoffs, inter-instruction dependency, pipeline hazard resolution, high level synthesis
12	Ravi Ganesan, Shlomo Weiss	Scalar Memory References in Pipelined Multiprocessors: A Performance Study.	IEEE Trans. Software Eng.	1992	DBLP DOI BibTeX RDF	scalar memory references, pipelined multiprocessors, high memory bandwidth, memory cycle, processor cycle time, bank reservation time, bank busy time, performance evaluation, probability, Markov chain, Markov processes, parallel machines, Markov models, storage management, simulation results, pipeline processing, state space, transition probabilities, pipelined computers, memory bank
12	Daniel C. McCrackin	Eliminating Interlocks in Deeply Pipelined Processors by Delay Enforced Multistreaming.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	deeply pipelined processors, delay enforced multistreaming, data dependency problem, jump problem, interdispatch delay, stream dispatching algorithms, modified fixed delay, encoded delay with fixed minimum, pipeline processing, processor architecture, interleaving, interlocks
12	Pradeep K. Dubey, Michael J. Flynn	Branch Strategies: Modeling and Optimization.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	branch-delay penalty, instruction bandwidth, i-traffic, wasted instruction fetches, active branch prediction, loop buffers, parallel programming, compilers, program compilers, pipeline processing, pipelined processors, branch-target-buffer
12	Henk J. Sips, Hai-Xiang Lin	An Improved Vector-Reduction Method.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	symmetric reduction methods, pipelined vector-reduction method, asymmetric reduction methods, digital arithmetic, pipeline processing
12	Ivan P. Radivojevic, Jayantha A. Herath	Executing DSP Applications in a Fine-Grained Dataflow Environment.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	fine-grained dataflow architecture, numerically intensive digital signal processing, pipelined data-parallel algorithms, high-level language programming blocks, logical fine-grained decomposition, serial fraction, fine-grained general-purpose dataflow computing, parallel algorithms, parallel architectures, pipeline processing, precedence relations, computerised signal processing, DSP applications
12	Peter Kornerup, David W. Matula	An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	tree pipeline, Gosper, redundant binary bit-pipelined rational arithmetic, redundant binary representation, rational operands, partial quotient arithmetic algorithm, online arithmetic unit, signed bit level, binary radix, binary rational representation, online delays, simulation, parallel computation, redundancy, interconnection, product, digital arithmetic, number theory, difference, quotient, sum
12	Norman P. Jouppi	The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	machine performance, first-order estimate, machine parallelism, instruction-level, machine pipelines, MultiTitan, superscalar machine, performance evaluation, parallel architectures, pipeline processing, CRAY-1
12	David Bernstein, Michael Rodeh, Izidor Gertner	On the Complexity of Scheduling Problems for Parallel/Pipelined Machines.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	pipelined machines, scheduling, computational complexity, complexity, NP-completeness, parallel machines, parallel machines, polynomial-time algorithm, pipeline processing, scheduling problems, dedicated processors
12	Jik H. Chang, Oscar H. Ibarra, Moon-Jung Chung, Kotesh K. Rao	Systolic Tree Implementation of Data Structures.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	systolic tree implementation, dequeues, unit response time, unit pipeline interval, data elements, data structures, data structures, queueing theory, trees (mathematics), queues, stacks, data transmission, dictionary machines
12	David Bernstein, Haran Boral, Ron Y. Pinter	Optimal Chaining in Expression Trees.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	optimal chaining, vector instructions pipelining, explicit pipelining, expression trees, linear time scheduling algorithm, scheduling, computational complexity, parallel programming, dynamic programming, pipeline processing, automatic programming, automatic code generation, complexity analysis, Cray-1, dynamic programming algorithms
12	James W. Watterson, Jill J. Hallenbeck	Modulo 3 Residue Checker: New Results on Performance and Cost.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	modulo-3 residue code checker, pipelined serial multiplier, concurrent self-test, minimum error latency, multiplier input operands, 4- mu m NMOS, standard cell design, performance evaluation, integrated circuit testing, error detection, automatic testing, digital arithmetic, pipeline processing, multiplying circuits, built in test, field effect integrated circuits, error detection coverage
12	Krishna P. Mikkilineni, Stanley Y. W. Su	An Evaluation of Relational Join Algorithms in a Pipelined Query Processing Environment.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	timing equations, relational join algorithms, pipelined query processing environment, nested block, sort-merge, pipelined sort-merge, performance evaluation, relational databases, relational databases, distributed processing, distributed databases, distributed databases, sorting, database theory, hash, pipeline processing, merging, query execution
12	Charles C. Wang, Trieu-Kien Truong, Howard M. Shao, Leslie J. Deutsch, Jim K. Omura, Irving S. Reed	VLSI Architectures for Computing Multiplications and Inverses in GF(2m).	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	Finite field inverse, normal basis multiplier, pipeline, systolic array, inverse, normal basis, finite field multiplication, Massey-Omura multiplier, finite field multiplier
12	Kuang Yung Liu	Architecture for VLSI Design of Reed-Solomon Decoders.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	BCH decoders, finite field processors, Reed?Solomon decoders, parallel processing, VLSI, error-correcting codes, pipeline processing
12	Gian Carlo Bongiovanni	Two VLSI Structures for the Discrete Fourier Transform.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Area-time complexity, shuffle-exchange connections, computational complexity, VLSI, Fourier transformation, data rate, pipeline structures
12	Martin De Prycker	Representing the Effect of Instruction Prefetch in a Microprocessor Performance Model.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Best/worst case, instruction prefetch pipeline, memory speed, performance analysis, clock cycles
12	Trieu-Kien Truong, Irving S. Reed, C.-S. Yeh, Howard M. Shao	A Parallel Architecture for Digital Filtering Using Fermat Number Transforms.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Fermat number transform, overlap-save method, VLSI, pipeline, Convolution, digital filter
12	Howard A. Sholl, Kevin Morris, James Norris	A Multimicroprocessor System for Real-Time Classification of Railroad Track Flaws.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	pipeline system, railroad track flaws, pattern recognition, real-time system, Multiple processor
12	Neil R. Lincoln	Technology and Design Tradeoffs in the Creation of a Modern Supercomputer.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	Architecture, parallelism, pipeline, technology, supercomputer, vector processor
12	Douglas W. Clark, Butler W. Lampson, Kenneth A. Pier	The Memory System of a High-Performance Personal Computer.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	scheduling, synchronization, Cache, pipeline, virtual memory, memory system, high bandwidth
12	Alvin M. Despain	Very Fast Fourier Transform Algorithms Hardware for Implementation.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	vector rotation., FFT, digital signal processing, Fourier transform, pipeline processors, parallel processors, CORDIC
12	David H. Hartke, Warren M. Sterling, Jack E. Shemer	Design of a Raster Display Processor for Office Applications.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	Alphanumeric display, character generator, distributed function architecture, high-speed CRT refresh, keyboard display systems, raster scan display processor, typewriter emulation, pipeline processing, word processing, text editing, graphic display
12	Hon Fung Li	Scheduling Trees in Parallel/Pipelined Processing Environments.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Flush time, polynomial completeness, scheduling vector, parallel, reconfiguration, pipeline, tree, latency, structure, sharing, preemption
12	Barry K. Gilbert, Martin T. Storma, Carl E. James, Leon W. Hobrock, Edward S. Yang, Keith C. Ballard, Earl H. Wood	A Real-Time Hardware System for Digital Processing of Wide-Band Video Images.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	digital communications interface, high-speed memory accessing, modular digital system, pipeline arithmetic processing, slaved computer, wide-band video, image manipulation, A/D conversion
12	Jean-Loup Baer	Multiprocessing Systems.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF	synchronization of concurrent processes, tight and loose coupling, multiprocessors, control, Array processors, pipeline computers
11	Amir Masoud Gharehbaghi, Bijan Alizadeh, Masahiro Fujita	Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	overclocking, timing error detection, timing error recovery, fpga
11	Yi-Hua E. Yang, Viktor K. Prasanna	High throughput and large capacity pipelined dynamic search tree on FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	2-3 tree, in-place update, ip forwarding, pipelined tree, b-tree, dynamic update, incremental update, openflow
11	Jialu Huang, Arun Raman, Thomas B. Jablin, Yun Zhang 0005, Tzu-Han Hung, David I. August	Decoupled software pipelining creates parallelization opportunities.	CGO	2010	DBLP DOI BibTeX RDF	DSWP, enabling transformation, parallelization, multicore, speculation
11	Muhammad Bilal Anwer, Murtaza Motiwala, Muhammad Mukarram Bin Tariq, Nick Feamster	SwitchBlade: a platform for rapid deployment of network protocols on programmable hardware.	SIGCOMM	2010	DBLP DOI BibTeX RDF	network virtualization, NetFPGA
11	Serguei A. Mokhov	Evolution of MARF and its NLP framework.	C3S2E	2010	DBLP DOI BibTeX RDF	MARF, software systems evolution, statistical natural language processing (NLP)
11	Craig Chambers, Ashish Raniwala, Frances Perry, Stephen Adams 0001, Robert R. Henry 0001, Robert Bradshaw, Nathan Weizenbaum	FlumeJava: easy, efficient data-parallel pipelines.	PLDI	2010	DBLP DOI BibTeX RDF	java, mapreduce, data-parallel programming
11	Andrei Tatarinov	Reyes using DirectX 11.	SIGGRAPH Talks	2010	DBLP DOI BibTeX RDF
11	Gregory Meeres-Young, Hannes Ricklefs, Robert Tovell	Managing thousands of assets for the Prince of Persia city of Alamut.	SIGGRAPH Talks	2010	DBLP DOI BibTeX RDF
11	Christine Rochange, Pascal Sainrat	A Context-Parameterized Model for Static Analysis of Execution Times.	Trans. High Perform. Embed. Archit. Compil.	2009	DBLP DOI BibTeX RDF	timing analysis, Worst-Case Execution Time
11	Alan Chu, Chi-Wing Fu, Andrew J. Hanson, Pheng-Ann Heng	GL4D: A GPU-based Architecture for Interactive 4D Visualization.	IEEE Trans. Vis. Comput. Graph.	2009	DBLP DOI BibTeX RDF
11	Bryan McDonnel, Niklas Elmqvist	Towards Utilizing GPUs in Information Visualization: A Model and Implementation of Image-Space Operations.	IEEE Trans. Vis. Comput. Graph.	2009	DBLP DOI BibTeX RDF
11	Wallace Santos Lages, Carlúcio Cordeiro, Dorgival O. Guedes	Performance analysis of a parallel multi-view rendering architecture using light fields.	Vis. Comput.	2009	DBLP DOI BibTeX RDF	Multiple viewpoint rendering, Light field rendering, Parallel rendering
11	Thomas Panhofer, Werner Friesenbichler, Martin Delvai	Optimization concepts for self-healing asynchronous circuits.	DDECS	2009	DBLP DOI BibTeX RDF
11	Eric Stotzer, Ernst L. Leiss	Modulo scheduling without overlapped lifetimes.	LCTES	2009	DBLP DOI BibTeX RDF	instruction level parallelism, register allocation, software pipelining, modulo scheduling
11	Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson	Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE).	LCTES	2009	DBLP DOI BibTeX RDF	l0/filter cache, lookahead instruction fetch engine (life), tagless hit instruction cache (th-ic)
11	Tsung-Te Lai, Tiffany Yu-Han Chen, Hao-Hua Chu, Polly Huang	PipeProbe: mapping hidden water pipelines.	SenSys	2009	DBLP DOI BibTeX RDF	water pipe, accelerometer, pressure sensor
11	Erdal Cayirci	Deployed sensor networks and their security challenges in practice.	SIN	2009	DBLP DOI BibTeX RDF	sensor, actuator, secure routing
11	Lik Wong, Nimar S. Arora, Lei Gao, Thuvan Hoang, Jingwei Wu	Oracle Streams: A High Performance Implementation for Near Real Time Asynchronous Replication.	ICDE	2009	DBLP DOI BibTeX RDF
11	Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi	CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.	HPCA	2009	DBLP DOI BibTeX RDF
11	Gabriel H. Loh, Samantika Subramaniam, Yuejian Xie	Zesto: A cycle-level simulator for highly detailed microarchitecture exploration.	ISPASS	2009	DBLP DOI BibTeX RDF
11	Hannah M. Dee, Karen E. Petrie, Roger D. Boyle, Reena Pau	Why are we still here?: experiences of successful women in computing.	ITiCSE	2009	DBLP DOI BibTeX RDF	motivation, gender issues, women in computing
11	Matthew Burnside, Angelos D. Keromytis	F3ildCrypt: End-to-End Protection of Sensitive Information in Web Services.	ISC	2009	DBLP DOI BibTeX RDF
11	Jasper R. R. Uijlings, Arnold W. M. Smeulders, Remko J. H. Scha	Real-time bag of words, approximately.	CIVR	2009	DBLP DOI BibTeX RDF	feature extraction, image retrieval, random forest, computational efficiency, bag of words
11	Alexander Wilkie, Andrea Weidlich, Marcus A. Magnor, Alan Chalmers	Predictive rendering.	SIGGRAPH ASIA Courses	2009	DBLP DOI BibTeX RDF
11	Kevin Geiger	Keeping your money on the screen & off the floor.	SIGGRAPH ASIA Courses	2009	DBLP DOI BibTeX RDF
11	Fang Liu, Meng-Cheng Huang, Xuehui Liu, Enhua Wu	Single pass depth peeling via CUDA rasterizer.	SIGGRAPH Talks	2009	DBLP DOI BibTeX RDF
11	Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang	Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs).	ISQED	2009	DBLP DOI BibTeX RDF
11	David Grelaud, Nicolas Bonneel, Michael Wimmer 0001, Manuel Asselot, George Drettakis	Efficient and practical audio-visual rendering for games using crossmodal perception.	SI3D	2009	DBLP DOI BibTeX RDF	audio-visual rendering, crossmodal perception
11	Akihiko Torii, Michal Havlena, Tomás Pajdla	Omnidirectional Image Stabilization by Computing Camera Trajectory.	PSIVT	2009	DBLP DOI BibTeX RDF	Structure from Motion, Omnidirectional Vision
11	Simone Campanoni, Giovanni Agosta, Stefano Crespi-Reghizzi	A parallel dynamic compiler for CIL bytecode.	ACM SIGPLAN Notices	2008	DBLP DOI BibTeX RDF	virtual execution system, parallel virtual machine, dynamic compilation
11	Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton	Practical Asynchronous Interconnect Network Design.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
11	Robert M. Kirby, Cláudio T. Silva	The Need for Verifiable Visualization.	IEEE Computer Graphics and Applications	2008	DBLP DOI BibTeX RDF
11	Marc Pollefeys, David Nistér, Jan-Michael Frahm, Amir Akbarzadeh, Philippos Mordohai, Brian Clipp, Chris Engels, David Gallup, Seon Joo Kim, Paul Merrell, C. Salmi, Sudipta N. Sinha, B. Talton, Liang Wang 0002, Qingxiong Yang, Henrik Stewénius, Ruigang Yang, Greg Welch, Herman Towles	Detailed Real-Time Urban 3D Reconstruction from Video.	Int. J. Comput. Vis.	2008	DBLP DOI BibTeX RDF	Large scale modeling, Urban reconstruction, Depth map fusion, 3D reconstruction, Structure from motion, Stereo vision, Plane sweeping
11	Larry Seiler, Doug Carmean, Eric Sprangle, Tom Forsyth, Michael Abrash, Pradeep Dubey, Stephen Junkins, Adam T. Lake, Jeremy Sugerman, Robert Cavin, Roger Espasa, Ed Grochowski, Toni Juan, Pat Hanrahan	Larrabee: a many-core x86 architecture for visual computing.	ACM Trans. Graph.	2008	DBLP DOI BibTeX RDF	graphics architecture, many-core computing, realtime graphics, software rendering, throughput computing, visual computing, parallel processing, GPGPU, SIMD
11	Xinhao Wang, Jiazhong Nie, Dingsheng Luo, Xihong Wu	A Joint Segmenting and Labeling Approach for Chinese Lexical Analysis.	ECML/PKDD (2)	2008	DBLP DOI BibTeX RDF	WFSTs, Chinese lexical analysis, joint segmentation and labeling
11	Roy J. Byrd, Mary S. Neff, Wilfried Teiken, Youngja Park, Keh-Shin F. Cheng, Stephen C. Gates, Karthik Visweswariah	Semi-automated logging of contact center telephone calls.	CIKM	2008	DBLP DOI BibTeX RDF	automatic summarization of dialogue, contact center analytics, speech analytics, natural language processing
11	Paolo Cozzi, Ivan Merelli, Luciano Milanesi	A Visualization ToolKit Based Application for Representing Macromolecular Surfaces.	CIBB	2008	DBLP DOI BibTeX RDF	Molecular visualization, Molecular Surfaces, Visualization Toolkit
11	Se-gon Roh, Do Wan Kim, Jung-Sub Lee, Hyungpil Moon, Hyouk Ryeol Choi	Modularized in-pipe robot capable of selective navigation Inside of pipelines.	IROS	2008	DBLP DOI BibTeX RDF
11	Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee	A hybrid software-based self-testing methodology for embedded processor.	SAC	2008	DBLP DOI BibTeX RDF	embedded processor testing, fault coverage, functional testing, software-based self-test
11	Mark Muir, Tughrul Arslan, Iain Lindsay	Automated Dynamic Throughput-constrained Structural-level Pipelining in Streaming Applications.	DATE	2008	DBLP DOI BibTeX RDF
11	Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt	Performance-aware speculation control using wrong path usefulness prediction.	HPCA	2008	DBLP DOI BibTeX RDF
11	Andre Guntoro, Manfred Glesner	High-performance fpga-based floating-point adder with three inputs.	FPL	2008	DBLP DOI BibTeX RDF
11	Xinbiao Gan, Kui Dai, Zhiying Wang 0003	Low-Level Component for OpenGL ES Oriented Heterogeneous Architecture with Optimization.	ICYCS	2008	DBLP DOI BibTeX RDF
11	Qishi Wu, Yi Gu, Mengxia Zhu, Nageswara S. V. Rao	Optimizing network performance of computing pipelines in distributed environments.	IPDPS	2008	DBLP DOI BibTeX RDF
11	Haris Javaid, Sri Parameswaran	Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	design space exploration, integer linear programming, MPSoCs