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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6285 occurrences of 1975 keywords
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Results
Found 21486 publication records. Showing 21486 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
28 | Yao-Wen Chang, D. F. Wong 0001, C. K. Wong |
Design and analysis of FPGA/FPIC switch modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 394-401, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
FPGA/FPIC switch modules, routing resources, FPIC, network-flow techniques, field programmable interconnect chip, field programmable gate arrays, FPGA, field programmable gate arrays, logic design, heuristic algorithm, programmable logic arrays, routability |
28 | Atabak Mahram, Martin C. Herbordt |
Fast and accurate NCBI BLASTP: acceleration with multiphase FPGA-based prefiltering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 24th International Conference on Supercomputing, 2010, Tsukuba, Ibaraki, Japan, June 2-4, 2010, pp. 73-82, 2010, ACM, 978-1-4503-0018-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
FPGA-based coprocessors, high performance reconfigurable computing, bioinformatics, biological sequence alignment |
28 | Yibo Chen, Jishen Zhao, Yuan Xie 0001 |
3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 55-60, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
non-volatile FPGA, phase-change memory, 3D IC |
28 | Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson 0001, Krste Asanovic |
RAMP gold: an FPGA-based architecture simulator for multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 463-468, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
simulation, FPGA, multiprocessors |
28 | Yi Zhu 0002, Yuanfang Hu, Michael B. Taylor, Chung-Kuan Cheng |
Energy and switch area optimizations for FPGA global routing architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(1), pp. 13:1-13:25, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, low power, global routing |
28 | René Müller 0001, Jens Teubner |
FPGA: what's in it for a database? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the ACM SIGMOD International Conference on Management of Data, SIGMOD 2009, Providence, Rhode Island, USA, June 29 - July 2, 2009, pp. 999-1004, 2009, ACM, 978-1-60558-551-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
data processing vlsi, fpga, hardware acceleration |
28 | Scott Cromar, Jaeho Lee, Deming Chen |
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 838-843, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
glitch power, FPGA, high-level synthesis, power reduction |
28 | Jianbin Huang, Zongwu Xie, Hong Liu 0002, Kai Sun, Yechao Liu, Zainan Jiang |
DSP/FPGA-based Controller Architecture for Flexible Joint Robot with Enhanced Impedance Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 53(3), pp. 247-261, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
M-LVDS serial data bus, Torque ripple, FPGA, DSP, Impedance control, Flexible joint |
28 | Kanupriya Gulati, Sunil P. Khatri |
Improving FPGA routability using network coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 147-150, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, network coding |
28 | In-Kwon Park, Jung-Hyun Kim 0006, Kwang-Seok Hong |
An implementation of an FPGA-based embedded gesture recognizer using a data glove. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICUIMC ![In: Proceedings of the 2nd International Conference on Ubiquitous Information Management and Communication, ICUIMC 2008, Suwon, Korea, January 31 - February 01, 2008, pp. 496-500, 2008, ACM, 978-1-59593-993-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, VHDL, gesture recognition |
28 | Camel Tanougast, Serge Weber, Gilles Millerioux, Jamal Daafouz, Ahmed Bouridane |
VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 386-389, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Cryptography system, self-synchronising stream cipher, FPGA, VLSI design |
28 | Shrutisagar Chandrasekaran, Abbes Amira |
High Performance FPGA Implementation of the Mersenne Twister. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 482-485, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
RC1000, FPGA, Mersenne Twister, Handel C |
28 | Yi-Hua E. Yang, Weirong Jiang, Viktor K. Prasanna |
Compact architecture for high-throughput regular expression matching on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2008, San Jose, California, USA, November 6-7, 2008, pp. 30-39, 2008, ACM, 978-1-60558-346-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
BRAM, FPGA, intrusion detection, finite state machine, regular expression, NFA |
28 | Premysl Sucha, Zdenek Hanzálek, Antonin Hermanek, Jan Schier |
Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 46(1), pp. 35-53, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
imperfectly nested loops, FPGA, high-level synthesis, implementation, integer linear programming, VLSI design, iterative algorithms, cyclic scheduling, blind equalization |
28 | Keith So |
Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 151-158, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
negotiated congestion, routability-driven routing, FPGA |
28 | Fei Xia, Yong Dou |
Reducing Storage Requirements in Accelerating Algorithm of Global BioSequence Alignment on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 7th International Symposium, APPT 2007, Guangzhou, China, November 22-23, 2007, Proceedings, pp. 90-99, 2007, Springer, 978-3-540-76836-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Global BioSequence Alignment, Needleman-Wunsch algorithm, FPGA, Bioinformatics, Hardware Accelerator |
28 | Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede |
Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 323-334, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
exhaustive key search, cryptanalysis, hash-functions, FPGA implementation, time-memory trade-off, rainbow table |
28 | Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer |
An automated exploration framework for FPGA-based soft multiprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 273-278, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
IPv4 packet forwarding, soft multiprocessors, FPGA, design space exploration, integer linear programming |
28 | Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan |
The microarchitecture of FPGA-based soft processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005, pp. 202-212, 2005, ACM, 1-59593-149-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor |
28 | Hui Qin, Tsutomu Sasao, Yukihiro Iguchi |
An FPGA design of AES encryption circuit with 128-bit keys. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 147-151, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
AES encryption, FPGA, pipeline |
28 | Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell |
A New FPGA for DSP Applications Integrating BIST Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(4), pp. 423-431, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hardware test, FPGA, digital signal processing, DSP, BIST, reconfigurable architectures |
28 | Chidamber Kulkarni, Gordon J. Brebner, Graham Schelle |
Mapping a domain specific language to a platform FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 924-927, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
platform FPGA, domain specific language, network processing |
28 | Marcus Bednara, Jürgen Teich |
Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 26(2), pp. 149-165, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
regular processor arrays, FPGA, design automation, space-time mapping |
28 | Seda Ogrenci Memik, Aggelos K. Katsaggelos, Majid Sarrafzadeh |
Analysis and FPGA Implementation of Image Restoration under Resource Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(3), pp. 390-399, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA, image segmentation, image restoration |
28 | Yao-Wen Chang, Kai Zhu 0001, Guang-Ming Wu, D. F. Wong 0001, C. K. Wong |
Analysis of FPGA/FPIC switch modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(1), pp. 11-37, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPIC, FPGA, synthesis, layout, Computer-aided design of VLSI |
28 | Deming Chen, Jason Cong, Yiping Fan |
Low-power high-level synthesis for FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 134-139, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA power reduction, RT-level power estimation, data path optimization |
28 | Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo |
Low-Power FSMs in FPGA: Encoding Alternatives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 363-370, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
One-Hot, State Encod-ing, FPGA, Low-Power, Finite State Machine |
28 | Dylan Carline, Paul Coulton |
Internet Authentication of LUT-Based FPGA Configuration Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Configuration Files, FPGA, Authentication, Bitstream |
28 | Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro C. Diniz |
Coarse-Grain Pipelining on Multiple FPGA Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 77-, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Coarse-grain Pipelining, FPGA-based Custom Computing Machines, Parallelizing Compiler Analysis Techniques |
28 | Dewi Utami, Hadi Suwastio, Bambang Sumadjudin |
FPGA Implementation of Digital Chaotic Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EurAsia-ICT ![In: EurAsia-ICT 2002: Information and Communication Technology, First EurAsian Conference, Shiraz, Iran, October 29-31, 2002, Proceedings, pp. 239-247, 2002, Springer, 3-540-00028-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
digital filter overflow, FPGA, cryptography, Chaos, fixed point |
28 | Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian |
TOF: a tool for test pattern generation optimization of an FPGA application oriented test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 323-328, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG |
28 | Andrzej Krasniewski |
Self-Testing of FPGA Delay Faults in the System Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 40-, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, BIST, random testing, delay faults |
28 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
Minimizing the Number of Test Configurations for Different FPGA Families. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 363-368, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGA, ATPG |
28 | Neil W. Bergmann, Yuk Ying Chung |
Video Compression on FPGA-Based Custom Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (1) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 361-364, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
FPGA-based custom computers, 2D DCT algorithms, Scalable Parallel Architecture for Concurrency Experiments, field programmable gate arrays, field programmable gate array, video compression, experimental result, SPACE, workstation, distributed arithmetic, super-computer, processing speed |
28 | Jie Zhou 0007, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang |
A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 110-122, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Philippe Bonnot 0001, Fabrice Lemonnier, Gilbert Edelin, Gerard Gaillat, Olivier Ruch, Pascal Gauget |
Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 610-615, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Jie Zhou 0007, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong |
Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: 10th IEEE International Conference on High Performance Computing and Communications, HPCC 2008, 25-27 Sept. 2008, Dalian, China, pp. 182-189, 2008, IEEE Computer Society, 978-0-7695-3352-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Hayden Kwok-Hay So, Robert W. Brodersen |
File system access from reconfigurable FPGA hardware processes in BORPH. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 567-570, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Changjian Gao, Shih-Lien Lu |
Novel FPGA based Haar classifier face detection algorithm acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 373-378, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Mingjie Lin, Steve Ferguson, Yaling Ma, Timothy Greene |
HAFT: A hybrid FPGA with amorphous and fault-tolerant architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1348-1351, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai |
PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-6, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Pengyuan Yu, Patrick Schaumont |
Secure FPGA circuits using controlled placement and routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 45-50, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Babak Zamanlooy, Vahid Hamiati Vaghef, Sattar Mirzakuchaki, Ali Shojaee Bakhtiari, Reza Ebrahimi Atani |
A Real Time Infrared Imaging System Based on DSP & FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PSIVT ![In: Advances in Image and Video Technology, Second Pacific Rim Symposium, PSIVT 2007, Santiago, Chile, December 17-19, 2007, Proceedings, pp. 16-23, 2007, Springer, 978-3-540-77128-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
IRFPA, Nonuniformity Detection, Nonuniformity Correction |
28 | Kazuhiro Shimizu, Shinichi Hirai |
Implementing Planar Motion Tracking Algorithms on CMOS+FPGA Vision System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2006 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2006, October 9-15, 2006, Beijing, China, pp. 1366-1371, 2006, IEEE, 1-4244-0258-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Tom Van Court, Martin C. Herbordt |
Sizing of Processing Arrays for FPGA-Based Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan |
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 152-164, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | David Sheldon, Rakesh Kumar 0002, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen |
Application-specific customization of parameterized FPGA soft-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 261-268, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Weiwei Ma, M. E. Kaye, D. M. Luke, R. Doraiswami |
An FPGA-Based Singular Value Decomposition Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1047-1050, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Takashi Morimoto, Hidekazu Adachi, Kousuke Yamaoka, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch |
An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 944-947, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Anurag Tiwari, Karen A. Tomko |
Enhanced reliability of finite-state machines in FPGA through efficient fault detection and correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 54(3), pp. 459-467, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Deepak Rautela, Rajendra S. Katti |
Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 232-237, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu |
LFF algorithm for heterogeneous FPGA floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1123-1126, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Vijay Degalahal, Tim Tuan |
Methodology for high level estimation of FPGA power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 657-660, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Chi-Jeng Chang, Wu-Ting Wu, Hui-Ching Su, Zen-Yi Huang, Hsin-Yen Li |
ARM Based Microcontroller for Image Capturing in FPGA Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVC ![In: Advances in Visual Computing, First International Symposium, ISVC 2005, Lake Tahoe, NV, USA, December 5-7, 2005, Proceedings, pp. 672-677, 2005, Springer, 3-540-30750-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Erno Salminen, Ari Kulmala, Timo D. Hämäläinen |
HIBI-based multiprocessor SoC on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3351-3354, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Ronald F. DeMara, Kening Zhang |
Autonomous FPGA Fault Handling through Competitive Runtime Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June - 1 July 2005, Washington, DC, USA, pp. 109-116, 2005, IEEE Computer Society, 0-7695-2399-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers |
Pel reconstruction on FPGA-augmented TriMedia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(6), pp. 622-635, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | André DeHon, Raphael Rubin |
Design of FPGA interconnect for multilevel metallization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(10), pp. 1038-1050, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Terrence S. T. Mak, Kai-Pui Lam |
On Computing Maximum Likelihood Phylogeny Using FPGA p. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 1188, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Fei Li 0003, Yan Lin 0001, Lei He 0001 |
Vdd programmability to reduce FPGA interconnect power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 760-765, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Ian G. Harris, Russell Tessier |
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11), pp. 1337-1343, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings |
Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 483-492, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Lech Józwiak, Aleksander Slusarczyk |
A New State Assignment Method Targeting FPGA Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 26th EUROMICRO 2000 Conference, Informatics: Inventing the Future, 5-7 September 2000, Maastricht, The Netherlands, pp. 1050-1059, 2000, IEEE Computer Society, 0-7695-0780-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Ian G. Harris, Russell Tessier |
Interconnect testing in cluster-based FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 49-54, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
field-programmable gate arrray, interconnect testing, hierarchical test |
28 | John F. McDonald 0001, Bryan S. Goda |
Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), July 19-21, 1999, Pasadena, CA, USA, pp. 188-192, 1999, IEEE Computer Society, 0-7695-0256-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Vaughn Betz, Jonathan Rose |
Effect of the prefabricated routing track distribution on FPGA area-efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(3), pp. 445-456, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
28 | Philip Heng Wai Leong, P. K. Tsang, T. K. Lee |
A FPGA Based Forth Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 254-255, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
28 | Wen-Jong Fang, Allen C.-H. Wu |
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 518-521, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
28 | Ashutosh Singla, Thomas M. Conte |
Bipartitioning for Hybrid FPGA-Software Simulatio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 211-214, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
28 | Jason Cong, Yuzheng Ding |
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1), pp. 1-12, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
26 | Mahdi Abbaszadeh, Dana L. How |
From Topology to Realization in FPGA/VPR Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 85-96, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang |
A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 185, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Zhigang Wei, Aman Arora, Emily Shriver, Lizy Kurian John |
Cross-FPGA Power Estimation from High Level Synthesis via Transfer-Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 187, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang 0001 |
Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 211-222, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Dongjoon Park, André DeHon |
REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 108-118, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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26 | Thore Gerlach, Stefan Knipp, David Biesner, Stelios Emmanouilidis, Klaus Hauber, Nico Piatkowski |
FPGA-Placement via Quantum Annealing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 43, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Timothy Sherwood |
Security, Synapses, Sustainability, and Superconducting: A Look at Possible Futures for the FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 1, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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26 | Prabhat K. Gupta |
My Fifteen Year Journey of Deploying FPGA Accelerated Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 142, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Zhenyu Xu, Miaoxiang Yu, Jillian Cai, Saddam Gafsi, Judson Douglas Ryckman, Qing Yang 0001, Tao Wei |
An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 119-129, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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26 | Will Lin, Yizhou Shan, Ryan Kosta, Arvind Krishnamurthy, Yiying Zhang 0005 |
SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 130-141, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Sahand Kashani, Mahyar Emami, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus |
A 475 MHz Manycore FPGA Accelerator for RTL Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 78-84, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Andy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao |
Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 33-39, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Yizhao Gao, Baoheng Zhang, Yuhao Ding, Hayden Kwok-Hay So |
A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 246-257, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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26 | Kai Qian, Zheng Liu, Yinqiu Liu, Haodong Lu 0001, Zexu Zhang, Ruiqiu Chen, Kun Wang 0005 |
AutoHammer: Breaking the Compilation Wall Between Deep Neural Network and Overlay-based FPGA Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 185, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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26 | Daniel Gerlinghoff, Benjamin Chen Ming Choong, Rick Siow Mong Goh, Weng-Fai Wong, Tao Luo 0014 |
Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 235-245, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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26 | Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne |
DynaRapid: From C to FPGA in a Few Seconds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024, pp. 40, 2024, ACM. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
26 | Wole Jaiyeoba, Nima Elyasi, Changho Choi, Kevin Skadron |
ACTS: A Near-Memory FPGA Graph Processing Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 79-89, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao |
ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 209-219, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Tim Oberschulte, Jakob Marten, Holger Blume |
Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space Station. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 48, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | Linus Y. Wong, Jialiang Zhang, Jing Jane Li |
DONGLE: Direct FPGA-Orchestrated NVMe Storage for HLS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 3-13, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | Shashwat Shrivastava, Stefan Nikolic 0001, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic |
Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 231, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Emanuele Del Sozzo, Davide Conficconi, Marco D. Santambrogio, Kentaro Sano |
Senju: A Framework for the Design of Highly Parallel FPGA-based Iterative Stencil Loop Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 233, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | Jonathan W. Greene |
FPGA Mux Usage and Routability Estimates without Explicit Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 141-147, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | Jinfeng Li, Yahong Rosa Zheng |
FPGA Acceleration for Successive Interference Cancellation in Severe Multipath Acoustic Communication Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 233, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Longfei Fan, Chang Wu |
FPGA Technology Mapping with Adaptive Gate Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 135-140, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | Chaoqiang Liu, Haifeng Liu 0003, Long Zheng 0003, Yu Huang 0013, Xiangyu Ye, Xiaofei Liao, Hai Jin 0001 |
FNNG: A High-Performance FPGA-based Accelerator for K-Nearest Neighbor Graph Construction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 67-77, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | Kaveh Aasaraai, Emanuele Cesena, Rahul Maganti, Nicolas Stalder, Javier Varela, Kevin Bowers |
Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 47, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | Ruiqi Chen, Haoyang Zhang, Yuhanxiao Ma, Enhao Tang, Shun Li, Yanxiang Zhu, Jun Yu 0010, Kun Wang 0005 |
Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 49, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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26 | Zhenyu Xu, Miaoxiang Yu, Qing Yang 0001, Yeonho Jeong, Tao Wei |
A Novel FPGA Simulator Accelerating Reinforcement Learning-Based Design of Power Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 51, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
26 | Andrew David Gunter, Steven J. E. Wilton |
Towards a Machine Learning Approach to Predicting the Difficulty of FPGA Routing Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023, pp. 231, 2023, ACM, 978-1-4503-9417-8. The full citation details ...](Pics/full.jpeg) |
2023 |
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