Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	Yao-Wen Chang, D. F. Wong 0001, C. K. Wong	Design and analysis of FPGA/FPIC switch modules.	ICCD	1995	DBLP DOI BibTeX RDF	FPGA/FPIC switch modules, routing resources, FPIC, network-flow techniques, field programmable interconnect chip, field programmable gate arrays, FPGA, field programmable gate arrays, logic design, heuristic algorithm, programmable logic arrays, routability
28	Atabak Mahram, Martin C. Herbordt	Fast and accurate NCBI BLASTP: acceleration with multiphase FPGA-based prefiltering.	ICS	2010	DBLP DOI BibTeX RDF	FPGA-based coprocessors, high performance reconfigurable computing, bioinformatics, biological sequence alignment
28	Yibo Chen, Jishen Zhao, Yuan Xie 0001	3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory.	ISLPED	2010	DBLP DOI BibTeX RDF	non-volatile FPGA, phase-change memory, 3D IC
28	Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson 0001, Krste Asanovic	RAMP gold: an FPGA-based architecture simulator for multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	simulation, FPGA, multiprocessors
28	Yi Zhu 0002, Yuanfang Hu, Michael B. Taylor, Chung-Kuan Cheng	Energy and switch area optimizations for FPGA global routing architectures.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, low power, global routing
28	René Müller 0001, Jens Teubner	FPGA: what's in it for a database?	SIGMOD Conference	2009	DBLP DOI BibTeX RDF	data processing vlsi, fpga, hardware acceleration
28	Scott Cromar, Jaeho Lee, Deming Chen	FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation.	DAC	2009	DBLP DOI BibTeX RDF	glitch power, FPGA, high-level synthesis, power reduction
28	Jianbin Huang, Zongwu Xie, Hong Liu 0002, Kai Sun, Yechao Liu, Zainan Jiang	DSP/FPGA-based Controller Architecture for Flexible Joint Robot with Enhanced Impedance Performance.	J. Intell. Robotic Syst.	2008	DBLP DOI BibTeX RDF	M-LVDS serial data bus, Torque ripple, FPGA, DSP, Impedance control, Flexible joint
28	Kanupriya Gulati, Sunil P. Khatri	Improving FPGA routability using network coding.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	FPGA, network coding
28	In-Kwon Park, Jung-Hyun Kim 0006, Kwang-Seok Hong	An implementation of an FPGA-based embedded gesture recognizer using a data glove.	ICUIMC	2008	DBLP DOI BibTeX RDF	FPGA, VHDL, gesture recognition
28	Camel Tanougast, Serge Weber, Gilles Millerioux, Jamal Daafouz, Ahmed Bouridane	VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher.	DELTA	2008	DBLP DOI BibTeX RDF	Cryptography system, self-synchronising stream cipher, FPGA, VLSI design
28	Shrutisagar Chandrasekaran, Abbes Amira	High Performance FPGA Implementation of the Mersenne Twister.	DELTA	2008	DBLP DOI BibTeX RDF	RC1000, FPGA, Mersenne Twister, Handel C
28	Yi-Hua E. Yang, Weirong Jiang, Viktor K. Prasanna	Compact architecture for high-throughput regular expression matching on FPGA.	ANCS	2008	DBLP DOI BibTeX RDF	BRAM, FPGA, intrusion detection, finite state machine, regular expression, NFA
28	Premysl Sucha, Zdenek Hanzálek, Antonin Hermanek, Jan Schier	Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	imperfectly nested loops, FPGA, high-level synthesis, implementation, integer linear programming, VLSI design, iterative algorithms, cyclic scheduling, blind equalization
28	Keith So	Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space.	ISPD	2007	DBLP DOI BibTeX RDF	negotiated congestion, routability-driven routing, FPGA
28	Fei Xia, Yong Dou	Reducing Storage Requirements in Accelerating Algorithm of Global BioSequence Alignment on FPGA.	APPT	2007	DBLP DOI BibTeX RDF	Global BioSequence Alignment, Needleman-Wunsch algorithm, FPGA, Bioinformatics, Hardware Accelerator
28	Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking.	ARC	2006	DBLP DOI BibTeX RDF	exhaustive key search, cryptanalysis, hash-functions, FPGA implementation, time-memory trade-off, rainbow table
28	Yujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer	An automated exploration framework for FPGA-based soft multiprocessor systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	IPv4 packet forwarding, soft multiprocessors, FPGA, design space exploration, integer linear programming
28	Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan	The microarchitecture of FPGA-based soft processors.	CASES	2005	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor
28	Hui Qin, Tsutomu Sasao, Yukihiro Iguchi	An FPGA design of AES encryption circuit with 128-bit keys.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	AES encryption, FPGA, pipeline
28	Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell	A New FPGA for DSP Applications Integrating BIST Capabilities.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	hardware test, FPGA, digital signal processing, DSP, BIST, reconfigurable architectures
28	Chidamber Kulkarni, Gordon J. Brebner, Graham Schelle	Mapping a domain specific language to a platform FPGA.	DAC	2004	DBLP DOI BibTeX RDF	platform FPGA, domain specific language, network processing
28	Marcus Bednara, Jürgen Teich	Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	regular processor arrays, FPGA, design automation, space-time mapping
28	Seda Ogrenci Memik, Aggelos K. Katsaggelos, Majid Sarrafzadeh	Analysis and FPGA Implementation of Image Restoration under Resource Constraints.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	FPGA, image segmentation, image restoration
28	Yao-Wen Chang, Kai Zhu 0001, Guang-Ming Wu, D. F. Wong 0001, C. K. Wong	Analysis of FPGA/FPIC switch modules.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	FPIC, FPGA, synthesis, layout, Computer-aided design of VLSI
28	Deming Chen, Jason Cong, Yiping Fan	Low-power high-level synthesis for FPGA architectures.	ISLPED	2003	DBLP DOI BibTeX RDF	FPGA power reduction, RT-level power estimation, data path optimization
28	Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo	Low-Power FSMs in FPGA: Encoding Alternatives.	PATMOS	2002	DBLP DOI BibTeX RDF	One-Hot, State Encod-ing, FPGA, Low-Power, Finite State Machine
28	Dylan Carline, Paul Coulton	Internet Authentication of LUT-Based FPGA Configuration Files.	IPDPS	2002	DBLP DOI BibTeX RDF	Configuration Files, FPGA, Authentication, Bitstream
28	Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro C. Diniz	Coarse-Grain Pipelining on Multiple FPGA Architectures.	FCCM	2002	DBLP DOI BibTeX RDF	Coarse-grain Pipelining, FPGA-based Custom Computing Machines, Parallelizing Compiler Analysis Techniques
28	Dewi Utami, Hadi Suwastio, Bambang Sumadjudin	FPGA Implementation of Digital Chaotic Cryptography.	EurAsia-ICT	2002	DBLP DOI BibTeX RDF	digital filter overflow, FPGA, cryptography, Chaos, fixed point
28	Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	TOF: a tool for test pattern generation optimization of an FPGA application oriented test.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	TOF tool, test pattern generation optimization, FPGA application oriented test, application-oriented test procedure, RAM-based FPGAs, AC nonredundant fault coverage, circuit netlist, TPG optimisation tool, field programmable gate arrays, logic testing, optimisation, integrated circuit testing, automatic test pattern generation, ATPG
28	Andrzej Krasniewski	Self-Testing of FPGA Delay Faults in the System Environment.	IOLTW	2000	DBLP DOI BibTeX RDF	FPGA, BIST, random testing, delay faults
28	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	Minimizing the Number of Test Configurations for Different FPGA Families.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	FPGA, ATPG
28	Neil W. Bergmann, Yuk Ying Chung	Video Compression on FPGA-Based Custom Computers.	ICIP (1)	1997	DBLP DOI BibTeX RDF	FPGA-based custom computers, 2D DCT algorithms, Scalable Parallel Architecture for Concurrency Experiments, field programmable gate arrays, field programmable gate array, video compression, experimental result, SPACE, workstation, distributed arithmetic, super-computer, processing speed
28	Jie Zhou 0007, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang	A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA.	APPT	2009	DBLP DOI BibTeX RDF
28	Philippe Bonnot 0001, Fabrice Lemonnier, Gilbert Edelin, Gerard Gaillat, Olivier Ruch, Pascal Gauget	Definition and SIMD Implementation of a Multi-Processing Architecture Approach on FPGA.	DATE	2008	DBLP DOI BibTeX RDF
28	Jie Zhou 0007, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong	Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.	HPCC	2008	DBLP DOI BibTeX RDF
28	Hayden Kwok-Hay So, Robert W. Brodersen	File system access from reconfigurable FPGA hardware processes in BORPH.	FPL	2008	DBLP DOI BibTeX RDF
28	Changjian Gao, Shih-Lien Lu	Novel FPGA based Haar classifier face detection algorithm acceleration.	FPL	2008	DBLP DOI BibTeX RDF
28	Mingjie Lin, Steve Ferguson, Yaling Ma, Timothy Greene	HAFT: A hybrid FPGA with amorphous and fault-tolerant architecture.	ISCAS	2008	DBLP DOI BibTeX RDF
28	Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai	PROToFLEX: FPGA-accelerated Hybrid Functional Simulator.	IPDPS	2007	DBLP DOI BibTeX RDF
28	Pengyuan Yu, Patrick Schaumont	Secure FPGA circuits using controlled placement and routing.	CODES+ISSS	2007	DBLP DOI BibTeX RDF
28	Babak Zamanlooy, Vahid Hamiati Vaghef, Sattar Mirzakuchaki, Ali Shojaee Bakhtiari, Reza Ebrahimi Atani	A Real Time Infrared Imaging System Based on DSP & FPGA.	PSIVT	2007	DBLP DOI BibTeX RDF	IRFPA, Nonuniformity Detection, Nonuniformity Correction
28	Kazuhiro Shimizu, Shinichi Hirai	Implementing Planar Motion Tracking Algorithms on CMOS+FPGA Vision System.	IROS	2006	DBLP DOI BibTeX RDF
28	Tom Van Court, Martin C. Herbordt	Sizing of Processing Arrays for FPGA-Based Computation.	FPL	2006	DBLP DOI BibTeX RDF
28	Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan	Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths.	FCCM	2006	DBLP DOI BibTeX RDF
28	David Sheldon, Rakesh Kumar 0002, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen	Application-specific customization of parameterized FPGA soft-core processors.	ICCAD	2006	DBLP DOI BibTeX RDF
28	Weiwei Ma, M. E. Kaye, D. M. Luke, R. Doraiswami	An FPGA-Based Singular Value Decomposition Processor.	CCECE	2006	DBLP DOI BibTeX RDF
28	Takashi Morimoto, Hidekazu Adachi, Kousuke Yamaoka, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch	An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture.	APCCAS	2006	DBLP DOI BibTeX RDF
28	Anurag Tiwari, Karen A. Tomko	Enhanced reliability of finite-state machines in FPGA through efficient fault detection and correction.	IEEE Trans. Reliab.	2005	DBLP DOI BibTeX RDF
28	Deepak Rautela, Rajendra S. Katti	Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources.	ISVLSI	2005	DBLP DOI BibTeX RDF
28	Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu	LFF algorithm for heterogeneous FPGA floorplanning.	ASP-DAC	2005	DBLP DOI BibTeX RDF
28	Vijay Degalahal, Tim Tuan	Methodology for high level estimation of FPGA power consumption.	ASP-DAC	2005	DBLP DOI BibTeX RDF
28	Chi-Jeng Chang, Wu-Ting Wu, Hui-Ching Su, Zen-Yi Huang, Hsin-Yen Li	ARM Based Microcontroller for Image Capturing in FPGA Design.	ISVC	2005	DBLP DOI BibTeX RDF
28	Erno Salminen, Ari Kulmala, Timo D. Hämäläinen	HIBI-based multiprocessor SoC on FPGA.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
28	Ronald F. DeMara, Kening Zhang	Autonomous FPGA Fault Handling through Competitive Runtime Reconfiguration.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
28	Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	Pel reconstruction on FPGA-augmented TriMedia.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
28	André DeHon, Raphael Rubin	Design of FPGA interconnect for multilevel metallization.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
28	Terrence S. T. Mak, Kai-Pui Lam	On Computing Maximum Likelihood Phylogeny Using FPGA p.	FPL	2004	DBLP DOI BibTeX RDF
28	Fei Li 0003, Yan Lin 0001, Lei He 0001	Vdd programmability to reduce FPGA interconnect power.	ICCAD	2004	DBLP DOI BibTeX RDF
28	Ian G. Harris, Russell Tessier	Testing and diagnosis of interconnect faults in cluster-based FPGA architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
28	Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings	Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification.	FPL	2001	DBLP DOI BibTeX RDF
28	Lech Józwiak, Aleksander Slusarczyk	A New State Assignment Method Targeting FPGA Implementations.	EUROMICRO	2000	DBLP DOI BibTeX RDF
28	Ian G. Harris, Russell Tessier	Interconnect testing in cluster-based FPGA architectures.	DAC	2000	DBLP DOI BibTeX RDF	field-programmable gate arrray, interconnect testing, hierarchical test
28	John F. McDonald 0001, Bryan S. Goda	Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
28	Vaughn Betz, Jonathan Rose	Effect of the prefabricated routing track distribution on FPGA area-efficiency.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
28	Philip Heng Wai Leong, P. K. Tsang, T. K. Lee	A FPGA Based Forth Microprocessor.	FCCM	1998	DBLP DOI BibTeX RDF
28	Wen-Jong Fang, Allen C.-H. Wu	Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy.	DAC	1997	DBLP DOI BibTeX RDF
28	Ashutosh Singla, Thomas M. Conte	Bipartitioning for Hybrid FPGA-Software Simulatio.	VLSI Design	1996	DBLP DOI BibTeX RDF
28	Jason Cong, Yuzheng Ding	FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
26	Mahdi Abbaszadeh, Dana L. How	From Topology to Realization in FPGA/VPR Routing.	FPGA	2024	DBLP DOI BibTeX RDF
26	Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang	A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs.	FPGA	2024	DBLP DOI BibTeX RDF
26	Zhigang Wei, Aman Arora, Emily Shriver, Lizy Kurian John	Cross-FPGA Power Estimation from High Level Synthesis via Transfer-Learning.	FPGA	2024	DBLP DOI BibTeX RDF
26	Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang 0001	Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis.	FPGA	2024	DBLP DOI BibTeX RDF
26	Dongjoon Park, André DeHon	REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs.	FPGA	2024	DBLP DOI BibTeX RDF
26	Thore Gerlach, Stefan Knipp, David Biesner, Stelios Emmanouilidis, Klaus Hauber, Nico Piatkowski	FPGA-Placement via Quantum Annealing.	FPGA	2024	DBLP DOI BibTeX RDF
26	Timothy Sherwood	Security, Synapses, Sustainability, and Superconducting: A Look at Possible Futures for the FPGA.	FPGA	2024	DBLP DOI BibTeX RDF
26	Prabhat K. Gupta	My Fifteen Year Journey of Deploying FPGA Accelerated Solutions.	FPGA	2024	DBLP DOI BibTeX RDF
26	Zhenyu Xu, Miaoxiang Yu, Jillian Cai, Saddam Gafsi, Judson Douglas Ryckman, Qing Yang 0001, Tao Wei	An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits.	FPGA	2024	DBLP DOI BibTeX RDF
26	Will Lin, Yizhou Shan, Ryan Kosta, Arvind Krishnamurthy, Yiying Zhang 0005	SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC.	FPGA	2024	DBLP DOI BibTeX RDF
26	Sahand Kashani, Mahyar Emami, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus	A 475 MHz Manycore FPGA Accelerator for RTL Simulation.	FPGA	2024	DBLP DOI BibTeX RDF
26	Andy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao	Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine.	FPGA	2024	DBLP DOI BibTeX RDF
26	Yizhao Gao, Baoheng Zhang, Yuhao Ding, Hayden Kwok-Hay So	A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA.	FPGA	2024	DBLP DOI BibTeX RDF
26	Kai Qian, Zheng Liu, Yinqiu Liu, Haodong Lu 0001, Zexu Zhang, Ruiqiu Chen, Kun Wang 0005	AutoHammer: Breaking the Compilation Wall Between Deep Neural Network and Overlay-based FPGA Accelerator.	FPGA	2024	DBLP DOI BibTeX RDF
26	Daniel Gerlinghoff, Benjamin Chen Ming Choong, Rick Siow Mong Goh, Weng-Fai Wong, Tao Luo 0014	Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic.	FPGA	2024	DBLP DOI BibTeX RDF
26	Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne	DynaRapid: From C to FPGA in a Few Seconds.	FPGA	2024	DBLP DOI BibTeX RDF
26	Wole Jaiyeoba, Nima Elyasi, Changho Choi, Kevin Skadron	ACTS: A Near-Memory FPGA Graph Processing Framework.	FPGA	2023	DBLP DOI BibTeX RDF
26	Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao	ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration.	FPGA	2023	DBLP DOI BibTeX RDF
26	Tim Oberschulte, Jakob Marten, Holger Blume	Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space Station.	FPGA	2023	DBLP DOI BibTeX RDF
26	Linus Y. Wong, Jialiang Zhang, Jing Jane Li	DONGLE: Direct FPGA-Orchestrated NVMe Storage for HLS.	FPGA	2023	DBLP DOI BibTeX RDF
26	Shashwat Shrivastava, Stefan Nikolic 0001, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic	Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing.	FPGA	2023	DBLP DOI BibTeX RDF
26	Emanuele Del Sozzo, Davide Conficconi, Marco D. Santambrogio, Kentaro Sano	Senju: A Framework for the Design of Highly Parallel FPGA-based Iterative Stencil Loop Accelerators.	FPGA	2023	DBLP DOI BibTeX RDF
26	Jonathan W. Greene	FPGA Mux Usage and Routability Estimates without Explicit Routing.	FPGA	2023	DBLP DOI BibTeX RDF
26	Jinfeng Li, Yahong Rosa Zheng	FPGA Acceleration for Successive Interference Cancellation in Severe Multipath Acoustic Communication Channels.	FPGA	2023	DBLP DOI BibTeX RDF
26	Longfei Fan, Chang Wu	FPGA Technology Mapping with Adaptive Gate Decomposition.	FPGA	2023	DBLP DOI BibTeX RDF
26	Chaoqiang Liu, Haifeng Liu 0003, Long Zheng 0003, Yu Huang 0013, Xiangyu Ye, Xiaofei Liao, Hai Jin 0001	FNNG: A High-Performance FPGA-based Accelerator for K-Nearest Neighbor Graph Construction.	FPGA	2023	DBLP DOI BibTeX RDF
26	Kaveh Aasaraai, Emanuele Cesena, Rahul Maganti, Nicolas Stalder, Javier Varela, Kevin Bowers	Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms.	FPGA	2023	DBLP DOI BibTeX RDF
26	Ruiqi Chen, Haoyang Zhang, Yuhanxiao Ma, Enhao Tang, Shun Li, Yanxiang Zhu, Jun Yu 0010, Kun Wang 0005	Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks.	FPGA	2023	DBLP DOI BibTeX RDF
26	Zhenyu Xu, Miaoxiang Yu, Qing Yang 0001, Yeonho Jeong, Tao Wei	A Novel FPGA Simulator Accelerating Reinforcement Learning-Based Design of Power Converters.	FPGA	2023	DBLP DOI BibTeX RDF
26	Andrew David Gunter, Steven J. E. Wilton	Towards a Machine Learning Approach to Predicting the Difficulty of FPGA Routing Problems.	FPGA	2023	DBLP DOI BibTeX RDF