Search results for "SRAM"

Hits ?▲	Authors	Title	Venue	Year	Link
11	Sheng-Yu Peng, I-Chun Liu, Yi-Heng Wu, Ting-Ju Lin, Chun-Jui Chen, Xiu-Zhu Li, Yong-Qi Cheng, Pin-Han Lin, Kuo-Hsuan Hung, Yu Tsao 0001	An SRAM-Based Reconfigurable Cognitive Computation Matrix for Sensor Edge Applications.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
11	Fei Tan, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak	A 0.05-mm2 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
11	Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang	A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
11	Jeongkyun Kim, Byungho Yook, Youngo Lee, Taemin Choi, Kyuwon Choi, Chanho Lee, Juchang Lee, Hyeongcheol Kim, Seok Yun, Changhoon Do, Minwoo Kwak, Mijoung Kim, Yunrong Li, Hoyoung Tang, Jaeyoung Kim, Inhak Lee, Dongwook Seo, Sangyeop Baeck	A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
11	Courtney Golden, Dan Ilan, Caroline Huang, Niansong Zhang, Zhiru Zhang, Christopher Batten	Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator.	IEEE Comput. Archit. Lett.	2024	DBLP DOI BibTeX RDF
11	Dain Chon, Woong Choi	Hardware Efficient Transposable 8T SRAM for Orthogonal Data Access.	IEEE Access	2024	DBLP DOI BibTeX RDF
11	Keun-Yong Chung, Honggu Kim, Yerim An, Kiho Seong, Dong-Hyun Shin, Kwang-Hyun Baek, Yong Shim	8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation.	IEEE Access	2024	DBLP DOI BibTeX RDF
11	Zupei Gu, Shukao Dou, Heng You, Yi Zhan, Shushan Qiao, Yumei Zhou	A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks.	IEEE Access	2024	DBLP DOI BibTeX RDF
11	Zhuojun Chen, Wenhao Yang, Jinghang Chen, Zujun Wang, Ding Ding	Improving Radiation Reliability of SRAM-Based Physical Unclonable Function With Self-Healing and Pre-Irradiation Masking Techniques.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
11	Shiwei Liu, Chen Mu, Hao Jiang, Yunzhengmao Wang, Jinshan Zhang 0006, Feng Lin, Keji Zhou, Qi Liu 0010, Chixiao Chen	HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
11	Na Bai, Xin Xiao, Yaohua Xu, Yi Wang, Liang Wang, Xinjie Zhou	Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
11	Chao-Yu Chen, Yan-Siou Dai, Hao-Chiao Hong	A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
11	Narendra Singh Dhakad, Eshika Chittora, Gopal Raut, Vishal Sharma, Santosh Kumar Vishvakarma	In-Memory Computing with 6T SRAM for Multi-operator Logic Design.	Circuits Syst. Signal Process.	2024	DBLP DOI BibTeX RDF
11	M. Elangovan, Kulbhushan Sharma, Ashish Sachdeva, Lipika Gupta	Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications.	Circuits Syst. Signal Process.	2024	DBLP DOI BibTeX RDF
11	Xin Qiao, Qingyu Guo, Xiyuan Tang, Jiahao Song, Renjie Wei, Meng Li 0004, Runsheng Wang, Yuan Wang 0001	A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
11	Heng You, Weijun Li, Delong Shang, Yumei Zhou, Shushan Qiao	A 1-8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
11	Qingyu Guo, Nanbing Pan, Xin Qiao, Xiaoxin Cui, Yuan Wang 0001	OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
11	Xiaoyong Song, Zhichuan Guo	Fast Update Algorithm With Reorder Mechanism for SRAM-Based Longest Prefix Matching on FPGA.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
11	Young Kyu Lee, Dong Han Ko, Seokhee Cho, Minjune Yeo, Mingu Kang, Seong-Ook Jung	Split WL 6T SRAM-Based Bit Serial Computing-in-Memory Macro With High Signal Margin and High Throughput.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
11	Feng Wei, Xiaole Cui, Sunrui Zhang, Xing Zhang	An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
11	Jian-Wei Su, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang	8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
11	Yuanyuan Han, Xu Cheng 0002, Xiaoyong Xue, Jun Han 0003, Jiawei Xu 0001, Xiaoyang Zeng	SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
11	Li Ni, Pengjun Wang, Yuejun Zhang, Xiangyu Li, Gang Li, Lin Ding, Jiliang Zhang 0002	SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
11	Inseong Jeon, Hyunho Park, Taehwan Yoon, Hanwool Jeong	High Efficiency Variation-Aware SRAM Timing Characterization via Machine-Learning-Assisted Netlist Extraction.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
11	Shams-Ul-Haq, Vijay Kumar Sharma	Improved Stability for Robust and Low-Power SRAM Cell Using FinFET Technology.	J. Circuits Syst. Comput.	2024	DBLP DOI BibTeX RDF
11	P. Nagarajan, M. Renuga, A. Manikandan, S. Dhanasekaran	Design and Simulation of a Novel 16T SRAM Cell for Low Power Memory Architecture.	J. Circuits Syst. Comput.	2024	DBLP DOI BibTeX RDF
11	Cenlin Duan, Jianlei Yang 0001, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao	DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
11	Chenghu Dai, Zihua Ren, Lijun Guan, Haitao Liu, Mengya Gao, Wenjuan Lu, Zhiyong Pang, Chunyu Peng, Xiulong Wu	A 9T-SRAM in-memory computing macro for Boolean logic and multiply-and-accumulate operations.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
11	Jianqing Liu, Na Gong, Hritom Das	Two Birds with One Stone: Differential Privacy by Low-power SRAM Memory.	CoRR	2024	DBLP DOI BibTeX RDF
11	Léopold Van Brandt, Denis Flandre, Jean-Charles Delvenne	Stochastic Nonlinear Dynamical Modelling of SRAM Bitcells in Retention Mode.	CoRR	2024	DBLP DOI BibTeX RDF
11	Ioanna Souvatzoglou, Athanasios Papadimitriou, Aitzan Sari, Vasileios Vlagkoulis, Mihalis Psarakis	Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs.	CoRR	2024	DBLP DOI BibTeX RDF
11	Jonathan Ku, Junyao Zhang, Haoxuan Shan, Saichand Samudrala, Jiawen Wu, Qilin Zheng, Ziru Li, J. V. Rajendran 0001, Yiran Chen 0001	ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM.	CoRR	2024	DBLP DOI BibTeX RDF
11	Léopold Van Brandt, Jean-Charles Delvenne, Denis Flandre	Variability-Aware Noise-Induced Dynamic Instability of Ultra-Low-Voltage SRAM Bitcells.	CoRR	2024	DBLP DOI BibTeX RDF
11	Courtney Golden, Dan Ilan, Nicholas Cebry, Christopher Batten	Accelerating Seed Location Filtering in DNA Read Mapping Using a Commercial Compute-in-SRAM Architecture.	CoRR	2024	DBLP DOI BibTeX RDF
11	Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, Sebastia Bota, Jaume Segura 0001	SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results.	CoRR	2024	DBLP DOI BibTeX RDF
11	Zain Ul Abideen 0002, Rui Wang, Tiago Diadami Perez, Geert Jan Schrijen, Samuel Pagliarini	Impact of Orientation on the Bias of SRAM-Based PUFs.	IEEE Des. Test	2024	DBLP DOI BibTeX RDF
11	Léopold Van Brandt, Jean-Charles Delvenne, Denis Flandre	Variability-Aware Noise-Induced Dynamic Instability of Ultra-Low-Voltage SRAM Bitcells.	LASCAS	2024	DBLP DOI BibTeX RDF
11	Jooyoung Bae, Chaeyun Shim, Bongjin Kim	15.6 e-Chimera: A Scalable SRAM-Based Ising Macro with Enhanced-Chimera Topology for Solving Combinatorial Optimization Problems Within Memory.	ISSCC	2024	DBLP DOI BibTeX RDF
11	Linfang Wang, Weizeng Li, Zhidao Zhou, Hanghang Gao, Zhi Li, Wang Ye, Hongyang Hu, Jing Liu, Jinshan Yue, Jianguo Yang, Qing Luo, Chunmeng Dou, Qi Liu, Ming Liu	34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process.	ISSCC	2024	DBLP DOI BibTeX RDF
11	Yiyang Yuan, Yiming Yang, Xinghua Wang, Xiaoran Li, Cailian Ma, Qirui Chen, Meini Tang, Xi Wei, Zhixian Hou, Jialiang Zhu, Hao Wu, Qirui Ren, Guozhong Xing, Pui-In Mak, Feng Zhang 0014	34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC.	ISSCC	2024	DBLP DOI BibTeX RDF
11	Daeyeon Kim, Yusung Kim 0002, Ayush Shrivastava, Gyusung Park, Anandkumar Mahadevan Pillai, Kunal Bannore, Tri Doan, Muktadir Rahman, Gwanghyeon Baek, Clifford Ong, Xiaofei Wang, Zheng Guo, Eric Karl	15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia.	ISSCC	2024	DBLP DOI BibTeX RDF
11	Masaru Haraguchi, Yorinobu Fujino, Yoshisato Yokoyama, Ming-Hung Chang, Yu-Hao Hsu, Hong-Chen Cheng, Koji Nii, Yih Wang, Tsung-Yung Jonathan Chang	15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.	ISSCC	2024	DBLP DOI BibTeX RDF
11	Fei Tan, Wei-Han Yu, Jinhai Lin, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak	17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM.	ISSCC	2024	DBLP DOI BibTeX RDF
11	Minjune Yeo, Keonhee Cho, Giseok Kim, Won Joon Jo, Jisang Oh, Sekeon Kim, Kyeongrim Baek, Sungho Park, Seung Jae Yei, Seong-Ook Jung	15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node.	ISSCC	2024	DBLP DOI BibTeX RDF
11	Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee, Xiaochen Peng, Vineet Joshi, Chao-Kai Chuang, Shu-Huan Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Yen-Chien Lai, Chia-Fu Lee, Tan-Li Chou, Kerem Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang	34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell.	ISSCC	2024	DBLP DOI BibTeX RDF
11	Hossein Khosravi, Ricardo Carmona-Galán, Jorge Fernández-Berni, Nabeeh Kandalaft	A novel 10T SRAM bit-cell with high static noise margin and low power consumption for binary In-Memory Computing.	CCWC	2024	DBLP DOI BibTeX RDF
11	Trevor Ridley, Julius Andrade, Cristian Luna, Hayssam El-Razouk	Smart Car Temperature Monitoring System Using SRAM-Based PUF Sensor.	CCWC	2024	DBLP DOI BibTeX RDF
11	Srujana Krishnamurthy Pillay	A 0.8V, Tri-State Inverter based SRAM Cell for SoC Applications.	VLSID	2024	DBLP DOI BibTeX RDF
11	Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy	A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range.	VLSID	2024	DBLP DOI BibTeX RDF
11	Kailash Prasad, Neel Shah, Jinay Dagli, Joycee Mekie	SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space.	VLSID	2024	DBLP DOI BibTeX RDF
11	Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Dan Lake, Brent R. Carlton	A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
11	Zhiting Lin, Zhongzhen Tong, Fangming Wang, Jin Zhang, Yue Zhao, Peng Sun, Tian Xu, Cheng Zhang, Xingwei Li, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao 0007, Junning Chen	In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
11	Rishabh Sehgal, Tanmay Thareja, Shanshan Xie, Can Ni, Jaydeep P. Kulkarni	A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
11	Yusung Kim 0002, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl	Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
11	Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang	A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
11	Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi	Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
11	Adrian Kneip, Martin Lefebvre 0002, Julien Verecken, David Bol	IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
11	Moon-Seok Kim, Sungho Kim, Sang-Kyung Yoo, Bong-Soo Lee, Ji-Man Yu, Il-Woong Tcho, Yang-Kyu Choi	Error reduction of SRAM-based physically unclonable function for chip authentication.	Int. J. Inf. Sec.	2023	DBLP DOI BibTeX RDF
11	Shelja Kaushal, Ashwani K. Rana	Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell.	Integr.	2023	DBLP DOI BibTeX RDF
11	Shuo Cai, Yan Wen, Caicai Xie, Weizheng Wang, Fei Yu 0009	Low-power and high-speed SRAM cells for double-node-upset recovery.	Integr.	2023	DBLP DOI BibTeX RDF
11	Liang Pang, Ziqi Wang, Rui Shi, Mengyun Yao, Xiao Shi, Hao Yan 0002, Longxin Shi	An efficient SRAM yield analysis method based on scaled-sigma adaptive importance sampling with meta-model accelerated.	Integr.	2023	DBLP DOI BibTeX RDF
11	Helen-Maria Dounavi, Yiorgos Tsiatouhas	An aging monitoring scheme for SRAM decoders.	Integr.	2023	DBLP DOI BibTeX RDF
11	Na Bai, Yueliang Zhou, Yaohua Xu, Yi Wang, Zihan Chen	Highly stable soft-error immune SRAM with multi-node upset recovery for aerospace applications.	Integr.	2023	DBLP DOI BibTeX RDF
11	Yu Xie, Tingting Qiao, Yizhuang Xie, He Chen	Soft error mitigation and recovery of SRAM-based FPGAs using brain-inspired hybrid-grained scrubbing mechanism.	Frontiers Comput. Neurosci.	2023	DBLP DOI BibTeX RDF
11	Mukku Pavan Kumar, Rohit Lorenzo	Double Node Upset Immune RHBD-14T SRAM Cell for Space and Satellite Applications.	IEEE Access	2023	DBLP DOI BibTeX RDF
11	Soumitra Pal 0002, Gajendranath Chowdary, Wing-Hung Ki, Chi-Ying Tsui	Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications.	IEEE Access	2023	DBLP DOI BibTeX RDF
11	Gadarapulla Rasheed, Sriadibhatla Sridevi	Design of 7T SRAM Using InGaAs-Dual Pocket-Dual Gate-Tunnel FET for IoT Applications.	IEEE Access	2023	DBLP DOI BibTeX RDF
11	Amit Kama, Michael Amar, Snir Gaaton, Kang Wang, Yifan Tu, Yossi Oren	Juliet-PUF: Enhancing the Security of IoT-Based SRAM-PUFs Using the Remanence Decay Effect.	IEEE Internet Things J.	2023	DBLP DOI BibTeX RDF
11	Zeinab Seifoori, Behzad Omidi, Hossein Asadi 0001	PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
11	Yicong Zhang, Mingyu Wang, Yangzhan Mai, Zhiyi Yu	TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
11	Zhuojun Chen, Ming Wu, Yifeng Zhou, Renlong Li, Jinzhe Tan, Ding Ding	PUF-CIM: SRAM-Based Compute-In-Memory With Zero Bit-Error-Rate Physical Unclonable Function for Lightweight Secure Edge Computing.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
11	Yuqi Wang, Shen Zhang, Yifei Li, Jian Chen, Wenfeng Zhao, Yajun Ha	A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
11	Zhiting Lin, Shaoying Zhang, Qian Jin, Jianping Xia, Yunwei Liu, Kefeng Yu, Jian Zheng, Xiaoming Xu, Xing Fan, Ke Li, Zhongzhen Tong, Xiulong Wu, Wenjuan Lu, Chunyu Peng, Qiang Zhao 0007	A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
11	Ihsan Çiçek, Ahmad Alkhas	A new read-write collision-based SRAM PUF implemented on Xilinx FPGAs.	J. Cryptogr. Eng.	2023	DBLP DOI BibTeX RDF
11	Ayush Dahiya, Poornima Mittal, Rajesh Rohilla	Variation-Tolerant Sense Amplifier Using Decoupling Transistors for Enhanced SRAM Read Performance.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
11	Anil Kumar Rajput, Alok Kumar Tiwari, Manisha Pattanaik	An Energy-Efficient Hybrid SRAM-Based In-Memory Computing Macro for Artificial Intelligence Edge Devices.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
11	Erfan Abbasian, Bahare Grailoo, Mahdieh Nayeri	Design of a 10-nm FinFET 11 T Near-Threshold SRAM Cell for Low-Energy Internet-of-Things Applications.	Circuits Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
11	Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose	A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process.	IET Circuits Devices Syst.	2023	DBLP DOI BibTeX RDF
11	Jaehyun Park, Sangheon Lee 0005, Hanwool Jeong	Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Shivendra Singh Parihar, Victor M. van Santen, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch	Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Junseo Lee, Jihwan Park, Seokhun Kim, Hanwool Jeong	Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Kaili Zhang, Deming Zhang, Mingyang Song, Zhipeng Guo 0006, You Wang 0002, Chengzhi Wang, Yue Zhang 0010, Lang Zeng	A Novel 9T1C-SRAM Compute-In-Memory Macro With Count-Less Pulse-Width Modulation Input and ADC-Less Charge-Integration-Count Output.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Zhen Gao 0005, Jiajun Xiao, Qiang Liu 0011, Anees Ullah, Pedro Reviriego	A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng	ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Sungsoo Cheon, Kyeongho Lee, Jongsun Park 0001	A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Adrian Kneip, David Bol	A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Yuzong Chen, Junjie Mu, Hyunjoon Kim, Lu Lu 0013, Tony Tae-Hyoung Kim	BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda	Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Leyi Chen, Cong Shi 0003, Junxian He, Jianyi Yu, Haibing Wang, Jing Lu, Liyuan Liu, Nanjian Wu, Min Tian	An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Jiahao Song, Xiyuan Tang, Xin Qiao, Yuan Wang 0001, Runsheng Wang, Ru Huang	A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Dawit Burusie Abdi, Shairfe Muhammad Salahuddin, Jürgen Bömmels, Edouard Giacomin, Pieter Weckx, Julien Ryckaert, Geert Hellings, Francky Catthoor	3D SRAM Macro Design in 3D Nanofabric Process Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Erfan Abbasian, Sobhan Sofimowloodi	Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Yanan Sun 0003, Dengfeng Wang, Liukai Xu, Yiming Chen, Zhi Li, Songyuan Liu, Weifeng He, Yongpan Liu, Huazhong Yang, Xueqing Li	CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Hyunjoon Kim, Junjie Mu, Chengshuo Yu, Tony Tae-Hyoung Kim, Bongjin Kim	A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
11	Tae Woo Oh, Juhyun Park, Tae Hyun Kim, Keonhee Cho, Seong-Ook Jung	Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
11	Ralph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang	A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
11	Piljoo Choi, Dong Kyue Kim	Lightweight Polynomial Multiplication Accelerator for NTRU Using Shared SRAM.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
11	Lu Lu 0013, Anh-Tuan Do	A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
11	Chuanghao Zhang, Mingyu Wang, Yangzhan Mai, Chengcheng Tang, Zhiyi Yu	A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
11	Sangheon Lee 0005, Jaehyun Park, Hanwool Jeong	Cross-Coupled nFET Preamplifier for Low Voltage SRAM.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF