Search results for "gate-level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Subhrajit Bhattacharya, Franc Brglez, Sujit Dey	Transformations and resynthesis for testability of RT-level control-data path specifications.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
12	Loganathan Lingappan, Niraj K. Jha	Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
12	Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao	Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
12	Dimitri Kagaris, Themistoklis Haniotakis	Transistor-Level Synthesis for Low-Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
12	Nitin Yogi, Vishwani D. Agrawal	Spectral RTL Test Generation for Microprocessors.	VLSI Design	2007	DBLP DOI BibTeX RDF
12	Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis	Early Power-Aware Design & Validation: Myth or Reality?	DAC	2007	DBLP BibTeX RDF
12	Behzad Akbarpour, Sofiène Tahar	An approach for the formal verification of DSP designs using Theorem proving.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
12	Silvio Misera, Heinrich Theodor Vierhaus, Lars Breitenfeld, André Sieber	A Mixed Language Fault Simulation of VHDL and SystemC.	DSD	2006	DBLP DOI BibTeX RDF
12	Steffen Knapp, Wolfgang J. Paul	Realistic Worst-Case Execution Time Analysis in the Context of Pervasive System Verification.	Program Analysis and Compilation	2006	DBLP DOI BibTeX RDF
12	Christian Jacobi 0002, Christoph Berg	Formal Verification of the VAMP Floating Point Unit.	Formal Methods Syst. Des.	2005	DBLP DOI BibTeX RDF	IEEE standard 754, formal verification, theorem proving, PVS, floating point unit
12	Loganathan Lingappan, Niraj K. Jha	Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits.	VTS	2005	DBLP DOI BibTeX RDF
12	Benton H. Calhoun, Frank Honoré, Anantha P. Chandrakasan	Design methodology for fine-grained leakage control in MTCMOS.	ISLPED	2003	DBLP DOI BibTeX RDF	fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS
12	Qing Wu 0002, Qinru Qiu, Massoud Pedram	Estimation of peak power dissipation in VLSI circuits using thelimiting distributions of extreme order statistics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
12	Rolf Drechsler, Wolfgang Günther 0001, Lothar Linhard, Gerhard Angst	Level Assignment for Displaying Combinational Logic.	DSD	2001	DBLP DOI BibTeX RDF
12	Montek Singh, Steven M. Nowick	Synthesis for logical initializability of synchronous finite-state machines.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
12	Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou 0001, Michel Langevin, Otmane Aït Mohamed	Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
12	Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie	Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
12	Kensaburo Alfredo Tamura	Locating Functional Errors in Logic Circuits.	DAC	1989	DBLP DOI BibTeX RDF
12	Yoshiharu Kazama, Yoshiaki Kinoshita, Motonobu Nagafuji, Hiroshi Murayama	Algorithm for Vectorizing Logic Simulation and Evaluation of "VELVET" Performance.	DAC	1988	DBLP BibTeX RDF
12	Chien-Hung Chao, F. Gail Gray	Micro-operation Perturbations in Chip Level Fault Modeling.	DAC	1988	DBLP BibTeX RDF
11	Levent Aksoy, Diego Jaccottet, Eduardo Costa 0001	Design of low complexity digital FIR filters.	SBCCI	2009	DBLP DOI BibTeX RDF	low-level synthesis, multiple constant multiplications, multiplierless filter design, high-level synthesis, array multipliers
11	Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri	A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF
11	Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	Optimization Techniques for ADL-Driven RTL Processor Synthesis.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
11	Debayan Bhaduri, Sandeep K. Shukla	NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	CTMR, defect-tolerant architecture, nanotechnology, granularity, TMR, PRISM
11	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria	An instruction-level energy model for embedded VLIW architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
11	Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng	HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis.	ISQED	2001	DBLP DOI BibTeX RDF
11	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre	Analyzing testability from behavioral to RT level.	ED&TC	1997	DBLP DOI BibTeX RDF
11	Christopher A. Ryan, Joseph G. Tront	FX: a fast approximate fault simulator for the switch-level using VHDL.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
10	Mario García-Valderas, Luis Entrena, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García	SET Emulation Under a Quantized Delay Model.	J. Electron. Test.	2009	DBLP DOI BibTeX RDF	Fault emulation, Fault tolerance, Fault injection, Single event transients
10	Wei Zhang 0012, Niraj K. Jha, Li Shang	A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	design optimization flow, logic folding, Dynamic reconfiguration, NATURE
10	Miroslav Knezevic, Kazuo Sakiyama, Yong Ki Lee, Ingrid Verbauwhede	On the high-throughput implementation of RIPEMD-160 hash algorithm.	ASAP	2008	DBLP DOI BibTeX RDF
10	Yousra Alkabani, Farinaz Koushanfar, Negar Kiyavash, Miodrag Potkonjak	Trusted Integrated Circuits: A Nondestructive Hidden Characteristics Extraction Approach.	Information Hiding	2008	DBLP DOI BibTeX RDF
10	Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek	Transaction-Based Communication-Centric Debug.	NOCS	2007	DBLP DOI BibTeX RDF
10	Lijun Li, Carl Tropper	A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation.	PADS	2007	DBLP DOI BibTeX RDF
10	Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu	A Study on Impact of Leakage Current on Dynamic Power.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Helia Naeimi, André DeHon	Fault Secure Encoder and Decoder for Memory Applications.	DFT	2007	DBLP DOI BibTeX RDF
10	Julien Schmaltz	A Formal Model of Clock Domain Crossing and Automated Verification of Time-Triggered Hardware.	FMCAD	2007	DBLP DOI BibTeX RDF
10	Wei Zhang 0012, Li Shang, Niraj K. Jha	NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture.	DAC	2007	DBLP DOI BibTeX RDF
10	Shweta Shah, Nazanin Mansouri, Adrián Núñez-Aldana	Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
10	Murari Mani, Ashish Kumar Singh, Michael Orshansky	Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization.	ICCAD	2006	DBLP DOI BibTeX RDF
10	Sreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney	Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
10	Vishal Khandelwal, Ankur Srivastava 0001	Active mode leakage reduction using fine-grained forward body biasing strategy.	ISLPED	2004	DBLP DOI BibTeX RDF	forward body biasing, leakage power optimization
10	Carlos A. Coello Coello, Erika Hernández Luna, Arturo Hernández Aguirre	Use of Particle Swarm Optimization to Design Combinational Logic Circuits.	ICES	2003	DBLP DOI BibTeX RDF
10	Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante	Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels.	DFT	2003	DBLP DOI BibTeX RDF
10	Tai-Hung Liu, Adnan Aziz, Vigyan Singhal	Optimizing designs containing black boxes.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	IP-based design, hierarchical logic synthesis, Don't cares
10	Reiner W. Hartenstein	Reconfigurable Computing: A New Business Model and its Impact on SoC Design.	DSD	2001	DBLP DOI BibTeX RDF
10	Silvia Chiusano, Fulvio Corno, Paolo Prinetto	A Test Pattern Generation Algorithm Exploiting Behavioral Information.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
10	Daniel G. Saab, Youssef Saab, Jacob A. Abraham	Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
10	Warren H. Debany Jr., Kevin A. Kwiat, Sami A. Al-Arian	A Method for Consistent Fault Coverage Reporting.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
10	Bernhard Hoppe, Gerd Neuendorf, Doris Schmitt-Landsiedel, J. Will Specks	Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
10	Hyung Ki Lee, Dong Sam Ha	SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits.	DAC	1990	DBLP DOI BibTeX RDF
10	Niraj K. Jha	Testing for multiple faults in domino-CMOS logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
10	Gerd Krüger 0001	Automatic generation of self-test programs - a new feature of the MIMOLA design system.	DAC	1986	DBLP DOI BibTeX RDF
10	Anil K. Gupta, James R. Armstrong	Functional fault modeling and simulation for VLSI devices.	DAC	1985	DBLP DOI BibTeX RDF
10	Danilo Ravotto, Edgar E. Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.	MTV	2007	DBLP DOI BibTeX RDF
10	József Sziray	Test Calculation for Logic and Delay Faults in Digital Circuits.	MTV	2006	DBLP DOI BibTeX RDF	Test-pattern calculation, logic faults, CMOS transistor structures, functional testing, delay faults, multi-valued logic
10	Jaan Raik, Tanel Nõmmeots, Raimund Ubar	A New Testability Calculation Method to Guide RTL Test Generation.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	test pattern generation, register-transfer level, decision diagrams, testability measures
10	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero	High-Level Observability for Effective High-Level ATPG.	VTS	2000	DBLP DOI BibTeX RDF
10	Vamsi Krishna, N. Ranganathan	A Methodology for High Level Power Estimation and Exploration.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Low Power Designs, Power Estimation, Switching Activity, High Level Designs
10	Dhruva R. Chakrabarti, Ajai Jain	An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph
10	Lawrence P. Huang, Randal E. Bryant	Intractability in linear switch-level simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
10	Gabriel M. Silberman, Ilan Y. Spillinger	Using functional fault simulation and the difference fault model to estimate implementation fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
9	Benjamin Vigoda, David Reynolds, Jeffrey Bernstein, Theophane Weber, Bill Bradley	Low power logic for statistical inference.	ISLPED	2010	DBLP DOI BibTeX RDF	device physics, probability programming language, stochastic circuits, fault tolerance, markov chain monte carlo, generative model, belief propagation, gibbs sampling, probabilistic graphical model
9	Mawahib Hussein Sulieman	On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations.	NanoNet	2009	DBLP DOI BibTeX RDF	Reliability, CMOS, threshold voltage, gates
9	Benjamin Carrión Schäfer, Taewhan Kim	Hotspots Elimination and Temperature Flattening in VLSI Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
9	Kristian Granhaug, Snorre Aunet	Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Subthreshold CMOS, Output-wired redundancy, Yield and defect tolerance
9	Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst	Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic.	FPL	2008	DBLP DOI BibTeX RDF
9	Muzhou Shao	Fast Timing Update under the Effect of IR Drop.	ISQED	2008	DBLP DOI BibTeX RDF
9	Yu Cao, Lawrence T. Clark	Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
9	Snorre Aunet, Hans Kristian Otnes Berge	Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits.	IWANN	2007	DBLP DOI BibTeX RDF
9	Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin	Low-cost protection for SER upsets and silicon defects.	DATE	2007	DBLP DOI BibTeX RDF
9	Kristian Granhaug, Snorre Aunet	Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates.	DFT	2006	DBLP DOI BibTeX RDF
9	Shuguang Zhao, Licheng Jiao, Jun Zhao	Multi-objective Evolutionary Design and Knowledge Discovery of Logic Circuits with an Improved Genetic Algorithm.	CIS (1)	2005	DBLP DOI BibTeX RDF
9	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	A library compatible driver output model for on-chip RLC transmission lines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
9	O. Milter, Avinoam Kolodny	Crosstalk noise reduction in synthesized digital logic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
9	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver	A Fine-Grain Phased Logic CPU.	ISVLSI	2003	DBLP DOI BibTeX RDF
9	Reza Sedaghat	A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
9	Luc Séméria, Renu Mehra, Barry M. Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng	RTL c-based methodology for designing and verifying a multi-threaded processor.	DAC	2002	DBLP DOI BibTeX RDF	formal equivalence, design, verification, RTL, checking, C/C++
9	Bruno Franzini, Cristiano Forzan, Davide Pandini, Primo Scandolara, Alessandro Dal Fabbro	Crosstalk Aware Static Timing Analysis: A Two Step Approach.	ISQED	2000	DBLP DOI BibTeX RDF
9	Jason Cong, Hui Huang 0001	Depth optimal incremental mapping for field programmable gate arrays.	DAC	2000	DBLP DOI BibTeX RDF
9	Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone	Power reduction through iterative gate sizing and voltage scaling.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
9	Jason Masner, John Cavalieri, James F. Frenzel, James A. Foster	Representation and Robustness for Evolved Sorting Networks.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
9	Michael J. Wirthlin, Brad L. Hutchings	Improving functional density using run-time circuit reconfiguration [FPGAs].	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
9	Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz	LOT: Logic Optimization with Testability. New transformations for logic synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
9	Douglas Chang, Malgorzata Marek-Sadowska	Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
9	J. Gong, Eddie M. C. Wong	Verification of Asynchronous Circuits with Bounded Inertial Gate Delays.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
9	Tatiana Kalganova, Julian F. Miller, Terence C. Fogarty	Some Aspects of an Evolvable Hardware Approach for Multiple-Valued Combinational Circuit Design.	ICES	1998	DBLP DOI BibTeX RDF
9	Marcello Dalpasso, Michele Favalli	A method for increasing the IDDQ testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
9	Rajendran Panda, Farid N. Najm	Technology-Dependent Transformations for Low-Power Synthesis.	DAC	1997	DBLP DOI BibTeX RDF
9	Yih-Lang Li, Cheng-Wen Wu	Cellular automata for efficient parallel logic and fault simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	Wei-Liang Lin, Majid Sarrafzadeh, Chak-Kuen Wong	The reproducing placement problem with applications.	ICCAD	1994	DBLP DOI BibTeX RDF
9	Ahmet N. Parlakbilek, David M. Lewis	A multiple-strength multiple-delay compiled-code logic simulator.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
9	Zaifu Zhang, Robert D. McLeod, Witold Pedrycz	A neural network algorithm for testing stuck-open faults in CMOS combinational circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	stuck-open and gate delay faults, Neural networks, test pattern generation
9	Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi	System-level PVT variation-aware power exploration of on-chip communication architectures.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	PVT variation, on-chip communication architectures, performance exploration, high-level synthesis, power estimation, digital systems
9	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.	VLSI Design	2008	DBLP DOI BibTeX RDF
9	Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha	High-Level Energy Estimation for ARM-Based SOCs.	SAMOS	2004	DBLP DOI BibTeX RDF
9	Li Shen 0002	RTL Concurrent Fault Simulation.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	concurrent fault simulation, fault model, RTL, high-level testing, circuit modeling
9	Karen Panetta Lentz, Jonathan B. Homer	Handling Behavioral Components in Multi-Level Concurrent Fault Simulation.	Annual Simulation Symposium	2000	DBLP DOI BibTeX RDF	concurrent fault simulation, simulation, behavioral modeling, multilevel
9	L. Ivanov, R. Nunna, S. Bloom	Modeling and analysis of noniterated systems: an approach based upon series-parallel posets.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
9	K. J. Singh, P. A. Subrahmanyam	Extracting RTL models from transistor netlists.	ICCAD	1995	DBLP DOI BibTeX RDF	Switch-level simulation, Formal verification, Extraction, RTL model