Search results for "finfet"

Hits ?▲	Authors	Title	Venue	Year	Link
14	Vinay Kumar, Ravindra kumar Shrivatava, Madhav Mansukh Padaliya	A Temperature Compensated Read Assist for Low Vmin and High Performance High Density 6T SRAM in FinFET Technology.	VLSID	2018	DBLP DOI BibTeX RDF
14	Esteve Amat, Alberto del Moral, Joan R. Bausells, Francesc Pérez-Murano, Fabian J. Klüpfel	Quantum dot location relevance into SET-FET circuits based on FinFET devices.	DCIS	2018	DBLP DOI BibTeX RDF
14	Rui Zhang 0048, Kexin Yang 0001, Taizhi Liu, Linda Milor	Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms.	DCIS	2018	DBLP DOI BibTeX RDF
14	Kexin Yang 0001, Rui Zhang 0048, Taizhi Liu, Dae Hyun Kim 0003, Linda Milor	Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology.	DCIS	2018	DBLP DOI BibTeX RDF
14	Shenggao Li, Fulvio Spagna, Ji Chen, Xiaoqing Wang, Luke Tong, Sujatha Gowder, Wenyan Jia, Roan Nicholson, Sitaraman Iyer, Rui Song, Lily Li, Meng-hung Chen, Amanda Tran, Michael De Vita, Deepar Govindrajan, Marcus Pasquarella, Dave Bradley, Frank Verdico, Matt Duwe, Eric Lee, Michelle Wigton	A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS.	A-SSCC	2018	DBLP DOI BibTeX RDF
14	Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards, Jonathan Bachrach, Elad Alon, Borivoje Nikolic	A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET.	A-SSCC	2018	DBLP DOI BibTeX RDF
14	Matthias Eberlein, Georgios Panagopoulos, Harald Pretl	A 40nW, Sub-IV Truly 'Digital' Reverse Bandgap Reference Using Bulk-Diodes in 16nm FinFET.	A-SSCC	2018	DBLP DOI BibTeX RDF
14	Srishti, Jasmeet Kaur	Performance Optimization of FinFET Configurations at 14 nm Technology Using ANN-PSO.	VDAT	2018	DBLP DOI BibTeX RDF
14	Yu-Sheng Lu, Yu-Hsuan Chang, Yao-Wen Chang	WB-trees: a meshed tree representation for FinFET analog layout designs.	DAC	2018	DBLP DOI BibTeX RDF
14	Marc Erett, James Hudner, Declan Carey, Ronan Casey, Kevin Geary, Kay Hearne, Pedro Neto 0001, Thomas Mallard, Vikas Sooden, Mark Smyth, Yohan Frans, Jay Im, Parag Upadhyaya, Wenfeng Zhang, Winson Lin, Bruce Xu, Ken Chang	A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Taejoong Song, Woojin Rim, Sunghyun Park 0003, Yongho Kim, Giyong Yang, Hoonki Kim, Sanghoon Baek, Jonghoon Jung, Bongjae Kwon, Sungwee Cho, Hyuntaek Jung, Yongjae Choo, Jaeseung Choi 0001	A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Jaydeep P. Kulkarni, John Keane 0001, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang 0001	5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Shinichi Shibahara, Chikafumi Takahashi, Kazuki Fukuoka, Yuko Kitaji, Takahiro Irita, Hirotaka Hara, Yasuhisa Shimazaki, Jun Matsushima	A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl	A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Yohan Frans, Jaewook Shin, Lei Zhou, Parag Upadhyaya, Jay Im, Vassili Kireev, Mohamed Elzeftawi, Hiva Hedayati, Toan Pham, Santiago Asuncion, Chris Borrelli, Geoff Zhang, Hongtao Zhang 0002, Ken Chang	A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang	A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Michael A. Turi, José G. Delgado-Frias	Full-VDD and near-threshold performance of 8T FinFET SRAM cells.	Integr.	2017	DBLP DOI BibTeX RDF
14	Xiaoliang Dai, Niraj K. Jha	Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation: Application to Extraction of Best 10-nm FinFET Parameter Values.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
14	Vikas Mahor, Manisha Pattanaik	An Aging-Aware Reliable FinFET-Based Low-Power 32-Word \(\times \) 32-bit Register File.	Circuits Syst. Signal Process.	2017	DBLP DOI BibTeX RDF
14	Ermao Cai, Diana Marculescu	Temperature Effect Inversion-Aware Power-Performance Optimization for FinFET-Based Multicore Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
14	Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques 0001, Leomar S. da Rosa Jr.	Transistor Count Optimization in IG FinFET Network Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2017	DBLP DOI BibTeX RDF
14	Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi	Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology.	Int. J. Circuit Theory Appl.	2017	DBLP DOI BibTeX RDF
14	Rahebeh Niaraki Asli, Shiva Taghipour	A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET Technology.	J. Electron. Test.	2017	DBLP DOI BibTeX RDF
14	Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell	Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies.	J. Electron. Test.	2017	DBLP DOI BibTeX RDF
14	V. Jegadheesan, K. Sivasankaran	RF stability performance of SOI junctionless FinFET and impact of process variation.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
14	Azzedin D. Es-Sakhi, Masud H. Chowdhury	Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
14	Usman Khalid, Antonio Mastrandrea, Mauro Olivieri	Effect of NBTI/PBTI Aging and Process Variations on Write Failures in MOSFET and FinFET Flip-Flops.	CoRR	2017	DBLP BibTeX RDF
14	Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Sergiu Mosanu, Mircea R. Stan	Back to the Future: Digital Circuit Design in the FinFET Era.	J. Low Power Electron.	2017	DBLP DOI BibTeX RDF
14	Alexander E. Shapiro, Eby G. Friedman	Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies.	J. Low Power Electron.	2017	DBLP DOI BibTeX RDF
14	Y. Q. de Aguiar, Laurent Artola, Guillaume Hubert, Cristina Meinhardt, Fernanda Lima Kastensmidt, Ricardo Augusto da Luz Reis	Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
14	Shimpei Yamaguchi, Zeynel Bayindir, Xiaoli He, Suresh Uppal, Purushothaman Srinivasan, Chloe Yong, Dongil Choi, Manoj Joshi, Hyuck Soo Yang, Owen Hu, Srikanth Samavedam, Dong Kyun Sohn	Effective work-function control technique applicable to p-type FinFET high-k/metal gate devices.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
14	Shiva Taghipour, Rahebeh Niaraki Asli	Aging comparative analysis of high-performance FinFET and CMOS flip-flops.	Microelectron. Reliab.	2017	DBLP DOI BibTeX RDF
14	Nathaniel Ross Pinckney, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw, Lucian Shifren, Brian Cline, Saurabh Sinha	Impact of FinFET on Near-Threshold Voltage Scalability.	IEEE Des. Test	2017	DBLP DOI BibTeX RDF
14	Faris S. Alghareb, Rizwan A. Ashraf, Ahmad Alzahrani 0001, Ronald F. DeMara	Energy and Delay Tradeoffs of Soft-Error Masking for 16-nm FinFET Logic Paths: Survey and Impact of Process Variation in the Near-Threshold Region.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
14	Luke Wang, Marc-Andre LaCroix, Anthony Chan Carusone	A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
14	Mohit Kumar Gupta 0001, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Dmitry Yakimets, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene	Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7.	ESSDERC	2017	DBLP DOI BibTeX RDF
14	Michail Noltsis, Eleni Maragkoudaki, Dimitrios Rodopoulos, Francky Catthoor, Dimitrios Soudris	Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point.	PATMOS	2017	DBLP DOI BibTeX RDF
14	Esteve Amat, Antonio Calomarde, Ramon Canal, Antonio Rubio 0001	Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level.	PATMOS	2017	DBLP DOI BibTeX RDF
14	Thiago Santos Copetti, Tiago R. Balen, Guilherme Cardoso Medeiros, Letícia Maria Bolzani Poehls	Analyzing the behavior of FinFET SRAMs with resistive defects.	VLSI-SoC	2017	DBLP DOI BibTeX RDF
14	Thiago Santos Copetti, Guilherme Cardoso Medeiros, Letícia Maria Bolzani Poehls, Tiago R. Balen	Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs.	VLSI-SoC (Selected Papers)	2017	DBLP DOI BibTeX RDF
14	Weiwei Jiang 0002, Davide Bertozzi, Gabriele Miorandi, Steven M. Nowick, Wayne P. Burleson, Greg Sadowski	An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart.	DATE	2017	DBLP DOI BibTeX RDF
14	Warin Sootkaneung, Suppachai Howimanporn, Sasithorn Chookaew	Thermal Effect on Performance, Power, and BTI Aging in FinFET-Based Designs.	DSD	2017	DBLP DOI BibTeX RDF
14	Y. Q. de Aguiar, Fernanda Lima Kastensmidt, Cristina Meinhardt, Ricardo A. L. Reis	SET response of FinFET-based majority voter circuits under work-function fluctuation.	ICECS	2017	DBLP DOI BibTeX RDF
14	Lawrence T. Clark, Vinay Vashishtha, David M. Harris, Samuel Dietrich, Zunyan Wang	Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit.	MSE	2017	DBLP DOI BibTeX RDF
14	Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang	Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET.	ESSCIRC	2017	DBLP DOI BibTeX RDF
14	Francesco Conzatti, Lukas Dörrer, Patrick Torta, Claus Kropf, Dirk Patzold, Jacinto San Pablo Garcia, Venerando Rallos, Norbert Schembera	A CT ΔΣ ADC with 9/50MHz BW achieving 73/71dB DR designed for robust blocker tolerance in 14nm FinFET.	ESSCIRC	2017	DBLP DOI BibTeX RDF
14	Philipp Salz, A. Frisch, Wolfgang Penth, J. Noack, T. Kalla, Rolf Sautter, Michael Kugel, Otto A. Torreiter, G. Sapp, Mike Lee, Eric Fluhr, A. Rozenfeld, Jürgen Pille, Dieter F. Wendel	A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology.	ESSCIRC	2017	DBLP DOI BibTeX RDF
14	Shushanik Karapetyan, Ulf Schlichtmann	20nm FinFET-based SRAM cell: Impact of variability and design choices on performance characteristics.	SMACD	2017	DBLP DOI BibTeX RDF
14	Shaofeng Guo, Runsheng Wang, Zhuoqing Yu, Peng Hao, Pengpeng Ren, Yangyuan Wang, Siyu Liao, Chunyi Huang, Tianlei Guo, Alvin Chen, Jushan Xie, Ru Huang	Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulator.	ICCAD	2017	DBLP DOI BibTeX RDF
14	Sudipta Bhuin, Joseph Sweeney, Samuel Pagliarini, Ayan Kumar Biswas, Lawrence T. Pileggi	A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ.	NANOARCH	2017	DBLP DOI BibTeX RDF
14	Lawrence T. Clark, Vinay Vashishtha	Design with sub-10 nm FinFET technologies.	CICC	2017	DBLP DOI BibTeX RDF
14	Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen 0001	A 0.031mm2, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS.	CICC	2017	DBLP DOI BibTeX RDF
14	Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl	28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET.	ISSCC	2017	DBLP DOI BibTeX RDF
14	Venumadhav Bhagavatula, Dae Hyun Kwon, Jaehun Lee, Quang-Diep Bui, Jeong-Hyun Choi, Siuchuang-Ivan Lu, Sang Won Son	13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS.	ISSCC	2017	DBLP DOI BibTeX RDF
14	Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Luis Cuellar, Muhammad Faisal, Yee William Li, Hyung Seok Kim, Khoa Minh Nguyen, Yulin Tan, Brent R. Carlton, Vaibhav A. Vaidya, Yanjie Wang, Thomas Tetzlaff, Satoshi Suzuki, Amr Fahim, Parmoon Seddighrad, Jianyong Xie, Zhichao Zhang, Divya Shree Vemparala, Ashoke Ravi, Stefano Pellerano, Yorgos Palaskas	13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications.	ISSCC	2017	DBLP DOI BibTeX RDF
14	Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park 0003, Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, Jaeseung Choi 0001	12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis.	ISSCC	2017	DBLP DOI BibTeX RDF
14	Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl	29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET.	ISSCC	2017	DBLP DOI BibTeX RDF
14	Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu	12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.	ISSCC	2017	DBLP DOI BibTeX RDF
14	Christophe Erdmann, Edward Cullen, Damien Brouard, Roberto Pelliconi, Bob Verbruggen, John McGrath, Diarmuid Collins, Marites De La Torre, Pierrick Gay, Patrick Lynch, Peng Lim, Anthony Collins, Brendan Farley	16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz.	ISSCC	2017	DBLP DOI BibTeX RDF
14	Hugh Mair, Ericbill Wang, Alice Wang, Ping Kao, Yuwen Tsai, Sumanth Gururajarao, Rolf Lagerquist, Jin Son, Gordon Gammie, Gordon Lin, Achuta Thippana, Kent Li, Manzur Rahman, Wuan Kuo, David Yen, Yi-Chang Zhuang, Ue Fu, Hung-Wei Wang, Mark Peng, Cheng-Yuh Wu, Taner Dosluoglu, Anatoly Gelman, Daniel Dia, Girishankar Gurumurthy, Tony Hsieh, W. X. Lin, Ray Tzeng, Jengding Wu, C. H. Wang, Uming Ko	3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance.	ISSCC	2017	DBLP DOI BibTeX RDF
14	Jay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang	6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET.	ISSCC	2017	DBLP DOI BibTeX RDF
14	Chao-Chieh Li, Min-Shueh Yuan, Chih-Hsien Chang, Yu-Tso Lin, Chia-Chun Liao, Kenny Hsieh, Mark Chen 0001, Robert Bogdan Staszewski	19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications.	ISSCC	2017	DBLP DOI BibTeX RDF
14	Vivek Nautiyal, Gaurav Singla, Satinderjit Singh, Fakhruddin Ali Bohra, Jitendra Dasani, Lalit Gupta, Sagar Dwivedi	Charge recycled low power SRAM with integrated write and read assist, for wearable electronics, designed in 7nm FinFET.	ISLPED	2017	DBLP DOI BibTeX RDF
14	Byung-Su Kim, Hyo-Sig Won, Tae Hee Han, Joon-Sung Yang	Non-linear library characterization method for FinFET logic cells by L1-minimization.	ISCAS	2017	DBLP DOI BibTeX RDF
14	Jan Plíva, Mahdi M. Khafaji, László Szilágyi, Ronny Henker, Frank Ellinger	Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOS.	SoCC	2017	DBLP DOI BibTeX RDF
14	Vivek Nautiyal, Gaurav Singla, Lalit Gupta, Sagar Dwivedi, Martin Kinkade	An ultra high density pseudo dual-port SRAM in 16nm FINFET process for graphics processors.	SoCC	2017	DBLP DOI BibTeX RDF
14	Gerd Teepe	Wednesday keynote I: FDSOI and FINFET for SoC developments.	SoCC	2017	DBLP DOI BibTeX RDF
14	Olivier Weber	FDSOI vs FinFET: differentiating device features for ultra low power & IoT applications.	ICICDT	2017	DBLP DOI BibTeX RDF
14	Eunah Ko, Jaesung Jo, Changhwan Shin, Bich-Yen Nguyen	Layout engineering to suppress hysteresis of negative capacitance FinFET.	ICICDT	2017	DBLP DOI BibTeX RDF
14	Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac	Analysis of short defects in FinFET based logic cells.	LATS	2017	DBLP DOI BibTeX RDF
14	Huimei Cheng, Ji Li 0006, Jeffrey T. Draper, Shahin Nazarian, Yanzhi Wang	Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems.	ACM Great Lakes Symposium on VLSI	2017	DBLP DOI BibTeX RDF
14	Edward Yi Chang, Quang-Ho Luc, Huy-Binh Do, Yueh-Chin Lin	Performance improvement of InGaAs FinFET using NH3 treatment.	ASICON	2017	DBLP DOI BibTeX RDF
14	Kazuhiko Endo	Advanced FinFET technologies for boosting SRAM performance.	ASICON	2017	DBLP DOI BibTeX RDF
14	Runsheng Wang, Xiaobo Jiang, Shaofeng Guo, Ru Huang	How close to the CMOS voltage scaling limit for FinFET technology? - Near-threshold computing and stochastic computing.	ASICON	2017	DBLP DOI BibTeX RDF
14	Sam C. Lo, Taylor T. Lee, Aaron J. Barker	High sigma statistical hold time analysis in FinFET sequential circuits.	ISQED	2017	DBLP DOI BibTeX RDF
14	Byungki Han, Jongwoo Lee, Seunghyun Oh, Jae-Kwon Kim, Eswar Mamidala, Thomas Byunghak Cho	A 14nm FinFET analog baseband SOC for multi-mode cellular applications with tri-band carrier aggregation.	ISOCC	2017	DBLP DOI BibTeX RDF
14	H. Girish, D. R. Shashikumar	Cost-Effective Computational Modeling of Fault Tolerant Optimization of FinFET-Based SRAM Cells.	CSOC (2)	2017	DBLP DOI BibTeX RDF
14	Ahmed S. Sajit, Michael A. Turi	SEU tolerance of FinFET 6T SRAM, 8T SRAM and DICE memory cells.	CCWC	2017	DBLP DOI BibTeX RDF
14	Mitesh Limachia, Pathik Viramgama, Rajesh Amratlal Thakker, Nikhil Kothari	Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin for 20nm FinFET Technology.	VLSID	2017	DBLP DOI BibTeX RDF
14	Sanjay Kumar Wadhwa, Nidhi Chaudhry	High Accuracy, Multi-output Bandgap Reference Circuit in 16nm FinFet.	VLSID	2017	DBLP DOI BibTeX RDF
14	Vinay Kumar, Nikhil Puri, Sudhir Kumar 0002, Sumit Srivastav	A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET.	VLSID	2017	DBLP DOI BibTeX RDF
14	Brendan Farley, Christophe Erdmann, Bruno Vaz, John McGrath, Edward Cullen, Bob Verbruggen, Roberto Pelliconi, Daire Breathnach, Peng Lim, Ali Boumaalif, Patrick Lynch, Conrado Mesadri, David Melinn, Kwee Peng Yap, Liam Madden	A programmable RFSoC in 16nm FinFET technology for wideband communications.	A-SSCC	2017	DBLP DOI BibTeX RDF
14	Da-Shin Lin, Hao-Ping Hong	A 0.5V BJT-based CMOS thermal sensor in 10-nm FinFET technology.	A-SSCC	2017	DBLP DOI BibTeX RDF
14	Jongmi Lee, Jongwoo Lee, Chilun Lo, Jaehoon Lee 0005, In-Young Lee, Byungki Han, Seunghyun Oh, Thomas Byunghak Cho	A reconfigurable analog baseband transformer for multistandard applications in 14nm FinFET CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
14	Angie Wang, Brian C. Richards, Daniel Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn 0003, Elad Alon, Borivoje Nikolic	A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET.	A-SSCC	2017	DBLP DOI BibTeX RDF
14	B. Vandana, Jitendra Kumar Das, S. K. Mohapatra, Brajesh Kumar Kaushik	Effectiveness of High Permittivity Spacer for Underlap Regions of Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel Effects.	VDAT	2017	DBLP DOI BibTeX RDF
14	Jay Pathak, Anand D. Darji	Investigation of TCADs Models for Characterization of Sub 16 nm In _0.53 Ga _0.47 As FinFET.	VDAT	2017	DBLP DOI BibTeX RDF
14	Shrikanth Ganapathy, John Kalamatianos, Keith Kasprak, Steven Raasch	On Characterizing Near-Threshold SRAM Failures in FinFET Technology.	DAC	2017	DBLP DOI BibTeX RDF
14	Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane 0001, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang 0001	A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
14	Sanu K. Mathew, David Johnston, Sudhir Satpathy, Vikram B. Suresh, Paul Newman 0002, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy	µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
14	Yohan Frans, Scott McLeod, Hiva Hedayati, Mohamed Elzeftawi, Jin Namkoong, Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang	A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
14	Alexander E. Shapiro, Eby G. Friedman	Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
14	Kyoman Kang, Hanwool Jeong, Younghwi Yang, Juhyun Park, Ki-Ryong Kim, Seong-Ook Jung	Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
14	Debajit Bhattacharya, Niraj K. Jha	TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
14	Sangheon Oh, Changhwan Shin	Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
14	Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu	Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
14	Bhupendra Singh Reniwal, Vikas Vijayvargiya, Santosh Kumar Vishvakarma, Devesh Dwivedi	Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance.	Circuits Syst. Signal Process.	2016	DBLP DOI BibTeX RDF
14	Esteve Amat, Antonio Calomarde, Francesc Moll, Ramon Canal, Antonio Rubio 0001	Feasibility of Embedded DRAM Cells on FinFET Technology.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
14	Wangkun Jia, Brian T. Helenbrook, Ming-C. Cheng	Fast Thermal Simulation of FinFET Circuits Based on a Multiblock Reduced-Order Model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
14	Pawan Sharma, Saurabh Khandelwal, Shyam Akashe	FinFET Design Considerations Based on Schmitt Trigger with Slew Rate and Gain-Bandwidth Product Analysis.	Wirel. Pers. Commun.	2016	DBLP DOI BibTeX RDF