Search results for "Architectures"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Qing Yang 0001	Performance Analysis of a Cache-Coherent Multiprocessor Based on Hierarchical Multiple Buses.	PARBASE / Architectures	1990	DBLP DOI BibTeX RDF
22	Mohan Ahuja, Kannan Varadhan, Amitabh Sinha	Flush Message Passing in Communicating Sequential Processes.	PARBASE / Architectures	1990	DBLP DOI BibTeX RDF
22	Hessa Al-Jaber, Shmuel Rotenstreich	Fault Tolerance of Message Delivery with Cascading Copies.	PARBASE / Architectures	1990	DBLP DOI BibTeX RDF
22	T. D. Roziner	Systolic Macropipelines for Multidimensional Fourier Transforms.	PARBASE / Architectures	1990	DBLP DOI BibTeX RDF
22	Peter J. Varman, Balakrishna R. Iyer, Donald J. Haderle	Parallel Merging on Shared and Distributed Memory Computers.	PARBASE / Architectures	1990	DBLP DOI BibTeX RDF
22	Jai Eun Jang	An Optimal Fault-Tolerant Broadcasting Algorithm for a Cube-Connected Cycles Multiprocessor.	PARBASE / Architectures	1990	DBLP DOI BibTeX RDF
22	Jie Wu 0001, Eduardo B. Fernández	The Extended G-Network, a Fault-Tolerant Interconnection Network for the Multiprocessors.	PARBASE / Architectures	1990	DBLP DOI BibTeX RDF
22	V. Prasad Krothapalli, P. Sadayappan	Dynamic Scheduling of DOACROSS Loops for Multiprocessors.	PARBASE / Architectures	1990	DBLP DOI BibTeX RDF
22	Manohar Rao, Zary Segall	Implementation and Evaluation of a Parallel PMS Simulator.	PARBASE / Architectures	1990	DBLP DOI BibTeX RDF
22	Andreas Alexander Albrecht, Hermann Jung 0001, Kurt Mehlhorn (eds.)	Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Didier Ferment, Brigitte Rozoy	Solutions for the Distributed Termination Problem.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Edgar Körner, T. Tsuda, H. Shimizu	Parallel in Sequence - Towards the Architecture of an Elementary Cortical Processor.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Akihiko Konagaya, Ryosei Nakazaki, Mamoru Umemura	A Co-Operative Programming Environment for a Back-End Type Sequential Inference Machine CHI.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Helmut Alt, Torben Hagerup, Kurt Mehlhorn, Franco P. Preparata	Deterministic Simulation of Idealized Parallel Computers on more Realistic Ones.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Burkhard Monien, Oliver Vornberger	Parallel Processing of Combinatorial Search.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Clark D. Thomborson, Linda L. Deneen, Gary M. Shute	Computing a Rectilinear Steiner Minimal Tree in nO(sqrt(n)) Time.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Nikolay N. Mirenkov	Parallel Algorithms and Static Analysis of Parallel Programs.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Chee-Keng Yap	What Can be Parallelized in Computational Geometry?.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Tetsuo Asano, Hiroshi Umeo	Systolic Algorithms for Computing the Visibility Polygon and Triangulation of A Polygonal Region.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Krzysztof Diks	Parallel Recognition of Outerplanar Graphs.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Wojciech Rytter, Raffaele Giancarlo	Optimal Parallel Parsing of Bracket Languages.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Reiner Creutzburg	Parallel Linear Conflict-Free Subtree Access.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Alberto Apostolico, Costas S. Iliopoulos, Robert Paige	On O(n log n) Cost Parallel Algorithm for the Single Function Coarsest Partition Problem.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Rex A. Dwyer, Ravi Kannan	Convex Hull of Randomly Chosen Points from A Polytope.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	D. De Baer, Jan Paredaens	A Formal Definition for Systolic Systems.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Friedmar Wächter	Optimization of Special Permutation Networks Using Simple Algebraic Relations.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Lothar Budach, Ernst-Günter Giessmann, Hubert Grassmann, Bernd Graw, Christoph Meinel	RELACS - A Recursive Layout Computing System.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Wojciech Rytter	A Note on Optimal Parallel Transformations of Regular Expressions to Nondeterministic Finite Automata.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Imrich Vrto	Area-time Tradeoffs for Selection.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Dietmar Uhlig	On Reliable Networks from Unreliable Gates.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Jayantha A. Herath, Toshitsugu Yuba, Nobuo Saito	Dataflow Computing.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Michael Gössel, R. Rebel	Memories for Parallel Subtree-Access.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Shogo Matsui, Yoshinobu Kato, Shinsuke Teramura, Tomoyuki Tanaka, Nobuyuki Mohri, Atsushi Maeda, Masakazu Nakanishi	SYNAPSE: A Multi-Microprocessor Lisp Machine with Parallel Garbage Collector.	Parallel Algorithms and Architectures	1987	DBLP DOI BibTeX RDF
22	Andy Yan, Steven J. E. Wilton	Product-Term-Based Synthesizable Embedded Programmable Logic Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
22	Deepak Rautela, Rajendra S. Katti	Efficient utilization of heterogeneous routing resources for FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
21	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures.	IEEE Micro	2010	DBLP DOI BibTeX RDF	nonuniform cache architectures, parallel architectures, multicore, cache memories, data placement
21	Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi	Compiling custom instructions onto expression-grained reconfigurable architectures.	CASES	2008	DBLP DOI BibTeX RDF	horizontal microprogramming, compilers, instruction set extensions, coarse-grained reconfigurable architectures, data-flow architectures
21	Jayaram Mudigonda, Harrick M. Vin, Stephen W. Keckler	Reconciling performance and programmability in networking systems.	SIGCOMM	2007	DBLP DOI BibTeX RDF	memoty bottleneck, multithreading, reconfigurable architectures, routers, data cache, processor architectures, packet processing
21	Lawrence Cabac, Michael Duvigneau, Daniel Moldt, Heiko Rölke	Multi-agent concepts as basis for dynamic plug-in software architectures.	AAMAS	2005	DBLP DOI BibTeX RDF	modeling, multi-agent systems, components, high-level Petri nets, renew, reference nets, nets-within-nets, dynamic software architectures, plug-in architectures, mulan
21	Shashank S. Nemawarkar, Guang R. Gao	Latency Tolerance: A Metric for Performance Analysis of Multithreaded Architectures.	IPPS	1997	DBLP DOI BibTeX RDF	performance analysis metric, multithreaded multiprocessor systems, tolerance index, program workload parameters, fine grain parallel program workloads, parallel architectures, multithreaded architectures, latency tolerance, closed queueing networks, analytical framework
21	Yunn Yen Chen, Jih-Kwon Peir, Chung-Ta King	Performance of Shared Cache on Multithreaded Architectures.	PDP	1996	DBLP DOI BibTeX RDF	shared cache performance, trace-driven simulation technique, storage hierarchy system, multithreaded execution environment, multithread scheduling techniques, server/workstation workload mix, MRU priority scheduling scheme, round-robin scheduling method, absolute hit ratio, concurrent threads, simulation, performance evaluation, parallel architectures, shared memory systems, processor scheduling, cache storage, multithreaded architectures, program traces, set associativity, cache size, direct-map cache
21	Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe	Load Balancing in Superscalar Architectures.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources
21	Zhiwei Xu, Kai Hwang 0001	MPPs and clusters for scalable computing.	ISPAN	1996	DBLP DOI BibTeX RDF	scalable parallel computing, Cray T3D/T3E, ASCI TeraFLOPS, performance evaluation, scalability, parallel architectures, reconfigurable architectures, clusters of workstations, Intel Paragon, Intel, massively parallel processors, performance attributes, scalable computing, MPPs, IBM SP2
21	Issei Numata, Susumu Horiguchi	Efficient reconfiguration scheme for mesh-connected network: the recursive shift approach.	ISPAN	1996	DBLP DOI BibTeX RDF	mesh-connected network, recursive shift, faulty processing elements, mesh arrays, redundant processing elements, fault tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, reconfigurable architectures, massively parallel system, reconfiguration scheme
21	Mounir Hamdi, Yi Pan 0001	Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses.	ISPAN	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations
21	Virginio Cantoni, Luca Lombardi	Hierarchical architectures for computer vision.	PDP	1995	DBLP DOI BibTeX RDF	general planning strategies, performance evaluation, computer vision, computer vision, image processing, parallel architectures, hierarchical architectures, computer performance, sensory data
21	Arindam Saha	A simulator for real-time parallel processing architectures.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	real-time parallel processing architectures, time-driven flit-based wormhole-routed parallel processor network simulator, user-friendly graphical user interface, prioritized queues, resource allocation policies, message priorities, average latency convergence, throughput monitoring, communication characteristics, performance, real-time systems, resource allocation, parallel architectures, graphical user interfaces, virtual machines, concurrency control, convergence, deadlocks, virtual channel, overlaps, real-time networks
21	Phyllis Crandall, Michael J. Quinn	Non-uniform 2-D grid partitioning for heterogeneous parallel architectures.	IPPS	1995	DBLP DOI BibTeX RDF	nonuniform 2D grid partitioning, heterogeneous parallel architectures, uniform computational requirements, block decomposition method, Fair Binary Recursive Decomposition, performance level, performance evaluation, parallel architectures, decomposition technique
21	Gopal Chillariga, Balkrishna Ramkumar	Performance prediction for portable parallel execution on MIMD architectures.	IPPS	1995	DBLP DOI BibTeX RDF	portable parallel execution, parallel program development, simulation based approach, portable-parallel programs, Charm, message driven programming environment, program portability, MIMD parallel systems, single debugging environment, portable parallel software, parallel programming, parallel architectures, feedback, program verification, performance prediction, parallel systems, program debugging, software portability, program correctness, performance debugging, performance bottlenecks, MIMD architectures, program performance
21	Martin C. Herbordt, Charles C. Weems	An empirical study of datapath, memory hierarchy, and network in SIMD array architectures.	ICCD	1995	DBLP DOI BibTeX RDF	SIMD array architectures, SIMD arrays, ENPASSANT, router network, local transfers, performance evaluation, performance, parallel architectures, broadcast, virtual machines, memory hierarchy, reduction, associativity, memory architecture, cache storage, simulation environment, datapath, block size
21	Alan Olson, Kang G. Shin	Fault-Tolerant Routing in Mesh Architectures.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	distributedcomputing system, fault-tolerant routing algorithm, routing scheme performance, square meshes, high probability, parallel architectures, fault tolerant computing, message passing, software reliability, network routing, torus, fault-tolerant routing, message routing, destination, parallelalgorithms, source, mesh architectures, hexagonal mesh, hexagonal meshes
21	Mayez A. Al-Mouhamed	Analysis of Macro-Dataflow Dynamic Scheduling on Nonuniform Memory Access Architectures.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	macro-dataflow dynamic scheduling, nonuniform memory access architectures, computational tasks, least-communication, finish time, first-come first-served scheduling, scheduling, computational complexity, parallel programming, parallel architectures, time complexity, granularity, communication costs, data transfer, multiprocessing programs, scheduling heuristic
21	Gilbert C. Sih, Edward A. Lee	A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	spatial dimensions, compile-time scheduling heuristic, interconnection-constrainedheterogeneous processor architectures, dynamic level scheduling, communicating tasks, scheduling, parallel architectures, temporal dimensions
21	Chaitali Chakrabarti, Joseph F. JáJá	Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	discrete Hartley, prime factor decomposition, two-dimensional systolic arrays, binary arithmetic, parallel architectures, fast Fourier transforms, discrete cosine transforms, hardware design, systolic architectures
21	A. L. Narasimha Reddy, Prithviraj Banerjee	Design, Analysis, and Simulation of I/O Architectures for Hypercube.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	I/O architectures, I/O access, disk organizations, scientific workload, performance evaluation, parallelism, data structures, parallel architectures, multiprocessor interconnection networks, multiprocessing systems, memory architecture, matrices, hypercube multiprocessors, multiprocessor network
21	Mark A. Yoder, Leah H. Jamieson	Simulation of a Word Recognition System on Two Parallel Architectures.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	word recognition system, VLSI processor array, 8-MHz MC68000, 12-MHz Intel 8051, simulations, parallel algorithms, parallel algorithms, parallel architectures, parallel architectures, speech recognition, SIMD, digital simulation
21	Steven R. Vegdahl	A Survey of Proposed Architectures for the Execution of Functional Languages.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	demand-drive architectures, programming languages, functional programming, Computer architecture, data flow, multiprocessing, data-driven architectures
21	Haeng-Kon Kim, Roger Y. Lee	MS2Web: Applying MDA and SOA to Web Services.	Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing	2008	DBLP DOI BibTeX RDF	SOA (Service Oriented Architecture), MDA(Model Driven Architectures), WSDL(Web Services Description Language), Dynamic Web services, Model Translation
21	Yan Liu 0001, Muhammad Ali Babar 0001, Ian Gorton	Middleware Architecture Evaluation for Dependable Self-managing Systems.	QoSA	2008	DBLP DOI BibTeX RDF
21	Heiko Koziolek, Roland Weiss, Jens Doppelhamer	Evolving Industrial Software Architectures into a Software Product Line: A Case Study.	QoSA	2009	DBLP DOI BibTeX RDF
21	Heiko Koziolek, Steffen Becker 0001, Jens Happe	Predicting the Performance of Component-Based Software Architectures with Different Usage Profiles.	QoSA	2007	DBLP DOI BibTeX RDF
21	Vincenzo Grassi, Raffaela Mirandola, Antonino Sabetta	An XML-Based Language to Support Performance and Reliability Modeling and Analysis in Software Architectures.	QoSA/SOQUA	2005	DBLP DOI BibTeX RDF
21	Werner Damm, Gert Döhmen	An Axiomatic Approach to the Specification of Distributed Computer Architectures.	PARLE (1)	1987	DBLP DOI BibTeX RDF
21	Adrian Paschke, Paul Vincent	A reference architecture for Event Processing.	DEBS	2009	DBLP DOI BibTeX RDF	system architectures, complex event processing, reference architecture, domain-specific architectures
21	Mehboob Alam, Wael M. Badawy, Vassil S. Dimitrov, Graham A. Jullien	An Efficient Architecture for a Lifted 2D Biorthogonal DWT.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	biorthogonal transform, wavelet architectures, lifted architectures, Mallats algorithms, image compression, discrete wavelet transforms, lifting
21	Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu	ARAS: asynchronous RISC architecture simulator.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing
21	Gary S. H. Tan, Yong Meng Teo	Experiences in simulating a declarative multiprocessor.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	declarative multiprocessor simulation, declarative programming languages, Flagship parallel reduction machine, packet-based graph reduction model, executional units, timing characteristics, event-driven timing scheme, tightly-coupled processor-store pairs, performance evaluation, performance evaluation, parallel architectures, virtual machines, timing, parallel machines, synchronisation, synchronisation, parallel languages, functional languages, functional languages, functional simulator, parallel computer architectures, MIMD architecture, delta network
21	Robert Yung, Neil C. Wilhelm	Caching processor general registers.	ICCD	1995	DBLP DOI BibTeX RDF	caching processor general registers, processor cycle time requirements, small register cache, register caching, windowed-register architectures, parallel architectures, performance model, memory architecture, cache storage, register file
21	Jeffrey S. Chase, Henry M. Levy, Michael J. Feeley, Edward D. Lazowska	Sharing and Protection in a Single-Address-Space Operating System.	ACM Trans. Comput. Syst.	1994	DBLP DOI BibTeX RDF	capability-based systems, microkernel operating systems, single-address-space operating systems, wide-address architectures, protection, object-oriented database systems, persistent storage, 64-bit architectures
21	Goetz Graefe, Diane L. Davison	Encapsulation of Parallelism and Architecture-Independence in Extensible Database Query Execution.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	extensible database query execution, database application domains, high functionality, Volcano query execution engine, query processing operators, arbitrarily complex query evaluation plans, data manipulation operators, exchange operator, generalized exchange operator, database query processing software, bit vector filtering, parallel programming, parallelism, query processing, debugging, distributed databases, computer architectures, high performance, hierarchical architectures
21	Jean-Luc Gaudiot, Andrew Sohn	Data-Driven Parallel Production Systems.	IEEE Trans. Software Eng.	1990	DBLP DOI BibTeX RDF	parallel production systems, data-flow principles, high programmability, data-driven principles, RETE match algorithm, actor set, program graph design, tagged data-flow computer, deterministic simulation, artificial intelligence production systems, parallel programming, parallel architectures, expert systems, symbolic computations, symbol manipulation, multiprocessor architecture, numerical computations, multiprocessor environment, data-driven architectures
20	Pavel G. Zaykov, Georgi Kuzmanov, Georgi Nedeltchev Gaydadjiev	Reconfigurable Multithreading Architectures: A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF
20	Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero	FAME: FAirly MEasuring Multithreaded Architectures.	PACT	2007	DBLP DOI BibTeX RDF
20	Aino Vonge Corry, Klaus Marius Hansen, David Svensson	Traveling Architects - A New Way of Herding Cats.	QoSA	2006	DBLP DOI BibTeX RDF
20	Arjun K. Pai, Khaled Benkrid, Danny Crookes	Embedded Reconfigurable DCT Architectures Using Adder-Based Distributed Arithmetic.	CAMP	2005	DBLP DOI BibTeX RDF
20	Esther Salamí, Mateo Valero	Initial Evaluation of Multimedia Extensions on VLIW Architectures.	SAMOS	2004	DBLP DOI BibTeX RDF
20	Yi Qian, Steve Carr 0001, Philip H. Sweany	Optimizing Loop Performance for Clustered VLIW Architectures.	IEEE PACT	2002	DBLP DOI BibTeX RDF
20	Peter Pirsch, Achim Freimann, C. Klar, Jens Peter Wittenburg	Processor Architectures for Multimedia Applications.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
20	Alexander Egyed, Nikunj R. Mehta, Nenad Medvidovic	Software Connectors and Refinement in Family Architectures.	IW-SAPF	2000	DBLP DOI BibTeX RDF
20	Simone Marini, Maurizio Martelli, Viviana Mascardi, Floriano Zini	Specification of Heterogeneous Agent Architectures.	ATAL	2000	DBLP DOI BibTeX RDF
20	Vijay Anand Korthikanti, Gul Agha	Towards optimizing energy costs of algorithms for shared memory architectures.	SPAA	2010	DBLP DOI BibTeX RDF	performance, parallel algorithms, energy, shared memory architectures
20	Muhammad Umar Farooq 0003, Lizy Kurian John, Margarida F. Jacome	Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures.	HiPEAC	2009	DBLP DOI BibTeX RDF	Tiled dataflow architectures, predication, power-performance trade-offs
20	Nicola Zingirian, Massimo Maresca	Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures.	CAMP	2000	DBLP DOI BibTeX RDF	loop regularization, instruction level parallel architectures, instruction reordering, image processing, embedded systems, embedded systems, video processing, digital signal processors, register renaming
20	Stijn Notebaert, Jan De Cock, Samie Beheydt, Jan de Lameillieure, Rik Van de Walle	Mixed architectures for H.264/AVC digital video transrating.	Multim. Tools Appl.	2009	DBLP DOI BibTeX RDF	Transrating, H.264/AVC, Transcoding, Video signal processing, Requantization
20	Behzad Khademian, Keyvan Hashtrudi-Zaad	Novel shared control architectures for enhanced users' interaction in haptic training simulation systems.	IROS	2009	DBLP DOI BibTeX RDF
20	Junchang Wang, Haipeng Cheng, Bei Hua, Xinan Tang	Practice of parallelizing network applications on multi-core architectures.	ICS	2009	DBLP DOI BibTeX RDF	application-level protocol processing, deep content inspection, lock-free data structures, multi-core parallelization, pipelining implementation, tcp/ip protocol processing
20	Sebastian Lange, Martin Middendorf	Design Aspects of Multi-level Reconfigurable Architectures.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	multi-level reconfiguration, dynamic reconfiguration, reconfigurable architecture
20	Min Li 0001, Bruno Bougard, Weiyu Xu, David Novo, Liesbet Van der Perre, Francky Catthoor	Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures.	DATE	2008	DBLP DOI BibTeX RDF
20	Venkatesan Packirisamy, Yangchun Luo, Wei-Lung Hung, Antonia Zhai, Pen-Chung Yew, Tin-Fook Ngai	Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective.	ICCD	2008	DBLP DOI BibTeX RDF
20	Stephen Neuendorffer, Kees A. Vissers	Streaming Systems in FPGAs.	SAMOS	2008	DBLP DOI BibTeX RDF	digital convergence, FPGAs, dataflow
20	Wangyuan Zhang, Xin Fu, Tao Li 0006, José A. B. Fortes	An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures.	ISPASS	2007	DBLP DOI BibTeX RDF	thread-aware reliability optimization, microarchitecture vulnerability, simultaneous multithreaded architecture, semiconductor transient fault, microprocessor reliability, processor throughput, soft error vulnerability analysis, SPEC CPU 2000 benchmark, microarchitecture structure, microarchitecture reliability profile, fetch policy, thread-level parallelism, multithreading architecture
20	Rahul Nagpal, Y. N. Srikant	Register File Energy Optimization for Snooping Based Clustered VLIW Architectures.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
20	Assem Kaylani, Ahmad A. Al-Daraiseh, Michael Georgiopoulos, Mansooreh Mollaghasemi, Georgios C. Anagnostopoulos, Annie S. Wu	Genetic Optimization of ART Neural Network Architectures.	IJCNN	2007	DBLP DOI BibTeX RDF
20	Yu-Wen Huang, Ching-Yeh Chen, Chen-Han Tsai, Chun-Fu Shen, Liang-Gee Chen	Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	global elimination algorithm, motion estimation, VLSI architecture, block matching
20	Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Valerie E. Taylor, Paul S. Graham, Maya B. Gokhale	A hybrid framework for design and analysis of fault-tolerant architectures.	DATE	2006	DBLP DOI BibTeX RDF
20	Sasa Junuzovic, Prasun Dewan	Response times in N-user replicated, centralized, and proximity-based hybrid collaboration architectures.	CSCW	2006	DBLP DOI BibTeX RDF	analytical model, response time, collaboration architecture
20	Zhiyuan Yan	Digit-Serial Systolic Architectures for Inversions over GF(2m).	SiPS	2006	DBLP DOI BibTeX RDF
20	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	On-FPGA Communication Architectures and Design Factors.	FPL	2006	DBLP DOI BibTeX RDF
20	Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai	Clock Distribution Architectures: A Comparative Study.	ISQED	2006	DBLP DOI BibTeX RDF
20	Indra Widjaja	Next-Generation Packet Network Architectures with Decoupled Service Plane and Transport Plane.	BROADNETS	2006	DBLP DOI BibTeX RDF