Search results for "ISPD"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Geoffrey C.-F. Yeap	Leakage current in low standby power and high performance devices: trends and challenges.	ISPD	2002	DBLP DOI BibTeX RDF	gate tunneling leakage, low standby power, off-state sub-threshold leakage, system-on-a-ship (SoC), high performance, CMOS technology, leakage current
1	Prashant Saxena, Satyanarayan Gupta	Shield count minimization in congested regions.	ISPD	2002	DBLP DOI BibTeX RDF	power routing, routing, noise, layout, crosstalk, shielding, high performance design, domino circuits
1	Steven L. Teig	Challenges and principles of physical design.	ISPD	2002	DBLP DOI BibTeX RDF
1	Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen	Twin binary sequences: a non-redundant representation for general non-slicing floorplan.	ISPD	2002	DBLP DOI BibTeX RDF
1	Sachin S. Sapatnekar, Massoud Pedram (eds.)	Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002	ISPD	2002	DBLP DOI BibTeX RDF
1	H. Chang, Eugene Shragowitz, Jian Liu, Habib Youssef, Bing Lu, Suphachai Sutanthavibul	Net criticality revisited: an effective method to improve timing in physical design.	ISPD	2002	DBLP DOI BibTeX RDF	criticality metrics, net delay bound, routing, placement
1	Bo Hu 0006, Malgorzata Marek-Sadowska	FAR: fixed-points addition & relaxation based placement.	ISPD	2002	DBLP DOI BibTeX RDF
1	Jason Cong	Timing closure based on physical hierarchy.	ISPD	2002	DBLP DOI BibTeX RDF	interconnect planning, logic hierarchy, physical hierarchy, retiming and pipelining, sequential arrival time, interconnect optimization, timing closure, multilevel optimization
1	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.	ISPD	2002	DBLP DOI BibTeX RDF	adjoint sensitivity, optimization, placement, ASICs, decoupling capacitor, power grid noise
1	Wai-Kei Mak, Evangeline F. Y. Young	Temporal logic replication for dynamically reconfigurable FPGA partitioning.	ISPD	2002	DBLP DOI BibTeX RDF
1	Yongseok Cheon, D. F. Wong 0001	Design hierarchy guided multilevel circuit partitioning.	ISPD	2002	DBLP DOI BibTeX RDF	clustering, Rent's rule, circuit partitioning, design hierarchy
1	Andrew B. Kahng	A roadmap and vision for physical design.	ISPD	2002	DBLP DOI BibTeX RDF
1	Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay	Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.	ISPD	2002	DBLP DOI BibTeX RDF
1	Phillip J. Restle, Albert E. Ruehli, Steven G. Walker	Multi-GHz interconnect effects in microprocessors.	ISPD	2001	DBLP DOI BibTeX RDF	full-wave analysis, simulation, interconnect, inductance, extraction, clock distribution, circuit-tuning
1	Yih-Chih Chou, Youn-Long Lin	A performance-driven standard-cell placer based on a modified force-directed algorithm.	ISPD	2001	DBLP DOI BibTeX RDF	placement, timing closure, force-directed
1	Majid Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner, Ankur Srivastava 0001	Design and analysis of physical design algorithms.	ISPD	2001	DBLP DOI BibTeX RDF
1	Kolja Sulimma, Wolfgang Kunz	An exact algorithm for solving difficult detailed routing problems.	ISPD	2001	DBLP DOI BibTeX RDF
1	Stephen P. Boyd, Lieven Vandenberghe, Abbas El Gamal, Sunghee Yun	Design of robust global power and ground networks.	ISPD	2001	DBLP DOI BibTeX RDF	interconnect sizing, power and ground network design, convex optimization
1	Wei-Jin Dai	Hierarchical physical design methodology for multi-million gate chips.	ISPD	2001	DBLP DOI BibTeX RDF	physical prototype, partitioning, placement, floorplanning, deep sub-micron, hierarchical design
1	Yingxin Pang, Chung-Kuan Cheng, Koen Lampaert, Weize Xie	Rectilinear block packing using O-tree representation.	ISPD	2001	DBLP DOI BibTeX RDF
1	Ruiqi Tian, Xiaoping Tang, D. F. Wong 0001	Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process.	ISPD	2001	DBLP DOI BibTeX RDF
1	Franklin M. Schellenberg, Luigi Capodieci	Impact of RET on physical layouts.	ISPD	2001	DBLP DOI BibTeX RDF	off-axis illumination, physical verification, simulation, DFM, OPC, lithography, RET, phase-shifting, PSM
1	Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu 0001, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia	Buffered Steiner trees for difficult instances.	ISPD	2001	DBLP DOI BibTeX RDF
1	Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham	Revisiting floorplan representations.	ISPD	2001	DBLP DOI BibTeX RDF
1	Rajeev Jayaraman	Physical design for FPGAs.	ISPD	2001	DBLP DOI BibTeX RDF	FPGA, routing, placement, physical design
1	Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani	Consistent floorplanning with super hierarchical constraints.	ISPD	2001	DBLP DOI BibTeX RDF
1	Sachin S. Sapatnekar, Manfred Wiesel (eds.)	Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001	ISPD	2001	DBLP DOI BibTeX RDF
1	Fook-Luen Heng, Lars Liebmann, Jennifer Lund	Application of automated design migration to alternating phase shift mask design.	ISPD	2001	DBLP DOI BibTeX RDF	design migration, phase-shifting mask, resolution enchancement technique
1	Jinan Lou, Shankar Krishnamoorthy, Henry S. Sheng	Estimating routing congestion using probabilistic analysis.	ISPD	2001	DBLP DOI BibTeX RDF
1	Andrew R. Conn, Chandramouli Visweswariah	Overview of continuous optimization advances and applications to circuit tuning.	ISPD	2001	DBLP DOI BibTeX RDF
1	Zhaoyun Xing, Russell Kao	A minimum cost path search algorithm through tile obstacles.	ISPD	2001	DBLP DOI BibTeX RDF	shortest path search, VLSI routing
1	Wai-Kei Mak	Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead.	ISPD	2001	DBLP DOI BibTeX RDF	minimum cut, circuit partitioning, logic replication
1	Warren Grobman, Robert Boone, Cece Philbin, Bob Jarvis	Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs.	ISPD	2001	DBLP DOI BibTeX RDF
1	Nancy Nettleton, Wolfgang Roethig, D. Hill, Majid Sarrafzadeh	Differences in ASIC, COT and processor design (panel).	ISPD	2001	DBLP DOI BibTeX RDF	ASIC
1	Ting-Yuan Wang, Charlie Chung-Ping Chen	Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method.	ISPD	2001	DBLP DOI BibTeX RDF
1	En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang	Slicing floorplan design with boundary-constrained modules.	ISPD	2001	DBLP DOI BibTeX RDF
1	Yangdong Deng, Wojciech Maly	Interconnect characteristics of 2.5-D system integration scheme.	ISPD	2001	DBLP DOI BibTeX RDF	2.5-D system integration, bounded sliceline grid, VLSI, partition, placement, floorplanning, wirelength
1	Fei Li 0003, Lei He 0001	Maximum current estimation considering power gating.	ISPD	2001	DBLP DOI BibTeX RDF	low-power design, ATPG, power estimation, power gating
1	Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje	Overcoming wireload model uncertainty during physical design.	ISPD	2001	DBLP DOI BibTeX RDF
1	Sabyasachi Das, Sunil P. Khatri	A regularity-driven fast gridless detailed router for high frequency datapath designs.	ISPD	2001	DBLP DOI BibTeX RDF
1	Patrick H. Madden	Reporting of standard cell placement results.	ISPD	2001	DBLP DOI BibTeX RDF
1	Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh	Congestion estimation during top-down placement.	ISPD	2001	DBLP DOI BibTeX RDF
1	Kaustav Banerjee, Massoud Pedram, Amir H. Ajami	Analysis and optimization of thermal issues in high-performance VLSI.	ISPD	2001	DBLP DOI BibTeX RDF
1	Ankireddy Nalamalpu, Wayne P. Burleson	Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters.	ISPD	2001	DBLP DOI BibTeX RDF	methodology, timing, interconnect, buffering
1	Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh	An exact algorithm for coupling-free routing.	ISPD	2001	DBLP DOI BibTeX RDF
1	Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar	A comparative study of two Boolean formulations of FPGA detailed routing constraints.	ISPD	2001	DBLP DOI BibTeX RDF
1	Tao Lin, Lawrence T. Pileggi	RC(L) interconnect sizing with second order considerations via posynomial programming.	ISPD	2001	DBLP DOI BibTeX RDF	RC trees, VLSI design automation, central moments, posynomiality, convex programming, interconnect optimization
1	Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu	ECBL: an extended corner block list with solution space including optimum placement.	ISPD	2001	DBLP DOI BibTeX RDF
1	Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh	Decoupling capacitance allocation for power supply noise suppression.	ISPD	2001	DBLP DOI BibTeX RDF	interconnect sizing, power and ground network design, convex optimization
1	Rob A. Rutenbar, John M. Cohn	Layout tools for analog ICs and mixed-signal SoCs: a survey.	ISPD	2000	DBLP DOI BibTeX RDF
1	Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou	Optimal reliable crosstalk-driven interconnect optimization.	ISPD	2000	DBLP DOI BibTeX RDF
1	Li-Fu Chang, Keh-Jeng Chang, Robert Mathews	Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects.	ISPD	2000	DBLP DOI BibTeX RDF	cladding material, copper interconnect, electromagnetic field solvers, skin-effect current distribution
1	Frank Schmiedle, Daniel Unruh, Bernd Becker 0001	Exact switchbox routing with search space reduction.	ISPD	2000	DBLP DOI BibTeX RDF
1	Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap	A two moment RC delay metric for performance optimization.	ISPD	2000	DBLP DOI BibTeX RDF
1	Chin-Chih Chang, Jason Cong	Pseudo pin assignment with crosstalk noise control.	ISPD	2000	DBLP DOI BibTeX RDF
1	Xiaojian Yang, Maogang Wang, Kenneth Eguro, Majid Sarrafzadeh	A snap-on placement tool.	ISPD	2000	DBLP DOI BibTeX RDF
1	Lauren Hui Chen, Malgorzata Marek-Sadowska	Aggressor alignment for worst-case coupling noise.	ISPD	2000	DBLP DOI BibTeX RDF	aggressor alignment, interconnect coupling, signal integrity, crosstalk noise, timing window
1	Yu-Yen Mo, Chris C. N. Chu	A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization.	ISPD	2000	DBLP DOI BibTeX RDF
1	Maogang Wang, Xiaojian Yang, Kenneth Eguro, Majid Sarrafzadeh	Multi-center congestion estimation and minimization during placement.	ISPD	2000	DBLP DOI BibTeX RDF
1	Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong	Floorplan area minimization using Lagrangian relaxation.	ISPD	2000	DBLP DOI BibTeX RDF
1	Rony Kay, Rob A. Rutenbar	Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution.	ISPD	2000	DBLP DOI BibTeX RDF
1	Patrick Groeneveld, Jacob Greidinger, J. George Janac, Wilm E. Donath	The right floorplanning formulations for future chip implementation methodologies (panel discussion - title only).	ISPD	2000	DBLP DOI BibTeX RDF
1	Masanori Hashimoto, Hidetoshi Onodera	A performance optimization method by gate sizing using statistical static timing analysis.	ISPD	2000	DBLP DOI BibTeX RDF
1	Christoph Albrecht	Provably good global routing by a new approximation algorithm for multicommodity flow.	ISPD	2000	DBLP DOI BibTeX RDF
1	Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert	Datapath routing based on a decongestion metric.	ISPD	2000	DBLP DOI BibTeX RDF
1	D. Hill, Mark Gilbreath, Wayne Heideman, J. George Janac, Adriaan Ligtenberg	EDA and the Internet (panel session - title only).	ISPD	2000	DBLP DOI BibTeX RDF
1	Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh	Routability-driven repeater block planning for interconnect-centric floorplanning.	ISPD	2000	DBLP DOI BibTeX RDF
1	Hai Zhou 0001, Adnan Aziz	Buffer minimization in pass transistor logic.	ISPD	2000	DBLP DOI BibTeX RDF
1	Evanthia Papadopoulou	Critical area computation for missing material defects in VLSI circuits.	ISPD	2000	DBLP DOI BibTeX RDF
1	I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong 0001	Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion.	ISPD	2000	DBLP DOI BibTeX RDF
1	Lei He 0001, Kevin M. Lepak	Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization.	ISPD	2000	DBLP DOI BibTeX RDF	VLSI design automation, net ordering, noise minimization, shielding
1	Manfred Wiesel, Dwight D. Hill (eds.)	Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000	ISPD	2000	DBLP DOI BibTeX RDF
1	Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi 0001	A practical clock tree synthesis for semi-synchronous circuits.	ISPD	2000	DBLP DOI BibTeX RDF	clock-input timing, environmental and manufacturing conditions, semi-synchronous, various timing clock tree, zero skew clock tree, clock scheduling
1	Andrew B. Kahng	Classical floorplanning harmful?	ISPD	2000	DBLP DOI BibTeX RDF	VLSI floorplanning, block packing and layout, coarse placement, hierarchical design methodology
1	Utpal Desai, Simon M. Tam, Robert Kim, Ji Zhang, Stefan Rusu	Itanium processor clock design.	ISPD	2000	DBLP DOI BibTeX RDF	Itanium processor, deskew, on-die-clock-shrink, clock distribution, IA-64
1	Jason Cong, Jie Fang, Kei-Yong Khoo	DUNE: a multi-layer gridless routing system with wire planning.	ISPD	2000	DBLP DOI BibTeX RDF
1	Jason Cong, Majid Sarrafzadeh	Incremental physical design.	ISPD	2000	DBLP DOI BibTeX RDF
1	Rory McInerney, Kurt Leeper, Troy Hill, Heming Chan, Bulent Basaran, Lance McQuiddy	Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor.	ISPD	2000	DBLP DOI BibTeX RDF	RC delay, routing, timing, estimation, microprocessors, floorplan, repeaters
1	Min Ouyang, Michel Toulouse, Krishnaiyan Thulasiraman, Fred W. Glover, Jitender S. Deogun	Multilevel cooperative search: application to the circuit/hypergraph partitioning problem.	ISPD	2000	DBLP DOI BibTeX RDF
1	Naveed A. Sherwani	The bottom-10 problems in EDA (panel session (title only)).	ISPD	2000	DBLP DOI BibTeX RDF
1	Ralph H. J. M. Otten	What is a floorplan?.	ISPD	2000	DBLP DOI BibTeX RDF
1	Xiaoping Tang, D. F. Wong 0001	Planning buffer locations by network flows.	ISPD	2000	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt	Requirements for models of achievable routing.	ISPD	2000	DBLP DOI BibTeX RDF	VLSI routing estimation, interconnect process optimization, via impact model
1	Yingxin Pang, Chung-Kuan Cheng, Takeshi Yoshimura	An enhanced perturbing algorithm for floorplan design using the O-tree representation.	ISPD	2000	DBLP DOI BibTeX RDF
1	Dennis Sylvester, Kurt Keutzer	Getting to the bottom of deep submicron II: a global wiring paradigm.	ISPD	1999	DBLP DOI BibTeX RDF
1	Paul B. Morton, Wayne Wei-Ming Dai	An efficient sequential quadratic programming formulation of optimal wire spacing for cross-talk noise avoidance routing.	ISPD	1999	DBLP DOI BibTeX RDF
1	Jeff Parkhurst, Naveed A. Sherwani, Sury Maturi, Dana Ahrams, Eli Chiprout	SRC physical design top ten problem.	ISPD	1999	DBLP DOI BibTeX RDF
1	Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov	Partitioning with terminals: a "new" problem and new benchmarks.	ISPD	1999	DBLP DOI BibTeX RDF
1	Kunihiro Fujiyoshi, Hiroshi Murata	Arbitrary convex and concave rectilinear block packing using sequence-pair.	ISPD	1999	DBLP DOI BibTeX RDF
1	Maogang Wang, Majid Sarrafzadeh	On the behavior of congestion minimization during placement.	ISPD	1999	DBLP DOI BibTeX RDF
1	Joachim Pistorius, Edmée Legai, Michel Minoux	Generation of very large circuits to benchmark the partitioning of FPGA.	ISPD	1999	DBLP DOI BibTeX RDF	Internet
1	Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov	Optimal partitioners and end-case placers for standard-cell layout.	ISPD	1999	DBLP DOI BibTeX RDF
1	Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai	Post-routing timing optimization with routing characterization.	ISPD	1999	DBLP DOI BibTeX RDF
1	Desmond Kirkpatrick	The deep sub-micron signal integrity challenge.	ISPD	1999	DBLP DOI BibTeX RDF
1	Fung Yu Young, D. F. Wong 0001	Slicing floorplans with range constraint.	ISPD	1999	DBLP DOI BibTeX RDF
1	Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang	Interconnect thermal modeling for determining design limits on current density.	ISPD	1999	DBLP DOI BibTeX RDF
1	Amit Singh 0001, Malgorzata Marek-Sadowska	Circuit clustering using graph coloring.	ISPD	1999	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Y. C. Pati	Subwavelength optical lithography: challenges and impact on physical design.	ISPD	1999	DBLP DOI BibTeX RDF
1	Jason Cong, Jie Fang, Kei-Yong Khoo	VIA design rule consideration in multi-layer maze routing algorithms.	ISPD	1999	DBLP DOI BibTeX RDF
1	Phiroze N. Parakh, Richard B. Brown	Crosstalk constrained global route embedding.	ISPD	1999	DBLP DOI BibTeX RDF

Publications at "ISPD"( http://dblp.L3S.de/Venues/ISPD )