|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 26884 occurrences of 7514 keywords
|
|
|
Results
Found 51597 publication records. Showing 51597 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
22 | Qing Yang 0001 |
Performance Analysis of a Cache-Coherent Multiprocessor Based on Hierarchical Multiple Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARBASE / Architectures ![In: Parallel Architectures (Postconference PARBASE-90)., pp. 260-275, 1990, IEEE Computer Society, 0-8186-9166-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Mohan Ahuja, Kannan Varadhan, Amitabh Sinha |
Flush Message Passing in Communicating Sequential Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARBASE / Architectures ![In: Parallel Architectures (Postconference PARBASE-90)., pp. 31-47, 1990, IEEE Computer Society, 0-8186-9166-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Hessa Al-Jaber, Shmuel Rotenstreich |
Fault Tolerance of Message Delivery with Cascading Copies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARBASE / Architectures ![In: Parallel Architectures (Postconference PARBASE-90)., pp. 48-67, 1990, IEEE Computer Society, 0-8186-9166-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | T. D. Roziner |
Systolic Macropipelines for Multidimensional Fourier Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARBASE / Architectures ![In: Parallel Architectures (Postconference PARBASE-90)., pp. 216-230, 1990, IEEE Computer Society, 0-8186-9166-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Peter J. Varman, Balakrishna R. Iyer, Donald J. Haderle |
Parallel Merging on Shared and Distributed Memory Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARBASE / Architectures ![In: Parallel Architectures (Postconference PARBASE-90)., pp. 231-249, 1990, IEEE Computer Society, 0-8186-9166-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Jai Eun Jang |
An Optimal Fault-Tolerant Broadcasting Algorithm for a Cube-Connected Cycles Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARBASE / Architectures ![In: Parallel Architectures (Postconference PARBASE-90)., pp. 124-140, 1990, IEEE Computer Society, 0-8186-9166-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Jie Wu 0001, Eduardo B. Fernández |
The Extended G-Network, a Fault-Tolerant Interconnection Network for the Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARBASE / Architectures ![In: Parallel Architectures (Postconference PARBASE-90)., pp. 250-259, 1990, IEEE Computer Society, 0-8186-9166-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | V. Prasad Krothapalli, P. Sadayappan |
Dynamic Scheduling of DOACROSS Loops for Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARBASE / Architectures ![In: Parallel Architectures (Postconference PARBASE-90)., pp. 141-160, 1990, IEEE Computer Society, 0-8186-9166-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Manohar Rao, Zary Segall |
Implementation and Evaluation of a Parallel PMS Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARBASE / Architectures ![In: Parallel Architectures (Postconference PARBASE-90)., pp. 201-215, 1990, IEEE Computer Society, 0-8186-9166-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Andreas Alexander Albrecht, Hermann Jung 0001, Kurt Mehlhorn (eds.) |
Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![Springer, 3-540-18099-0 The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Didier Ferment, Brigitte Rozoy |
Solutions for the Distributed Termination Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 114-121, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Edgar Körner, T. Tsuda, H. Shimizu |
Parallel in Sequence - Towards the Architecture of an Elementary Cortical Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 37-47, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Akihiko Konagaya, Ryosei Nakazaki, Mamoru Umemura |
A Co-Operative Programming Environment for a Back-End Type Sequential Inference Machine CHI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 196-205, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Helmut Alt, Torben Hagerup, Kurt Mehlhorn, Franco P. Preparata |
Deterministic Simulation of Idealized Parallel Computers on more Realistic Ones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 11-15, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Burkhard Monien, Oliver Vornberger |
Parallel Processing of Combinatorial Search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 60-69, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Clark D. Thomborson, Linda L. Deneen, Gary M. Shute |
Computing a Rectilinear Steiner Minimal Tree in nO(sqrt(n)) Time. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 176-183, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Nikolay N. Mirenkov |
Parallel Algorithms and Static Analysis of Parallel Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 48-59, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Chee-Keng Yap |
What Can be Parallelized in Computational Geometry?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 184-195, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Tetsuo Asano, Hiroshi Umeo |
Systolic Algorithms for Computing the Visibility Polygon and Triangulation of A Polygonal Region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 77-85, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Krzysztof Diks |
Parallel Recognition of Outerplanar Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 105-113, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Wojciech Rytter, Raffaele Giancarlo |
Optimal Parallel Parsing of Bracket Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 146-154, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Reiner Creutzburg |
Parallel Linear Conflict-Free Subtree Access. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 89-96, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Alberto Apostolico, Costas S. Iliopoulos, Robert Paige |
On O(n log n) Cost Parallel Algorithm for the Single Function Coarsest Partition Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 70-76, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Rex A. Dwyer, Ravi Kannan |
Convex Hull of Randomly Chosen Points from A Polytope. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 16-24, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | D. De Baer, Jan Paredaens |
A Formal Definition for Systolic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 97-104, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Friedmar Wächter |
Optimization of Special Permutation Networks Using Simple Algebraic Relations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 169-174, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Lothar Budach, Ernst-Günter Giessmann, Hubert Grassmann, Bernd Graw, Christoph Meinel |
RELACS - A Recursive Layout Computing System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 86-88, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Wojciech Rytter |
A Note on Optimal Parallel Transformations of Regular Expressions to Nondeterministic Finite Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 138-145, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Imrich Vrto |
Area-time Tradeoffs for Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 163-168, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Dietmar Uhlig |
On Reliable Networks from Unreliable Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 155-162, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Jayantha A. Herath, Toshitsugu Yuba, Nobuo Saito |
Dataflow Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 25-36, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Michael Gössel, R. Rebel |
Memories for Parallel Subtree-Access. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 122-130, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Shogo Matsui, Yoshinobu Kato, Shinsuke Teramura, Tomoyuki Tanaka, Nobuyuki Mohri, Atsushi Maeda, Masakazu Nakanishi |
SYNAPSE: A Multi-Microprocessor Lisp Machine with Parallel Garbage Collector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Algorithms and Architectures ![In: Parallel Algorithms and Architectures, International Workshop, Suhl, GDR, May 25-30, 1987, Proceedings, pp. 131-137, 1987, Springer, 3-540-18099-0. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
22 | Andy Yan, Steven J. E. Wilton |
Product-Term-Based Synthesizable Embedded Programmable Logic Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(5), pp. 474-488, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Deepak Rautela, Rajendra S. Katti |
Efficient utilization of heterogeneous routing resources for FPGAs (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 264, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki |
Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 30(1), pp. 29, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
nonuniform cache architectures, parallel architectures, multicore, cache memories, data placement |
21 | Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi |
Compiling custom instructions onto expression-grained reconfigurable architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 51-60, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
horizontal microprogramming, compilers, instruction set extensions, coarse-grained reconfigurable architectures, data-flow architectures |
21 | Jayaram Mudigonda, Harrick M. Vin, Stephen W. Keckler |
Reconciling performance and programmability in networking systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM SIGCOMM 2007 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications, Kyoto, Japan, August 27-31, 2007, pp. 73-84, 2007, ACM, 978-1-59593-713-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
memoty bottleneck, multithreading, reconfigurable architectures, routers, data cache, processor architectures, packet processing |
21 | Lawrence Cabac, Michael Duvigneau, Daniel Moldt, Heiko Rölke |
Multi-agent concepts as basis for dynamic plug-in software architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAMAS ![In: 4th International Joint Conference on Autonomous Agents and Multiagent Systems (AAMAS 2005), July 25-29, 2005, Utrecht, The Netherlands, pp. 1157-1158, 2005, ACM, 1-59593-094-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
modeling, multi-agent systems, components, high-level Petri nets, renew, reference nets, nets-within-nets, dynamic software architectures, plug-in architectures, mulan |
21 | Shashank S. Nemawarkar, Guang R. Gao |
Latency Tolerance: A Metric for Performance Analysis of Multithreaded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 227-232, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
performance analysis metric, multithreaded multiprocessor systems, tolerance index, program workload parameters, fine grain parallel program workloads, parallel architectures, multithreaded architectures, latency tolerance, closed queueing networks, analytical framework |
21 | Yunn Yen Chen, Jih-Kwon Peir, Chung-Ta King |
Performance of Shared Cache on Multithreaded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 541-548, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
shared cache performance, trace-driven simulation technique, storage hierarchy system, multithreaded execution environment, multithread scheduling techniques, server/workstation workload mix, MRU priority scheduling scheme, round-robin scheduling method, absolute hit ratio, concurrent threads, simulation, performance evaluation, parallel architectures, shared memory systems, processor scheduling, cache storage, multithreaded architectures, program traces, set associativity, cache size, direct-map cache |
21 | Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe |
Load Balancing in Superscalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 651-, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources |
21 | Zhiwei Xu, Kai Hwang 0001 |
MPPs and clusters for scalable computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 117-123, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
scalable parallel computing, Cray T3D/T3E, ASCI TeraFLOPS, performance evaluation, scalability, parallel architectures, reconfigurable architectures, clusters of workstations, Intel Paragon, Intel, massively parallel processors, performance attributes, scalable computing, MPPs, IBM SP2 |
21 | Issei Numata, Susumu Horiguchi |
Efficient reconfiguration scheme for mesh-connected network: the recursive shift approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 221-227, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
mesh-connected network, recursive shift, faulty processing elements, mesh arrays, redundant processing elements, fault tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, reconfigurable architectures, massively parallel system, reconfiguration scheme |
21 | Mounir Hamdi, Yi Pan 0001 |
Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 440-446, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations |
21 | Virginio Cantoni, Luca Lombardi |
Hierarchical architectures for computer vision. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), January 25-27, 1995, San Remo, Italy, pp. 392-399, 1995, IEEE Computer Society, 0-8186-7031-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
general planning strategies, performance evaluation, computer vision, computer vision, image processing, parallel architectures, hierarchical architectures, computer performance, sensory data |
21 | Arindam Saha |
A simulator for real-time parallel processing architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 28st Annual Simulation Symposium (SS '95), April 25-28, 1995, Santa Barbara, California, USA, pp. 74-83, 1995, IEEE Computer Society, 0-8186-7091-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
real-time parallel processing architectures, time-driven flit-based wormhole-routed parallel processor network simulator, user-friendly graphical user interface, prioritized queues, resource allocation policies, message priorities, average latency convergence, throughput monitoring, communication characteristics, performance, real-time systems, resource allocation, parallel architectures, graphical user interfaces, virtual machines, concurrency control, convergence, deadlocks, virtual channel, overlaps, real-time networks |
21 | Phyllis Crandall, Michael J. Quinn |
Non-uniform 2-D grid partitioning for heterogeneous parallel architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 428-435, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
nonuniform 2D grid partitioning, heterogeneous parallel architectures, uniform computational requirements, block decomposition method, Fair Binary Recursive Decomposition, performance level, performance evaluation, parallel architectures, decomposition technique |
21 | Gopal Chillariga, Balkrishna Ramkumar |
Performance prediction for portable parallel execution on MIMD architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 630-634, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
portable parallel execution, parallel program development, simulation based approach, portable-parallel programs, Charm, message driven programming environment, program portability, MIMD parallel systems, single debugging environment, portable parallel software, parallel programming, parallel architectures, feedback, program verification, performance prediction, parallel systems, program debugging, software portability, program correctness, performance debugging, performance bottlenecks, MIMD architectures, program performance |
21 | Martin C. Herbordt, Charles C. Weems |
An empirical study of datapath, memory hierarchy, and network in SIMD array architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 546-551, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
SIMD array architectures, SIMD arrays, ENPASSANT, router network, local transfers, performance evaluation, performance, parallel architectures, broadcast, virtual machines, memory hierarchy, reduction, associativity, memory architecture, cache storage, simulation environment, datapath, block size |
21 | Alan Olson, Kang G. Shin |
Fault-Tolerant Routing in Mesh Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(11), pp. 1225-1232, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
distributedcomputing system, fault-tolerant routing algorithm, routing scheme performance, square meshes, high probability, parallel architectures, fault tolerant computing, message passing, software reliability, network routing, torus, fault-tolerant routing, message routing, destination, parallelalgorithms, source, mesh architectures, hexagonal mesh, hexagonal meshes |
21 | Mayez A. Al-Mouhamed |
Analysis of Macro-Dataflow Dynamic Scheduling on Nonuniform Memory Access Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(8), pp. 875-888, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
macro-dataflow dynamic scheduling, nonuniform memory access architectures, computational tasks, least-communication, finish time, first-come first-served scheduling, scheduling, computational complexity, parallel programming, parallel architectures, time complexity, granularity, communication costs, data transfer, multiprocessing programs, scheduling heuristic |
21 | Gilbert C. Sih, Edward A. Lee |
A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(2), pp. 175-187, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
spatial dimensions, compile-time scheduling heuristic, interconnection-constrainedheterogeneous processor architectures, dynamic level scheduling, communicating tasks, scheduling, parallel architectures, temporal dimensions |
21 | Chaitali Chakrabarti, Joseph F. JáJá |
Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(11), pp. 1359-1368, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
discrete Hartley, prime factor decomposition, two-dimensional systolic arrays, binary arithmetic, parallel architectures, fast Fourier transforms, discrete cosine transforms, hardware design, systolic architectures |
21 | A. L. Narasimha Reddy, Prithviraj Banerjee |
Design, Analysis, and Simulation of I/O Architectures for Hypercube. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(2), pp. 140-151, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
I/O architectures, I/O access, disk organizations, scientific workload, performance evaluation, parallelism, data structures, parallel architectures, multiprocessor interconnection networks, multiprocessing systems, memory architecture, matrices, hypercube multiprocessors, multiprocessor network |
21 | Mark A. Yoder, Leah H. Jamieson |
Simulation of a Word Recognition System on Two Parallel Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(9), pp. 1269-1284, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
word recognition system, VLSI processor array, 8-MHz MC68000, 12-MHz Intel 8051, simulations, parallel algorithms, parallel algorithms, parallel architectures, parallel architectures, speech recognition, SIMD, digital simulation |
21 | Steven R. Vegdahl |
A Survey of Proposed Architectures for the Execution of Functional Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(12), pp. 1050-1072, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
demand-drive architectures, programming languages, functional programming, Computer architecture, data flow, multiprocessing, data-driven architectures |
21 | Haeng-Kon Kim, Roger Y. Lee |
MS2Web: Applying MDA and SOA to Web Services. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing ![In: Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, pp. 163-180, 2008, Springer, 978-3-540-70559-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SOA (Service Oriented Architecture), MDA(Model Driven Architectures), WSDL(Web Services Description Language), Dynamic Web services, Model Translation |
21 | Yan Liu 0001, Muhammad Ali Babar 0001, Ian Gorton |
Middleware Architecture Evaluation for Dependable Self-managing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QoSA ![In: Quality of Software Architectures. Models and Architectures, 4th International Conference on the Quality of Software-Architectures, QoSA 2008, Karlsruhe, Germany, October 14-17, 2008. Proceedings, pp. 189-204, 2008, Springer, 978-3-540-87878-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Heiko Koziolek, Roland Weiss, Jens Doppelhamer |
Evolving Industrial Software Architectures into a Software Product Line: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QoSA ![In: Architectures for Adaptive Software Systems, 5th International Conference on the Quality of Software Architectures, QoSA 2009, East Stroudsburg, PA, USA, June 24-26, 2009, Proceedings, pp. 177-193, 2009, Springer, 978-3-642-02350-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
21 | Heiko Koziolek, Steffen Becker 0001, Jens Happe |
Predicting the Performance of Component-Based Software Architectures with Different Usage Profiles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QoSA ![In: Software Architectures, Components, and Applications, Third International Conference on Quality of Software Architectures, QoSA 2007, Medford, MA, USA, July 11-23, 2007, Revised Selected Papers, pp. 145-163, 2007, Springer, 978-3-540-77617-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Vincenzo Grassi, Raffaela Mirandola, Antonino Sabetta |
An XML-Based Language to Support Performance and Reliability Modeling and Analysis in Software Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QoSA/SOQUA ![In: Quality of Software Architectures and Software Quality, First International Conference on the Quality of Software Architectures, QoSA 2005 and Second International Workshop on Software Quality, SOQUA 2005, Erfurt, Germany, September 20-22, 2005, Proceedings, pp. 71-87, 2005, Springer, 3-540-29033-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Werner Damm, Gert Döhmen |
An Axiomatic Approach to the Specification of Distributed Computer Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (1) ![In: PARLE, Parallel Architectures and Languages Europe, Volume I: Parallel Architectures, Eindhoven, The Netherlands, June 15-19, 1987, Proceedings, pp. 103-120, 1987, Springer, 3-540-17943-7. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
21 | Adrian Paschke, Paul Vincent |
A reference architecture for Event Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DEBS ![In: Proceedings of the Third ACM International Conference on Distributed Event-Based Systems, DEBS 2009, Nashville, Tennessee, USA, July 6-9, 2009, 2009, ACM, 978-1-60558-665-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
system architectures, complex event processing, reference architecture, domain-specific architectures |
21 | Mehboob Alam, Wael M. Badawy, Vassil S. Dimitrov, Graham A. Jullien |
An Efficient Architecture for a Lifted 2D Biorthogonal DWT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 40(3), pp. 335-342, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
biorthogonal transform, wavelet architectures, lifted architectures, Mallats algorithms, image compression, discrete wavelet transforms, lifting |
21 | Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu |
ARAS: asynchronous RISC architecture simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 210-, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing |
21 | Gary S. H. Tan, Yong Meng Teo |
Experiences in simulating a declarative multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 28st Annual Simulation Symposium (SS '95), April 25-28, 1995, Santa Barbara, California, USA, pp. 95-104, 1995, IEEE Computer Society, 0-8186-7091-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
declarative multiprocessor simulation, declarative programming languages, Flagship parallel reduction machine, packet-based graph reduction model, executional units, timing characteristics, event-driven timing scheme, tightly-coupled processor-store pairs, performance evaluation, performance evaluation, parallel architectures, virtual machines, timing, parallel machines, synchronisation, synchronisation, parallel languages, functional languages, functional languages, functional simulator, parallel computer architectures, MIMD architecture, delta network |
21 | Robert Yung, Neil C. Wilhelm |
Caching processor general registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 307-312, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
caching processor general registers, processor cycle time requirements, small register cache, register caching, windowed-register architectures, parallel architectures, performance model, memory architecture, cache storage, register file |
21 | Jeffrey S. Chase, Henry M. Levy, Michael J. Feeley, Edward D. Lazowska |
Sharing and Protection in a Single-Address-Space Operating System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 12(4), pp. 271-307, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
capability-based systems, microkernel operating systems, single-address-space operating systems, wide-address architectures, protection, object-oriented database systems, persistent storage, 64-bit architectures |
21 | Goetz Graefe, Diane L. Davison |
Encapsulation of Parallelism and Architecture-Independence in Extensible Database Query Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 19(8), pp. 749-764, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
extensible database query execution, database application domains, high functionality, Volcano query execution engine, query processing operators, arbitrarily complex query evaluation plans, data manipulation operators, exchange operator, generalized exchange operator, database query processing software, bit vector filtering, parallel programming, parallelism, query processing, debugging, distributed databases, computer architectures, high performance, hierarchical architectures |
21 | Jean-Luc Gaudiot, Andrew Sohn |
Data-Driven Parallel Production Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 16(3), pp. 281-293, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
parallel production systems, data-flow principles, high programmability, data-driven principles, RETE match algorithm, actor set, program graph design, tagged data-flow computer, deterministic simulation, artificial intelligence production systems, parallel programming, parallel architectures, expert systems, symbolic computations, symbol manipulation, multiprocessor architecture, numerical computations, multiprocessor environment, data-driven architectures |
20 | Pavel G. Zaykov, Georgi Kuzmanov, Georgi Nedeltchev Gaydadjiev |
Reconfigurable Multithreading Architectures: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 263-274, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero |
FAME: FAirly MEasuring Multithreaded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 305-316, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Aino Vonge Corry, Klaus Marius Hansen, David Svensson |
Traveling Architects - A New Way of Herding Cats. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QoSA ![In: Quality of Software Architectures, Second International Conference on Quality of Software Architectures, QoSA 2006, Västerås, Sweden, June 27-29, 2006 Revised Papers, pp. 111-126, 2006, Springer, 3-540-48819-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Arjun K. Pai, Khaled Benkrid, Danny Crookes |
Embedded Reconfigurable DCT Architectures Using Adder-Based Distributed Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 4-6 July 2005, Palermo, Italy, pp. 81-86, 2005, IEEE Computer Society, 0-7695-2255-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Esther Salamí, Mateo Valero |
Initial Evaluation of Multimedia Extensions on VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 403-412, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Yi Qian, Steve Carr 0001, Philip H. Sweany |
Optimizing Loop Performance for Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 271-280, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Peter Pirsch, Achim Freimann, C. Klar, Jens Peter Wittenburg |
Processor Architectures for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Embedded Processor Design Challenges ![In: Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, pp. 188-206, 2002, Springer, 3-540-43322-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Alexander Egyed, Nikunj R. Mehta, Nenad Medvidovic |
Software Connectors and Refinement in Family Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IW-SAPF ![In: Software Architectures for Product Families, International Workshop IW-SAPF-3, Las Palmas de Gran Canaria, Spain, March 15-17, 2000, Proceedings, pp. 96-106, 2000, Springer, 3-540-41480-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Simone Marini, Maurizio Martelli, Viviana Mascardi, Floriano Zini |
Specification of Heterogeneous Agent Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATAL ![In: Intelligent Agents VII. Agent Theories Architectures and Languages, 7th International Workshop, ATAL 2000, Boston, MA, USA, July 7-9, 2000, Proceedings, pp. 275-289, 2000, Springer, 3-540-42422-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Vijay Anand Korthikanti, Gul Agha |
Towards optimizing energy costs of algorithms for shared memory architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2010: Proceedings of the 22nd Annual ACM Symposium on Parallelism in Algorithms and Architectures, Thira, Santorini, Greece, June 13-15, 2010, pp. 157-165, 2010, ACM, 978-1-4503-0079-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance, parallel algorithms, energy, shared memory architectures |
20 | Muhammad Umar Farooq 0003, Lizy Kurian John, Margarida F. Jacome |
Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 324-338, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Tiled dataflow architectures, predication, power-performance trade-offs |
20 | Nicola Zingirian, Massimo Maresca |
Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 261-269, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
loop regularization, instruction level parallel architectures, instruction reordering, image processing, embedded systems, embedded systems, video processing, digital signal processors, register renaming |
20 | Stijn Notebaert, Jan De Cock, Samie Beheydt, Jan de Lameillieure, Rik Van de Walle |
Mixed architectures for H.264/AVC digital video transrating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 44(1), pp. 39-64, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Transrating, H.264/AVC, Transcoding, Video signal processing, Requantization |
20 | Behzad Khademian, Keyvan Hashtrudi-Zaad |
Novel shared control architectures for enhanced users' interaction in haptic training simulation systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2009 IEEE/RSJ International Conference on Intelligent Robots and Systems, October 11-15, 2009, St. Louis, MO, USA, pp. 886-892, 2009, IEEE, 978-1-4244-3803-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
20 | Junchang Wang, Haipeng Cheng, Bei Hua, Xinan Tang |
Practice of parallelizing network applications on multi-core architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009, pp. 204-213, 2009, ACM, 978-1-60558-498-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
application-level protocol processing, deep content inspection, lock-free data structures, multi-core parallelization, pipelining implementation, tcp/ip protocol processing |
20 | Sebastian Lange, Martin Middendorf |
Design Aspects of Multi-level Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(1), pp. 23-37, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
multi-level reconfiguration, dynamic reconfiguration, reconfigurable architecture |
20 | Min Li 0001, Bruno Bougard, Weiyu Xu, David Novo, Liesbet Van der Perre, Francky Catthoor |
Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 444-449, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Venkatesan Packirisamy, Yangchun Luo, Wei-Lung Hung, Antonia Zhai, Pen-Chung Yew, Tin-Fook Ngai |
Efficiency of thread-level speculation in SMT and CMP architectures - performance, power and thermal perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 286-293, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Stephen Neuendorffer, Kees A. Vissers |
Streaming Systems in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings, pp. 147-156, 2008, Springer, 978-3-540-70549-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
digital convergence, FPGAs, dataflow |
20 | Wangyuan Zhang, Xin Fu, Tao Li 0006, José A. B. Fortes |
An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 169-178, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
thread-aware reliability optimization, microarchitecture vulnerability, simultaneous multithreaded architecture, semiconductor transient fault, microprocessor reliability, processor throughput, soft error vulnerability analysis, SPEC CPU 2000 benchmark, microarchitecture structure, microarchitecture reliability profile, fetch policy, thread-level parallelism, multithreading architecture |
20 | Rahul Nagpal, Y. N. Srikant |
Register File Energy Optimization for Snooping Based Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 24-27 October 2007, Gramado, RS, Brazil, pp. 161-168, 2007, IEEE Computer Society, 0-7695-3014-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Assem Kaylani, Ahmad A. Al-Daraiseh, Michael Georgiopoulos, Mansooreh Mollaghasemi, Georgios C. Anagnostopoulos, Annie S. Wu |
Genetic Optimization of ART Neural Network Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2007, Celebrating 20 years of neural networks, Orlando, Florida, USA, August 12-17, 2007, pp. 379-384, 2007, IEEE, 978-1-4244-1379-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Yu-Wen Huang, Ching-Yeh Chen, Chen-Han Tsai, Chun-Fu Shen, Liang-Gee Chen |
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 42(3), pp. 297-320, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
global elimination algorithm, motion estimation, VLSI architecture, block matching |
20 | Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Valerie E. Taylor, Paul S. Graham, Maya B. Gokhale |
A hybrid framework for design and analysis of fault-tolerant architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 335-336, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Sasa Junuzovic, Prasun Dewan |
Response times in N-user replicated, centralized, and proximity-based hybrid collaboration architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCW ![In: Proceedings of the 2006 ACM Conference on Computer Supported Cooperative Work, CSCW 2006, Banff, Alberta, Canada, November 4-8, 2006, pp. 129-138, 2006, ACM, 1-59593-249-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
analytical model, response time, collaboration architecture |
20 | Zhiyuan Yan |
Digit-Serial Systolic Architectures for Inversions over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 77-82, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
On-FPGA Communication Architectures and Design Factors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-8, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai |
Clock Distribution Architectures: A Comparative Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 85-91, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Indra Widjaja |
Next-Generation Packet Network Architectures with Decoupled Service Plane and Transport Plane. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BROADNETS ![In: 3rd International Conference on Broadband Communications, Networks, and Systems (BROADNETS 2006), 1-5 October 2006, San José, California, USA, 2006, IEEE, 978-1-4244-0425-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
|
|