Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Guoyong Shi, C.-J. Richard Shi |
Parametric reduced order modeling for interconnect analysis. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Jason Helge Anderson, Farid N. Najm |
Interconnect capacitance estimation for FPGAs. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | James D. Ma, Rob A. Rutenbar |
Interval-valued reduced order statistical interconnect modeling. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Renqiu Huang, Ranga Vemuri |
Analysis and evaluation of a hybrid interconnect structure for FPGAs. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Joel R. Phillips |
Variational interconnect analysis via PMTBR. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Janet Meiling Wang, Praveen Ghanta, Sarma B. K. Vrudhula |
Stochastic analysis of interconnect performance in the presence of process variations. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim |
Analytical Dynamic Time Delay Model of Strongly Coupled RLC Interconnect Lines Dependent on Switching. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Valeriy Sukharev |
Physically-Based Simulation of Electromigration Induced Failures in Copper Dual-Damascene Interconnect. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Yves Quéré, Thierry LeGouguec, Pierre-Marie Martin, Fabrice Huret |
Interconnect Mode Conversion in High-Speed VLSI Circuits. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Mehdi Baradaran Tahoori, Subhasish Mitra |
Interconnect Delay Testing of Designs on Programmable Logic Devices. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Dave Mark, Jenny Fan |
Localizing Open Interconnect Defects using Targeted Routing in FPGA's. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Roberto Ammendola, M. Guagnelli, G. Mazza, Filippo Palombi, Roberto Petronzio, Davide Rossetti, Andrea Salamon, Piero Vicini |
APENet: a high speed, low latency 3D interconnect network. |
CLUSTER |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man |
High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
modeling, model order reduction, substrate noise |
17 | Dmitri B. Chklovskii |
Evolution as the blind engineer: wiring minimization in the brain. |
SLIP |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Arvind Kumar, Sandip Tiwari |
Defect tolerance for nanocomputer architecture. |
SLIP |
2004 |
DBLP DOI BibTeX RDF |
wire length estimation, FPGA, reliability, reconfigurability, defect tolerance, nanoelectronics, Rent's rule, nanocomputing |
17 | Phillip Christie, José Pineda de Gyvez |
Prelayout interconnect yield prediction. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Qinwei Xu, Pinaki Mazumder |
Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie |
Multi-objective optimization of interconnect geometry. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Ashok K. Murugavel, N. Ranganathan |
Petri net modeling of gate and interconnect delays for power estimation. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy 0001 |
On-chip interconnect modeling by wire duplication. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts |
Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. |
IEEE Des. Test Comput. |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, Richard Hersemeule, Jean-Philippe Cousin |
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect. |
MEMOCODE |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Jérôme Lescot, François J. R. Clément |
Interconnect Parasitic Extraction Tool for Radio-Frequency Integrated Circuits. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni |
Effects of Temperature in Deep-Submicron Global Interconnect Optimization. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Srividya Srinivasaraghavan, Wayne P. Burleson |
Interconnect Effort - A Unification of Repeater Insertion and Logical Effort. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Frédéric Pétrot, Pascal Gomez |
Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Terry Tao Ye, Luca Benini, Giovanni De Micheli |
Packetized On-Chip Interconnect Communication Analysis for MPSoC. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
17 | W. J. Bainbridge, William B. Toms, David A. Edwards, Stephen B. Furber |
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes. |
ASYNC |
2003 |
DBLP DOI BibTeX RDF |
|
17 | L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti 0001 |
A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu |
Retiming with Interconnect and Gate Delay. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Magdy A. El-Moursy, Eby G. Friedman |
Inductive interconnect width optimization for low power. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Timo Palenius, Janne Roos |
An efficient reduced-order interconnect macromodel for time-domain simulation. |
ISCAS (4) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Alyssa B. Apsel, Andreas G. Andreou |
A 10 milliwatt 2 Gbps CMOS optical receiver for optoelectronic interconnect. |
ISCAS (1) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Dirk K. de Vries, Paul L. C. Simon |
Calibration of Open Interconnect Yield Models. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Won-Seok Lee, Keun-Ho Lee, Jin-Kyu Park, Tae-Kyung Kim, Young-Kwan Park, Jeong-Taek Kong |
Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Mehdi Baradaran Tahoori, Subhasish Mitra |
Automatic Configuration Generation for FPGA Interconnect Testing. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Dereck A. Fernandes, Ian G. Harris |
Application of Built in Self-Test for Interconnect Testing of FPGAs. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Erik Chmelar |
FPGA Interconnect Delay Fault Testing. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Lee Whetsel |
Adapting JTAG for AC Interconnect Testing. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Jason Helge Anderson, Farid N. Najm |
Switching activity analysis and pre-layout activity prediction for FPGAs. |
SLIP |
2003 |
DBLP DOI BibTeX RDF |
FPGAs, field-programmable gate arrays, low-power design, power, estimation |
17 | Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi |
Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems. |
IEEE Des. Test Comput. |
2002 |
DBLP DOI BibTeX RDF |
|
17 | David Goren, Michael Zelikson, Tiberiu C. Galambos, Rachel Gordin, Betty Livshitz, Alon Amir, Anatoly Sherman, Israel A. Wagner |
An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach . |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao |
Flip-Flop and Repeater Insertion for Early Interconnect Planning. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy 0001 |
On-chip interconnect modeling by wire duplication. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Koichi Nose, Takayasu Sakurai |
Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Louis Scheffer |
Methodologies and Tools for Pipelined On-Chip Interconnect. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo |
An interconnect optimized floorplanning of a scalar product macrocell. |
ISCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Pasi Liljeberg, Imed Ben Dhaou, Juha Plosila, Jouni Isoaho, Hannu Tenhunen |
Interconnect peak current reduction for wavelet array processor using self-timed signaling. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Cliff C. N. Sze, Ting-Chi Wang |
Optimal circuit clustering with variable interconnect delay. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen |
Optimising bandwidth over deep sub-micron interconnect. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Steve Sistare, Christopher J. Jackson |
Ultra-high performance communication with MPI and the Sun fireTM link interconnect. |
SC |
2002 |
DBLP DOI BibTeX RDF |
kernel bypass, remote shared memory, performance evaluation, MPI, interconnects, SAN |
17 | Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian |
Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
FPGA, Test |
17 | Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin |
An Adaptive Interconnect-Length Driven Placer. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Andrey V. Mezhiba, Eby G. Friedman |
Scaling trends of on-chip Power distribution noise. |
SLIP |
2002 |
DBLP DOI BibTeX RDF |
technology scaling, power supply noise, power distribution |
17 | Peter Meuris, Wim Schoenmaker, Wim Magnus |
Strategy for electromagnetic interconnect modeling. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Jason Cong, Cheng-Kok Koh, Patrick H. Madden |
Interconnect layout optimization under higher order RLC model forMCM designs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Amit Singh 0001, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska |
Interconnect pipelining in a throughput-intensive FPGA architecture. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Martin R. Frerichs |
Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling: invited talk. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Dian Zhou, Wei Li, Wei Cai, Nailong Guo |
An efficient balanced truncation realization algorithm for interconnect model order reduction. |
ISCAS (5) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | John Marty Emmert, Jason A. Cheatham |
On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router . |
DFT |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu |
Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. |
ISQED |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Ralph H. J. M. Otten, Giuseppe S. Garcea |
Are wires plannable? |
SLIP |
2001 |
DBLP DOI BibTeX RDF |
|
17 | José Pineda de Gyvez |
Yield modeling and BEOL fundamentals. |
SLIP |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang |
Interconnect thermal modeling for accurate simulation of circuittiming and reliability. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
Testing the Local Interconnect Resources of SRAM-Based FPGA's. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
FPGA, VLSI, test, ATPG |
17 | Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi |
Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models. |
MTDT |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Hung-Jung Chen, Bradley S. Carlson |
Power estimation for a submicron CMOS inverter driving a CRC interconnect load. |
ACM Great Lakes Symposium on VLSI |
2000 |
DBLP DOI BibTeX RDF |
|
17 | H. Levy, W. Scott, Don MacMillen, Jacob White 0001 |
A rank-one update method for efficient processing of interconnect parasitics in timing analysis. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Janet Meiling Wang, Qingjian Yu, Ernest S. Kuh |
Coupled Noise Estimation for Distributed RC Interconnect Model. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
17 | A. Toulouse, David Bernard, Christian Landrault, Pascal Nouet |
Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Jinsong Hou, Zeyi Wang, Xianlong Hong |
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
Parasitic Capacitance, Hierarchical h-Adaptive Computation, VLSI, Boundary Element Method |
17 | Chun-Keung Lo, Philip C. H. Chan |
An Efficient Structural Approach to Board Interconnect Diagnosis. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Wenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi |
A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi |
Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
FPGA, Fault Diagnosis, Fault Detection |
17 | Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi |
Interconnect Diagnosis of Bus-Connected Multi-RAM Systems. |
MTDT |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz |
Interconnect scaling implications for CAD. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Hyunjin Kim, Jongchul Shin, Sungho Kang 0001 |
An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Yuichi Tanji, Mamoru Tanaka |
A new order-reduction method of interconnect networks characterized by sampled data via orthogonal least square algorithm. |
ISCAS (5) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Rex Lowther |
Compact modeling of interconnect and substrate coupling at GHz frequencies. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Zhong-Fang Jin, Jean-Jacques Laurin, Yvon Savaria, Pierre Garon |
A new approach to analyze interconnect delays in RC wire models. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi |
PRIMA: passive reduced-order interconnect macromodeling algorithm. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
Testing the Interconnect of RAM-Based FPGAs. |
IEEE Des. Test Comput. |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Michael Gasteier, Manfred Glesner, Michael Münch |
Generation of Interconnect Topologies for Communication Synthesis. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
bus generation, channel merging, Communications synthesis |
17 | Huibo Hou, Sachin S. Sapatnekar |
Routing tree topology construction to meet interconnect timing constraints. |
ISPD |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Hui Zhang 0008, Jan M. Rabaey |
Low-swing interconnect interface circuits. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr. |
Incorporating interconnect, register, and clock distribution delays into the retiming process. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
17 | José T. de Sousa, Peter Y. K. Cheung |
Improved diagnosis of realistic interconnect shorts. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Jason Cong, David Zhigang Pan, Lei He 0001, Cheng-Kok Koh, Kei-Yong Khoo |
Interconnect design for deep submicron ICs. |
ICCAD |
1997 |
DBLP BibTeX RDF |
required-arrival-time Steiner tree higher-order moment signal delay and integrity |
17 | Haluk Konuk |
Fault simulation of interconnect opens in digital CMOS circuits. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
fault simulation, opens, breaks |
17 | Kangwoo Lee, Woo-Jong Han, Michel Dubois 0001 |
Bottleneck-Free Interconnect and IO Subsystem in SPAX. |
ICPADS |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Qing Zhu, Wayne Wei-Ming Dai |
High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Narain D. Arora, Kartik V. Raol, Reinhard Schumann, Llanda M. Richardson |
Modeling and extraction of interconnect capacitances for multilayer VLSI circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Yogindra Abhyankar, Anil Degwekar, Abhay Karandikar |
Centre for Development of Advanced Computing: DS-Link over Fiber: A High-Speed Interconnect for Cluster Computing. |
IPPS |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Hans T. Heineken, Wojciech Maly |
Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
Standard Cell Designs, Synthesis, Interconnects, Manufacturability, Yield |
17 | Ludmila Cherkasova, Vadim E. Kotov, Tomas Rokicki |
The Impact of Message Scheduling on a Packet Switching Interconnect Fabric. |
HICSS (1) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli |
Automatic generation of analytical models for interconnect capacitances. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel |
Block-oriented programmable design with switching network interconnect. |
IEEE Trans. Very Large Scale Integr. Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage |
Time-domain macromodels for VLSI interconnect analysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Tolga Soyata, Eby G. Friedman |
Retiming with non-zero clock skew, variable register, and interconnect delay. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
17 | C. Bachelu, Martin Lefebvre 0001 |
A study of the use of local interconnect in CMOS leaf cell design. |
IEEE Trans. Very Large Scale Integr. Syst. |
1993 |
DBLP DOI BibTeX RDF |
|