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Publication years (Num. hits)
1960-1974 (15) 1975-1980 (15) 1982-1987 (18) 1988-1990 (21) 1991-1992 (25) 1993 (20) 1994 (19) 1995 (26) 1996 (17) 1997 (20) 1998 (25) 1999 (32) 2000 (33) 2001 (48) 2002 (34) 2003 (55) 2004 (43) 2005 (62) 2006 (65) 2007 (69) 2008 (68) 2009 (32) 2010 (32) 2011 (27) 2012 (24) 2013 (24) 2014 (18) 2015 (18) 2016 (26) 2017 (31) 2018 (39) 2019 (31) 2020 (38) 2021 (42) 2022 (29) 2023 (43) 2024 (7)
Publication types (Num. hits)
article(465) incollection(4) inproceedings(717) phdthesis(5)
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Found 1191 publication records. Showing 1191 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
104Seiji Kajihara, Tsutomu Sasao On the Adders with Minimum Tests. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF ripple carry adder, minimum test set, test generation, stuck-at fault, carry look-ahead adders
92Akhilesh Tyagi A Reduced-Area Scheme for Carry-Select Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders
88Javier Hormigo, Manuel Ortiz, Francisco J. Quiles 0002, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata Efficient Implementation of Carry-Save Adders in FPGAs. Search on Bibsonomy ASAP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
88Mary D. Brown, Yale N. Patt Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files. Search on Bibsonomy HPCA The full citation details ... 2002 DBLP  DOI  BibTeX  RDF redundant binary, limited bypass, pipelined register file, signed digit
88Oscar Gustafsson, Henrik Ohlsson, Lars Wanhammar Minimum-adder integer multipliers using carry-save adders. Search on Bibsonomy ISCAS (2) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
79Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin Power-delay characteristics of CMOS adders. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
77Stanislaw J. Piestrak Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF residue generators, multioperand modular adders, arithmetic error detecting codes, binary-to-residue number system, residue generator, digital arithmetic, adders, Chinese remainder theorem, residue number system, arithmetic codes, residue arithmetic, carry-save adders
77Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF delay optimisation, block carry-lookahead adders, multidimensional dynamic programming, worst-case carry propagation delays, minimum latency, fanin, dynamic programming, digital arithmetic, adders, gate delays, carry logic, fanout, critical path delay, carry-skip adders
76Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian Easily Testable Cellular Carry Lookahead Adders. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model
73Dilip P. Vasudevan, Parag K. Lala A Technique for Modular Design of Self-Checking Carry-Select Adder. Search on Bibsonomy DFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
71Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos High-Speed Parallel-Prefix Modulo 2n-1 Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Modulo $2^n-1$ adders, VLSI design, parallel-prefix adders, carry look-ahead adders
71Hans Lindkvist, Per Andersson Dynamic CMOS circuit techniques for delay and power reduction in parallel adders . Search on Bibsonomy ARVLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF dynamic CMOS circuit techniques, delay reduction, parallel adders, high-speed adders, Manchester-carry chains, clock/data precharged dynamic logic blocks, carry calculation trees, parallel processing, VLSI, delays, logic design, digital arithmetic, power consumption, adders, CMOS logic circuits, power reduction, carry logic
64Javier D. Bruguera, Tomás Lang Multilevel Reverse-Carry Addition: Single and Dual Adders. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF prefix adders, dual adders, most-significant-carry detection, computer arithmetic, VLSI design
64W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
63Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait Area-time optimal adder with relative placement generator. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
62Vitit Kantabutra Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF accelerated two-level carry-skip adders, bit positions, bimodal, CMOS VLSI, 12.6 sec, VLSI, delays, adders, CMOS integrated circuits, unimodal, 2 micron
62Luigi Dadda, Vincenzo Piuri Pipelined Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF high-speed adders, high-throughput adders, skewed arithmetic, Adders, pipelined computation
62Hung Chi Lai, Saburo Muroga Logic Networks of Carry-Save Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1982 DBLP  DOI  BibTeX  RDF parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders
62Hung Chi Lai, Saburo Muroga Minimum Parallel Binary Adders with NOR (NAND) Gates. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1979 DBLP  DOI  BibTeX  RDF NOR gates, carry-ripple adders, minimum adders, NAND gates, logic design, Adders
61Jeong-Gun Lee, Jeong-A Lee, Byeong-Seok Lee, Milos D. Ercegovac A Design Method for Heterogeneous Adders. Search on Bibsonomy ICESS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
61Sumeer Goel, Ashok Kumar 0001, Magdy A. Bayoumi Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
61Johannes Grad, James E. Stine Low power binary addition using carry increment adders. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
61Keshab K. Parhi Low-energy CSMT carry generators and binary adders. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
58Giorgos Dimitrakopoulos, Dimitris Nikolos High-Speed Parallel-Prefix VLSI Ling Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF parallel-prefix carry computation, computer arithmetic, VLSI design, Adders
58Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. Search on Bibsonomy ASYNC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF completion detection, Brent-Kung, Carry-Bypass, asynchronous, adders, hazards, high-performance design
54R. Mahesh 0001, A. Prasad Vinod 0001 A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
54Ajay Kumar Verma, Paolo Ienne Automatic synthesis of compressor trees: reevaluating large counters. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
54Douglas L. Maskell, Jussipekka Leiwo, Jagdish Chandra Patra The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
54Johannes Grad, James E. Stine New algorithms for carry propagation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF carry propagate addition, conditional sum adder, hybrid adder, ling adder, pseudo-complements, reed adder, domino logic, carry-skip adder
52Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001 A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
52Ilya Obridko, Ran Ginosar Minimal Energy Asynchronous Dynamic Adders. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Giorgos Dimitrakopoulos, Pavlos Kolovos, P. Kalogerakis, Dimitris Nikolos Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. Search on Bibsonomy PATMOS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
52João Leonardo Fragoso, Gilles Sicard, Marc Renaudin Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. Search on Bibsonomy PATMOS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
52João Leonardo Fragoso, Gilles Sicard, Marc Renaudin Automatic Generation of 1-of-M QDI Asynchronous Adders. Search on Bibsonomy SBCCI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
52Radomir S. Stankovic, Jaakko Astola Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision Diagrams. Search on Bibsonomy ISMVL The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Decision  diagrams, Logic design, Switching functions, Spectral transforms
52Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
52Uming Ko, T. Balsara, Wai Lee Low-power design techniques for high-performance CMOS adders. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
49Giacomo Paci, Paul Marchal, Luca Benini Exploration of Low Power Adders for a SIMD Data Path. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF SIMD data path, low power adders
49Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos Modulo 2n±1 Adder Design Using Select-Prefix Blocks. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF modulo 2n± 1 adders, select-prefix adders, computer arithmetic, VLSI architectures
49Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos Diminished-One Modulo 2n+1 Adder Design. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Modulo $big. 2^{rm n}+1bigr.$ addition, carry look-ahead addition, diminished-one number representation, VLSI adders, parallel-prefix adders
46Chien-Hung Lin, Shu-Chung Yi, Jin-Jia Chen Low Power Adders Design for Portable Video Terminal. Search on Bibsonomy IIH-MSP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF low power adders, portable video terminal, Full adders
46Vitit Kantabutra Designing Optimum One-Level Carry-Skip Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF one-level, 64 bit, 6.23 ns, logic design, digital simulation, adders, SPICE simulation, carry-skip adders, 1 micron
46Branislava Perunicic, Salim Lakhani, Veljko M. Milutinovic Stochastic Modeling and Analysis of Propagation Delays in GaAs Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF GaAs adders, stochastic changes, III-V semiconductors, probability, combinational circuits, stochastic modelling, stochastic processes, adders, combinatorial circuits, propagation delays, gate delays, GaAs, gallium arsenide, probability distribution function
46Bernd Becker 0001 Efficient Testing of Optimal Time Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF optimal time adders, conditional sum adder, VLSI, logic testing, adders, integrated logic circuits, VLSI chip, carry look-ahead adder
46Riyaz A. Patel, Mohammed Benaissa, Said Boussakta Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Modulo 2n-1 adders, One's complement adders, computer arithmetic, VLSI design, parallel-prefix adders
45Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi 0001 Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms. Search on Bibsonomy ISMVL The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
43Haridimos T. Vergos, Dimitris Bakalis On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Erdal Oruklu, Vibhuti B. Dave, Jafar Saniie Performance analysis of flagged prefix adders with logical effort. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Álvaro Vázquez, Elisardo Antelo New insights on Ling adders. Search on Bibsonomy ASAP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy 0001 Fine-Grained Redundancy in Adders. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos Fast Parallel-Prefix Modulo 2^n+1 Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou Deterministic BIST for RNS Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF deterministic and pseudorandom tests, formal test sets, Built-In Self-Test, Residue Number System
43Jean-Luc Beuchat Some Modular Adders and Multipliers for Field Programmable Gate Arrays. Search on Bibsonomy IPDPS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF modulo m addition, modulo m multiplication, FPGA, Computer arithmetic
43Bernd Becker 0001, Reiner Kolla On the Construction of Optimal Time Adders (Extended Abstract). Search on Bibsonomy STACS The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
40Jianhua Liu, Yi Zhu 0002, Haikun Zhu, Chung-Kuan Cheng, John Lillis Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF optimum prefix adders, static power consumptions, dynamic power consumptions, high-level synthesis, integer linear programming, buffer insertion, gate sizing, power models, ASIC designs, parallel prefix adder, binary adder
40Peter Kornerup Reviewing 4-to-2 Adders for Multi-Operand Addition. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF redundant adders, digit sets, digit encodings, multiplier trees
40Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald Self-Timed Carry-Lookahead Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF delay-insenstive circuits, tree iterative circuits, CMOS, Self-timed circuits, carry-lookahead adders
40José Fernández Ramos, Alfonso Gago Bohórquez Two Operand Binary Adders with Threshold Logic. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1999 DBLP  DOI  BibTeX  RDF neural networks, logic design, computer arithmetic, Threshold logic, threshold gate, binary adders
40Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer Testing Schemes for FIR Filter Structures. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Complex multipliers, sign-extended adders, trees of adders, design for testability, FIR filters, pseudoexhaustive testing, state coverage, cell fault model
40Priyadarsan Patra, Donald S. Fussell Fully asynchronous, robust, high-throughput arithmetic structures. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers
36Swaroop Ghosh, Kaushik Roy 0001 Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
36Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie Design and Synthesis of a Three Input Flagged Prefix Adder. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36A. Prasad Vinod 0001, Edmund Ming-Kit Lai Low power and high-speed implementation of fir filters for software defined radio receivers. Search on Bibsonomy IEEE Trans. Wirel. Commun. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu The new architecture of radix-4 Chinese abacus adder. Search on Bibsonomy ISMVL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
36A. Prasad Vinod 0001, Edmund Ming-Kit Lai On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal On the Advantages of Serial Architectures for Low-Power Reliable Computations. Search on Bibsonomy ASAP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Jeff Rebacz, Erdal Oruklu, Jafar Saniie High performance signed-digit decimal adders. Search on Bibsonomy EIT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Fatemeh Eslami, Amirali Baniasadi, Mostafa Farahani Application Specific Transistor Sizing for Low Power Full Adders. Search on Bibsonomy ASAP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
34Wenjing Rao, Alex Orailoglu Towards fault tolerant parallel prefix adders in nanoelectronic systems. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Hirokatsu Shirahama, Takahiro Hanyu Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. Search on Bibsonomy ISMVL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Carry pre-addition, Differential-pair circuitry, Voltage-mode circuit, Transfer-gate circuitry, Current-mode circuit
34Zine Abid, Wei Wang 0003 New designs of Redundant-Binary full Adders and its applications. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
34Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition. Search on Bibsonomy DSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. Search on Bibsonomy ICESS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Sheng Sun, Carl Sechen Post-layout comparison of high performance 64b static adders in energy-delay space. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34A. Neslin Ismailoglu, Murat Askar Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy 0001 Comparison of high-performance VLSI adders in the energy-delay space. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Rumi Zhang, Wei Wang 0003, Konrad Walus, Graham A. Jullien Performance comparison of quantum-dot cellular automata adders. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Jin-Fu Li 0001, Jiunn-Der Yu, Yu-Jen Huang A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability. Search on Bibsonomy ISCAS (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis Test Generation Methodology for High-Speed Floating Point Adders. Search on Bibsonomy IOLTS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata On-line Multioperand Addition Based on On-line Full Adders. Search on Bibsonomy ASAP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
34Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. Search on Bibsonomy ISVLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
34Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris Fast adders in modern FPGAs. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
34Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy 0001 Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
34Simon Knowles A Family of Adders. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
34Viv A. Bartlett, Andrew G. Dempster Using carry-save adders in low-power multiplier blocks. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
34Henrik Eriksson, Per Larsson-Edefors, William P. Marnane A regular parallel multiplier which utilizes multiple carry-propagate adders. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
34Athanasios Kakarountas, Kyriakos Papadomanolakis, Vasileios Kokkinos, Constantinos E. Goutis Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance. Search on Bibsonomy PATMOS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
34Simon Knowles A Family of Adders. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
34Sae Hwan Kim, Shiu-Kai Chin Formal Verification of Tree-Structured Carry-Lookahead Adders. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
34Shanzhen Xing, William W. H. Yu FPGA Adders: Performance Evaluation and Optimal Design. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
34Yirng-An Chen, Randal E. Bryant Verification of Floating-Point Adders. Search on Bibsonomy CAV The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
33Levent Aksoy, Ece Olcay Günes Area optimization algorithms in high-speed digital FIR filter synthesis. Search on Bibsonomy SBCCI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF high-speed filter design, multiple constant multiplications, subexpression sharing, area optimization, carry-save adders
33Luigi Dadda Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF multioperand adders, Computer arithmetic, hardware design, decimal arithmetic
33Ann Majchrzak, Christian Wagner 0001, Dave Yates Corporate wiki users: results of a survey. Search on Bibsonomy Int. Sym. Wikis The full citation details ... 2006 DBLP  DOI  BibTeX  RDF corporate wiki, knowledge contribution, knowledge restructuring, survey, adders, knowledge reuse, synthesizers
32Chandan Kumar Jha 0001, Ankita Nandi, Joycee Mekie Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
32Vishesh Mishra, Neelofar Hassan, Akshay Mehta, Urbi Chatterjee DARK-Adders: Digital Hardware Trojan Attack on Block-based Approximate Adders. Search on Bibsonomy VLSID The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
32Daniel Etiemble Two New CNTFET Quaternary Full Adders for Carry-Propagate Adders. Search on Bibsonomy CoRR The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
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