Search results for "CLBs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
58	Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin	Combining technology mapping and placement for delay-minimization in FPGA designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
44	Jenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren	Quantitative Analysis of In-Field Defects in Image Sensor Arrays.	DFT	2007	DBLP DOI BibTeX RDF
44	Mohammed Y. Niamat, Surya S. Hejeebu, Mansoor Alam	A BIST Approach for Testing FPGAs Using JBITS.	FCCM	2005	DBLP DOI BibTeX RDF
44	Seok-Bum Ko	Area Minimization of Exclusive-OR Intensive Circuits in FPGAs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	FPGA, XOR, ESOP
44	Frank Honoré, Benton H. Calhoun, Anantha P. Chandrakasan	Power-aware architectures and circuits for FPGA-based signal processing.	FPGA	2003	DBLP DOI BibTeX RDF
44	Seok-Bum Ko, Jien-Chung Lo	Efficient Decomposition Techniques for FPGAs.	HiPC	2002	DBLP DOI BibTeX RDF
44	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules.	DFT	2001	DBLP DOI BibTeX RDF	configurable logic blocks, fault diagnosis, BIST, FPGA testing
44	Chi-Chou Kao, Yen-Tai Lai	A routability and performance driven technology mapping algorithm for LUT based FPGA designs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
44	Shyue-Kung Lu, Cheng-Wen Wu	A novel approach to testing LUT-based FPGAs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
44	Madhukar R. Korupolu, K. K. Lee, D. F. Wong 0001	Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs.	DAC	1998	DBLP DOI BibTeX RDF
44	Martine D. F. Schlag, Pak K. Chan, Jackson Kong	Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
34	Mengfan Xu, Yuejun Zhang, Huihong Zhang, Liang Wen, Tengfei Yuan, Pengjun Wang, Zhiyi Li	Full-custom Design of Improved Carry Adder Circuit for CLBs.	ASICON	2023	DBLP DOI BibTeX RDF
34	Sarang Kazeminia, Maryam Ghafoorzadeh, Faeze Noruzpur	An extendable global clock high-speed binary counter compatible to the FPGA CLBs.	MIXDES	2017	DBLP DOI BibTeX RDF
34	Anjela Yu. Matrosova, Sergey Ostanin, Valentina Andreeva	Patching circuit design based on reserved CLBs.	AQTR	2016	DBLP DOI BibTeX RDF
34	Arwa Ben Dhia, Lirida A. B. Naviner, Philippe Matherat	Comparison of fault-tolerant fabless CLBs in SRAM-based FPGAs.	LATW	2013	DBLP DOI BibTeX RDF
34	Yong Fu, Chi Wang, Liguang Chen, Jinmei Lai	A novel full coverage test method for CLBs in FPGA (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
34	Arwa Ben Dhia, Lirida Alves de Barros Naviner, Philippe Matherat	A new fault-tolerant architecture for CLBs in SRAM-based FPGAs.	ICECS	2012	DBLP DOI BibTeX RDF
34	Anjela Yu. Matrosova, Ekaterina Loukovnikova, Sergei Ostanin, Alexandra Zinchuk, Ekaterina Nikolaeva	Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs.	DFT	2007	DBLP DOI BibTeX RDF
34	Nadia Nedjah, Luiza de Macedo Mourelle	How Many CLBs Does Your Circuit Need to be Implemented?.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
34	G. Bozikian, J. William Atwood	CICS LSR Buffer Simulator (CLBS).	Int. CMG Conference	1988	DBLP BibTeX RDF
33	Khalil Dayo, Abdul Qadeer Khan Rajput, Bhawani Shankar Chowdhry, Narinder P. Chowdhry	Impact of Cluster Size on Efficient LUT-FPGA Architecture for Best Area and Delay Trade-Off.	IMTIC	2008	DBLP DOI BibTeX RDF	CLBs, BLE, FPGA, Lookup table
33	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	LAP: a logic activity packing methodology for leakage power-tolerant FPGAs.	ISLPED	2005	DBLP DOI BibTeX RDF	activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), sleep transistor (ST), sub-threshold leakage power, FPGA, packing
29	Shantanu Dutt, Li Li	Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	masking probability, parity groups, parity randomization, trust checking, trust-based design, FPGAs, Error-correcting codes
29	Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal	A high-level clustering algorithm targeting dual Vdd FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	clustering, field programmable gate arrays, partitioning, placement, voltage scaling, Dynamic power
29	Jason Meyer, Fatih Kocan	Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
29	Guijun Gao, Youren Wang, Jiang Cui, Rui Yao	Research on Multi-objective On-Line Evolution Technology of Digital Circuit Based on FPGA Model.	ICES	2007	DBLP DOI BibTeX RDF	On-line Evolution, Multi-objective Evolutionary Method, FPGA Model, Digital Circuit, Evolvable Hardware
29	Marvin Tom, David Leong, Guy G. Lemieux	Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs.	ICCAD	2006	DBLP DOI BibTeX RDF	channel width constraints, clustering, field-programmable gate arrays (FPGA), packing
29	Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee	Accurate Area and Delay Estimators for FPGAs.	DATE	2002	DBLP DOI BibTeX RDF
29	Khaled Benkrid, Danny Crookes, Abdsamad Benkrid	Design and implementation of a novel algorithm for general purpose median filtering on FPGAs.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
29	Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley	Reconfigurable Array Media Processor (RAMP).	FCCM	2000	DBLP DOI BibTeX RDF
29	K. K. Lee, D. F. Wong 0001	An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs.	ICCD	1999	DBLP DOI BibTeX RDF
29	Abderrahim Doumar, Satoshi Kaneko, Hideo Ito	Defect and Fault Tolerance FPGAs by Shifting the Configuration Data.	DFT	1999	DBLP DOI BibTeX RDF
29	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF
29	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	RAM-Based FPGA's: A Test Approach for the Configurable Logic.	DATE	1998	DBLP DOI BibTeX RDF
29	Mehrdad Nourani, Christos A. Papachristou	A Bypass Scheme for Core-Based System Fault Testing.	DATE	1998	DBLP DOI BibTeX RDF
29	Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita	Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
29	Wei-Kang Huang, M. Y. Zhang, Fred J. Meyer, Fabrizio Lombardi	A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	programmable system, diagnosis, FPGA testing, XOR
15	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris Jr.	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
15	Fang Wu, Huowen Zhang, Lei Duan, Jinmei Lai, Yuan Wang, Jiarong Tong	A delay-optimized universal FPGA routing architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
15	Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman	Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
15	Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera	A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
15	Stephen Bijansky, Adnan Aziz	TuneFPGA: post-silicon tuning of dual-Vdd FPGAs.	DAC	2008	DBLP DOI BibTeX RDF	FPGA, delay, process variation, yield, tuning
15	Pritha Banerjee 0001, Susmita Sur-Kolay, Arijit Bishnu	Floorplanning in Modern FPGAs.	VLSI Design	2007	DBLP DOI BibTeX RDF
15	Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis	Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
15	Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali	Testing embedded RAM modules in SRAM-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
15	Amilcar do Carmo Lucas, Sven Heithecker, Peter Rüffer, Rolf Ernst, Holger Rückert, Gerhard Wischermann, Karin Gebel, Reinhard Fach, Wolfgang Huther, Stefan Eichner, Gunter Scheller	A reconfigurable HW/SW platform for computation intensive high-resolution real-time digital film applications.	DATE	2006	DBLP DOI BibTeX RDF	digital film, stream-based architecture, weak-programming, FPGA, motion-estimation, reconfigurable
15	Yi Wang 0016, Jussipekka Leiwo, Thambipillai Srikanthan, Yu Yu	FPGA based DPA-resistant Unified Architecture for Signcryption.	ITNG	2006	DBLP DOI BibTeX RDF
15	Somsubhra Mondal, Rajarshi Mukherjee, Seda Ogrenci Memik	Fine-grain thermal profiling and sensor insertion for FPGAs.	ISCAS	2006	DBLP DOI BibTeX RDF
15	P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis	A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
15	Yi Wang 0016, Douglas L. Maskell, Jussipekka Leiwo, Thambipillai Srikanthan	Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems.	APCCAS	2006	DBLP DOI BibTeX RDF
15	Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001	A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
15	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
15	Kuan Zhou, John F. McDonald 0001	Multi-GHz SiGe design methodologies for reconfigurable computing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	CLB, virtex, FPGA, SiGe
15	Marvin Tom, Guy G. Lemieux	Logic block clustering of large designs for channel-width constrained FPGAs.	DAC	2005	DBLP DOI BibTeX RDF	channel width constraints, clustering, field-programmable gate arrays (FPGA), packing
15	Mahmoud Méribout, Masato Motomura	Efficient metrics and high-level synthesis for dynamically reconfigurable logic.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
15	Seok-Bum Ko, Jien-Chung Lo	Efficient Realization of Parity Prediction Functions in FPGAs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	parity prediciton functions, Davio''s expansion, AND/XOR expressions, FPGA, technology mapping
15	Paul Kohlbrenner, Kris Gaj	An embedded true random number generator for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	TRNG, FPGA, random numbers, RNG, cryptographic
15	Lei Cheng 0001, Martin D. F. Wong	Floorplan design for multi-million gate FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
15	Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald 0001, Russell P. Kraft, Bryan S. Goda	A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.	FPGA	2003	DBLP DOI BibTeX RDF
15	Shyamnath Harinath, Ron Sass	Reconfigurable Mapping Functions for Online Architectures.	IPDPS	2003	DBLP DOI BibTeX RDF
15	Benton H. Calhoun, Frank Honoré, Anantha P. Chandrakasan	Design methodology for fine-grained leakage control in MTCMOS.	ISLPED	2003	DBLP DOI BibTeX RDF	fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS
15	J. M. Pierre Langlois, Dhamin Al-Khalili, Robert J. Inkol	Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	quadrature demodulation, digital down conversion, polyphase filtering, field programmable gate arrays, digital filtering
15	Domingo Benitez	Performance of Remote FPGA-Based Coprocessors for Image-Processing Applications.	DSD	2002	DBLP DOI BibTeX RDF
15	Jean-Luc Beuchat, Arnaud Tisserand	Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices.	FPL	2002	DBLP DOI BibTeX RDF
15	Akira Miyashita, Toshihito Fujiwara, Tsutomu Maruyama	A Placement/Routing Approach for FPGA Accelerators.	FPL	2002	DBLP DOI BibTeX RDF
15	Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José Manuel Martins Ferreira	On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
15	Salvatore Pontarelli, Gian Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano	A self-checking cell logic block for fault tolerant FPGAs.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
15	Dewi Utami, Hadi Suwastio, Bambang Sumadjudin	FPGA Implementation of Digital Chaotic Cryptography.	EurAsia-ICT	2002	DBLP DOI BibTeX RDF	digital filter overflow, FPGA, cryptography, Chaos, fixed point
15	Jason Cong, Yean-Yow Hwang	Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
15	Greg Snider, Barry Shackleford, Richard J. Carter	Attacking the semantic gap between application programming languages and configurable hardware.	FPGA	2001	DBLP DOI BibTeX RDF
15	Wei-Je Huang, Edward J. McCluskey	A memory coherence technique for online transient error recovery of FPGA configurations.	FPGA	2001	DBLP DOI BibTeX RDF	fault tolerance, FPGA, error recovery, memory coherence
15	Reiner W. Hartenstein	Reconfigurable Computing: A New Business Model and its Impact on SoC Design.	DSD	2001	DBLP DOI BibTeX RDF
15	Srihari Cadambi, Seth Copen Goldstein	Static Profile-Driven Compilation for FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
15	Jayabrata Ghosh-Dastidar, Nur A. Touba	Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability.	DFT	2001	DBLP DOI BibTeX RDF
15	Artur Chojnacki, Lech Józwiak	High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures.	ISQED	2001	DBLP DOI BibTeX RDF
15	Tim Courtney, Richard H. Turner, Roger F. Woods	Multiplexer Based Reconfiguration for Virtex Multipliers.	FPL	2000	DBLP DOI BibTeX RDF
15	Jian Qiao, Makoto Ikeda, Kunihiro Asada	Optimum Functional Decomposition for LUT-Based FPGA Synthesis.	FPL	2000	DBLP DOI BibTeX RDF
15	Parag K. Lala, Alvernon Walker	An On-Line Reconfigurable FPGA Architecture.	DFT	2000	DBLP DOI BibTeX RDF
15	Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang	An Analytical Delay Model for SRAM-Based FPGA Interconnections.	ASP-DAC	1999	DBLP DOI BibTeX RDF
15	Abderrahim Doumar, Hideo Ito	Testing the Logic Cells and Interconnect Resources for FPGAs.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
15	W. Quddus, Abhijit Jas, Nur A. Touba	Configuration self-test in FPGA-based reconfigurable systems.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
15	Abderrahim Doumar, Hideo Ito	An Automatic Testing and Diagnosis for FPGAs.	PRDC	1999	DBLP DOI BibTeX RDF
15	Jian Xu, Paifa Si, Wei-Kang Huang, Fabrizio Lombardi	A Novel Fault Tolerant Approach for SRAM-Based FPGAs.	PRDC	1999	DBLP DOI BibTeX RDF	FPGA, fault-tolerant routing, fault-tolerant architecture
15	Debaleena Das, Nur A. Touba	A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems.	VLSI Design	1999	DBLP DOI BibTeX RDF
15	A. R. Naseer, M. Balakrishnan, Anshul Kumar	Direct mapping of RTL structures onto LUT-based FPGA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
15	Akihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda	New FPGA Architecture for Bit-Serial Pipeline Datapath.	FCCM	1998	DBLP DOI BibTeX RDF
15	Philip Heng Wai Leong, P. K. Tsang, T. K. Lee	A FPGA Based Forth Microprocessor.	FCCM	1998	DBLP DOI BibTeX RDF
15	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ.	ITC	1998	DBLP DOI BibTeX RDF	IDDQ Tes t, Configurable Logic Blocks, FPGA, Testing, Bridging Fault, Programming Phase
15	Balakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi	In-Place Power Optimization for LUT-Based FPGAs.	DAC	1998	DBLP DOI BibTeX RDF
15	Timothy J. Callahan, John Wawrzynek	Datapath-oriented FPGA mapping and placement for configurable computing.	FCCM	1997	DBLP DOI BibTeX RDF
15	Wei Liang Huang, Fred J. Meyer, Fabrizio Lombardi	Multiple fault detection in logic resources of FPGAs.	DFT	1997	DBLP DOI BibTeX RDF	logic resources, AND tree, OR tree, CLB test generation, field programmable gate arrays, fault model, configurability, testability, programmability, multiple fault detection, SRAM-based FPGA
15	Madhavi Vootukuru, Ranga Vemuri, Nand Kumar	Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs.	VLSI Design	1997	DBLP DOI BibTeX RDF
15	Vassilliy Tchoumatchenko, Tania Vassileva, P. Gurov	An FPGA-Based Square-Root Co-Processor.	EUROMICRO	1996	DBLP DOI BibTeX RDF
15	Les Mintzer	FIR filters with field-programmable gate arrays.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF