Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
62 | Ludovico de Souza, John D. Bunton, Duncan Campbell-Wilson, Roger J. Cappallo, Barton B. Kincaid |
A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 62-67, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
54 | Jürgen Becker 0001, Michael Hübner 0001, Michael Ullmann |
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 283-288, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Virtex FPGA, runtime reconfiguration, power consumption |
54 | Anup Kumar Raghavan, Peter Sutton |
JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
JBits, FPGA design flow, Partial Bitstream, Xilinx Virtex, Partial Reconfiguration |
54 | Michael Hübner 0001, Lars Braun, Jürgen Becker 0001, Christopher Claus, Walter Stechele |
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 41-46, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
54 | Parimal Patel |
Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 16, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
54 | Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo |
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 77-83, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
46 | Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly |
Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | S. Sukhsawas, Khaled Benkrid |
A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 229-232, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
46 | Edson L. Horta, John W. Lockwood |
Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 975-979, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
46 | Abdsamad Benkrid, Khaled Benkrid, Danny Crookes |
Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 553-564, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Abdsamad Benkrid, Khaled Benkrid, Danny Crookes |
A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 8-11 April 2003, Napa, CA, USA, Proceedings, pp. 273-275, 2003, IEEE Computer Society, 0-7695-1979-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
46 | Jerzy Kasperek |
Real Time Morphological Image Contrast Enhancement in Virtex FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 430-440, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
42 | Muzaffar Rao, Thomas Newe, Ian Andrew Grout, Avijit Mathur |
High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 25(7), pp. 1650069:1-1650069:13, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
42 | Liuba Slasten, Alexey Dordopulo, Igor Kaliaev, Ilya I. Levin |
Reconfigurable Computer Systems Based on Virtex-6 and Virtex-7 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDeS ![In: 12th IFAC Conference on Programmable Devices and Embedded Systems, PDeS 2013, Ostrava, Czech Republic, September 25-27, 2013., pp. 210-214, 2013, International Federation of Automatic Control, 978-3-902823-53-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
42 | Amir Moradi 0001, Markus Kasper, Christof Paar |
Black-Box Side-Channel Attacks Highlight the Importance of Countermeasures - An Analysis of the Xilinx Virtex-4 and Virtex-5 Bitstream Encryption Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2012 - The Cryptographers' Track at the RSA Conference 2012, San Francisco, CA, USA, February 27 - March 2, 2012. Proceedings, pp. 1-18, 2012, Springer, 978-3-642-27953-9. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
42 | Christian Schuck, Bastian Haetzer, Jürgen Becker 0001 |
Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Reconfigurable Comput. ![In: Int. J. Reconfigurable Comput. 2011, pp. 671546:1-671546:12, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Amir Moradi 0001, Markus Kasper, Christof Paar |
On the Portability of Side-Channel Attacks - An Analysis of the Xilinx Virtex 4 and Virtex 5 Bitstream Encryption Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2011, pp. 391, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
42 | Christian Schuck, Bastian Haetzer, Jürgen Becker 0001 |
Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/ Virtex II-Pro FPGAs: A Case Study of Distributed Power Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, ReCoSoC 2010, Karlsruhe, Germany, May 17-19, 2010, pp. 45-50, 2010, KIT Scientific Publishing, 978-3-86644-515-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
42 | Bradley F. Dutton, Charles E. Stroud |
Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CATA ![In: Proceedings of the ISCA 24th International Conference on Computers and Their Applications, CATA 2009, April 8-10, 2009, Holiday Inn Downtown-Superdome, New Orleans, Louisiana, USA, pp. 57-62, 2009, ISCA, 978-1-880843-70-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
42 | Bradley F. Dutton, Charles E. Stroud |
Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESA ![In: Proceedings of the 2009 International Conference on Embedded Systems & Applications, ESA 2009, July 13-16, 2009, Las Vegas Nevada, USA, pp. 149-155, 2009, CSREA Press, 1-60132-102-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
41 | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan |
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1200-1203, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel |
Power estimation approach for SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 195-202, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Qiang Wang, Subodh Gupta, Jason Helge Anderson |
Clock power reduction for virtex-5 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 13-22, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking |
37 | Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal |
Architecture-specific packing for virtex-5 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 5-13, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing |
37 | Rashad S. Oreifej, Rawad N. Al-Haddad, Heng Tan, Ronald F. DeMara |
Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 299-304, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Christopher Claus, Florian Helmut Müller, Johannes Zeppenfeld, Walter Stechele |
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-7, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Abdsamad Benkrid, Khaled Benkrid, Danny Crookes |
Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 222-225, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMara |
Evolutionary Fault Recovery in a Virtex FPGA Using a Representation that Incorporates Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 172, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMara |
A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 5th International Conference, ICES 2003, Trondheim, Norway, March 17-20, 2003, Proceedings, pp. 47-56, 2003, Springer, 3-540-00730-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Li Shang, Alireza Kaviani, Kusuma Bathala |
Dynamic power consumption in Virtex[tm]-II FPGA family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 157-164, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Jean-Luc Beuchat, Arnaud Tisserand |
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 513-522, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Gordon J. Brebner |
Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 22-24 April 2002, Napa, CA, USA, Proceedings, pp. 35-44, 2002, IEEE Computer Society, 0-7695-1801-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Felix Albu, Jiri Kadlec, Christopher I. Softley, Rudolf Matousek, Antonin Hermanek, Nick Coleman, Anthony D. Fagan |
Implementation of (Normalised) RLS Lattice on Virtex. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 91-100, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Yoshiki Yamaguchi, Akira Miyashita, Tsutomu Maruyama, Tsutomu Hoshino |
A Co-processor System with a Virtex FPGA for Evolutionary Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 240-249, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Cesar Ortega-Sanchez, Andrew M. Tyrrell |
A Hardware Implementation of an Embryonic Architecture Using Virtex FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, Third International Conference, ICES 2000, Edinburgh, Scotland, UK, April 17-19, 2000, Proceedings, pp. 155-164, 2000, Springer, 3-540-67338-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Cameron Patterson |
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 113-121, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Gordon Hollingworth, Steve Smith, Andrew M. Tyrrell |
Safe Intrinsic Evolution of Virtex Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 2nd NASA / DoD Workshop on Evolvable Hardware (EH 2000), 13-15 July 2000, Palo Alto, CA, USA, pp. 195-204, 2000, IEEE Computer Society, 0-7695-0762-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Roman C. Kordasiewicz, Shahram Shirani |
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 47(3), pp. 189-199, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, Quantization, hardware implementations, MPEG4 |
33 | Roman C. Kordasiewicz, Shahram Shirani |
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 47(2), pp. 93-102, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, quantization, hardware implementations, MPEG4 |
33 | Kuan Zhou, John F. McDonald 0001 |
Multi-GHz SiGe design methodologies for reconfigurable computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 207-212, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CLB, virtex, FPGA, SiGe |
33 | Tomasz S. Czajkowski, Jonathan Rose |
A synthesis oriented omniscient manual editor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 89-98, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
virtex-e, synthesis, manual |
33 | Michael Hübner 0001, Tobias Becker, Jürgen Becker 0001 |
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 28-32, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
virtex, dynamic partial reconfiguration |
33 | Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich |
Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Virtex, Compression, Decompression |
33 | Jiri Novotný, Otto Fucík, David Antos |
Project of IPv6 Router with FPGA Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 964-967, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Liberouter, Virtex II, FPGA, IPv6, router |
33 | Andreas Koch |
A Comprehensive Prototyping-Platform for Hardware-Software Codesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), Paris, France, June 21-23, 2000, pp. 78-, 2000, IEEE Computer Society, 0-7695-0668-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
hybrid processor, RTEMS, Virtex, FPGA, prototyping, codesign, SPARC, Xilinx |
33 | Neil Steiner, Peter M. Athanas |
An Alternate Wire Database for Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 336-337, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Michalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou |
Implementation of a genetic algorithm on a virtex-ii pro FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 287, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multiplier blocks, genetic algorithm, fpga, fitness functions |
29 | Radu Andrei Stefan, Sorin Dan Cotofana |
Bitstream compression techniques for Virtex 4 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 323-328, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Andreas Ehliar, Per Karlström, Dake Liu |
A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 599-602, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Mamoun F. Al-Mistarihi |
Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 531-534, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Philippe Bulens, François-Xavier Standaert, Jean-Jacques Quisquater, Pascal Pellegrin, Gaël Rouvroy |
Implementation of the AES-128 on Virtex-5 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFRICACRYPT ![In: Progress in Cryptology - AFRICACRYPT 2008, First International Conference on Cryptology in Africa, Casablanca, Morocco, June 11-14, 2008. Proceedings, pp. 16-26, 2008, Springer, 978-3-540-68159-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Stefan Raaijmakers, Stephan Wong |
Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 679-683, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Irwin O. Kennedy |
Implementation of Low Frequency Finite State Machines Using the VIRTEX SRL16 Primitive. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 675-678, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Bas Breijer, Filipa Duarte, Stephan Wong |
An OCM based shared Memory controller for Virtex 4. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 692-696, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Antonio Plaza |
Towards Real-Time Compression of Hyperspectral Images Using Virtex-II FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2007, Parallel Processing, 13th International Euro-Par Conference, Rennes, France, August 28-31, 2007, Proceedings, pp. 248-257, 2007, Springer, 978-3-540-74465-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga |
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 463-470, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Filipa Duarte, Stephan Wong |
Profiling Bluetooth and Linux on the Xilinx Virtex II Pro. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 229-235, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Michael Hübner 0001, Christian Schuck, Jürgen Becker 0001 |
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Carsten Bieser, Klaus D. Müller-Glaser |
Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 14-16 June 2006, Chania, Crete, Greece, pp. 193-199, 2006, IEEE Computer Society, 0-7695-2580-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Heiko Kalte, Mario Porrmann |
REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 403-412, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
bitstream manipulation, task relocation, FPGA, reconfigurable computing |
29 | Melanie Po-Leen Ooi |
Hardware Implementation for Face Detection on Xilinx Virtex-II FPGA using the Reversible Component Transformation Colour Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 41-46, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Peter J. Green, Desmond P. Taylor |
Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 89-92, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Jing Lu, John W. Lockwood |
IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Kyrre Glette, Jim Tørresen |
A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 6th International Conference, ICES 2005, Sitges, Spain, September 12-14, 2005, Proceedings, pp. 66-75, 2005, Springer, 3-540-28736-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Monica Alderighi, A. Candelori, Fabio Casini, Sergio D'Angelo, Marcello Mancini, Alessandro Paccagnella, Sandro Pastore, Giacomo R. Sechi |
Heavy Ion Effects on Configuration Logic of Virtex FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 49-53, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis |
The Virtex II ProTM MOLEN Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 192-202, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin 0001 |
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 394-401, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek |
Post-placement C-slow retiming for the xilinx virtex FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 185-194, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
C-slow retiming, FPGA CAD, FPGA optimization, retiming |
29 | Xiaojun Wang, Brent E. Nelson |
Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 8-11 April 2003, Napa, CA, USA, Proceedings, pp. 195-, 2003, IEEE Computer Society, 0-7695-1979-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, A. Marmo, Sandro Pastore, Giacomo R. Sechi |
A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 71-78, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Ian Robertson, James Irvine 0001, Patrick Lysaght, David Robinson |
Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 127-135, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, verification, dynamic reconfiguration, run-time reconfiguration |
29 | Matthias Dyer, Christian Plessl, Marco Platzner |
Partially Reconfigurable Cores for Xilinx Virtex. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 292-301, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Alexander Staller, Peter Dillinger, Reinhard Männer |
Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 503-512, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Trevor W. Fox, Laurence E. Turner |
Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 492-502, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Oswaldo Cadenas, Graham M. Megson |
A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 322-331, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Tim Courtney, Richard H. Turner, Roger F. Woods |
Multiplexer Based Reconfiguration for Virtex Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 749-758, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Gordon Hollingworth, Steve Smith, Andy M. Tyrrell |
The Intrinsic Evolution of Virtex Devices Through Internet Reconfigurable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, Third International Conference, ICES 2000, Edinburgh, Scotland, UK, April 17-19, 2000, Proceedings, pp. 72-79, 2000, Springer, 3-540-67338-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Hao Wang, Shi Pu, Gabriel Knezek, Jyh-Charn Liu |
A modular NFA architecture for regular expression matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 209-218, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
character class constraint repetition, overlapped matching, FPGA, regular expression, NFA |
24 | Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003 |
Intel nehalem processor core made FPGA synthesizable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 3-12, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
intel nehalem, synthesizable core, fpga, emulator |
24 | Lei Chen 0010, Zhiquan Zhang, Zhiping Wen 0001 |
A novel BIST approach for testing input/output buffers in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 285, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
i/o buffers, built-in self-test, fpga testing |
24 | Pramod Kumar Meher, Jagdish Chandra Patra |
Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 43-48, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Patrick Lysaght, Brandon Blodget, Jeff Mason, Jay Young, Brendan Bridgford |
Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Roar Lien, Tim Grembowski, Kris Gaj |
A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2004, The Cryptographers' Track at the RSA Conference 2004, San Francisco, CA, USA, February 23-27, 2004, Proceedings, pp. 324-338, 2004, Springer, 3-540-20996-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Saber Krim, Mohamed Faouzi Mimouni |
Design and Xilinx Virtex-field-programmable gate array for hardware in the loop of sensorless second-order sliding mode control and model reference adaptive system-sliding mode observer for direct torque control of induction motor drive. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Control. Eng. ![In: J. Syst. Control. Eng. 237(5), pp. 839-869, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | N. Sathiabama, S. Anila |
A Universal BIST Approach for Virtex-Ultrascale Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Syst. Sci. Eng. ![In: Comput. Syst. Sci. Eng. 45(3), pp. 2705-2720, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Chang Cai, Bingxu Ning, Xue Fan, Tianqi Liu, Lingyun Ke, Gengsheng Chen, Jian Yu, Ze He, Liewei Xu, Jie Liu 0032 |
SEU sensitivity and large spacing TMR efficiency of Kintex-7 and Virtex-7 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 65(2), 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | M. Vivekanandan, Subramanian Kanaga Suba Raja |
Virtex-II Pro FPGA Based Smart Agricultural System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 125(1), pp. 119-141, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Ahmed J. Abd El-Maksoud, Amr Gamal, Aya Hesham, Gamal Saied, Mennat-Allah Ayman, Omnia Essam, Sara M. Mohamed, Eman El Mandouh, Ziad Ibrahim, Sara Mohamed, Hassan Mostafa |
Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: International Conference on Microelectronics, ICM 2021, New Cairo City, Egypt, December 19-22, 2021, pp. 70-73, 2021, IEEE, 978-1-6654-0839-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Karan Desai, Justin Johnson 0001 |
VirTex: Learning Visual Representations From Textual Annotations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR ![In: IEEE Conference on Computer Vision and Pattern Recognition, CVPR 2021, virtual, June 19-25, 2021, pp. 11162-11173, 2021, Computer Vision Foundation / IEEE. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
21 | Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa |
Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISDCS ![In: 4th International Symposium on Devices, Circuits and Systems, ISDCS 2021, Higashi-Hiroshima, Japan, March 3-5, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1478-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Mahendrakumar Gunasekaran, Kumar Rahul, Santosh Yachareni |
Optimizing Sub bytes and Mix Column to improve performance of AES in Virtex 7 FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNCC ![In: International Symposium on Networks, Computers and Communications, ISNCC 2021, Dubai, United Arab Emirates, October 31 - November 2, 2021, pp. 1-5, 2021, IEEE, 978-1-6654-0304-7. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
21 | Baoju Chen, Simin Yu, Ping Chen, Liangshan Xiao, Jinhu Lü |
Design and Virtex-7-Based Implementation of Video Chaotic Secure Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Bifurc. Chaos ![In: Int. J. Bifurc. Chaos 30(5), pp. 2050075:1-2050075:24, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Karan Desai, Justin Johnson 0001 |
VirTex: Learning Visual Representations from Textual Annotations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2006.06666, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
21 | Ali H. Gad, Seif Eldeen E. Abdalazeem, Omar A. Abdelmegid, Hassan Mostafa |
Low power and area SHA-256 hardware accelerator on Virtex-7 FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NILES ![In: 2nd Novel Intelligent and Leading Emerging Sciences Conference, NILES 2020, Giza, Egypt, October 24-26, 2020, pp. 181-185, 2020, IEEE, 978-1-7281-8226-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Abd El-Rahman Mohsen, Mohamed Youssef GadAlrab, Zeina elhaya Mahmoud, Gameel Alshaer, Mahmoud Asy, Hassan Mostafa |
Remote FPGA Lab For ZYNQ and Virtex-7 Kits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019, Dallas, TX, USA, August 4-7, 2019, pp. 185-188, 2019, IEEE, 978-1-7281-2788-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Abbas Yazdinejad, Ali Bohlooli, Kamal Jamshidi |
Efficient design and hardware implementation of the OpenFlow v1.3 Switch on the Virtex-6 FPGA ML605. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 74(3), pp. 1299-1320, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Javier Olivito, Felipe Serrano, Juan Antonio Clemente, Hortensia Mecha, Javier Resano |
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 12(4), pp. 150-157, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Lars Engeln, Rainer Groh 0001 |
VirtEx: Eine Ontologie-basierte Virtuelle Ausstellungen. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MuC ![In: Mensch und Computer 2018 - Tagungsband, Dresden, Germany, September 2-5, 2018., 2018, Gesellschaft für Informatik e.V.. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Chao Wang, Shengjun Xiong |
A High-precision Underwater Acoustic Communication Signal Modeling Method Based on VirTEX Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSPCC ![In: 2018 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC), Qingdao, China, September 14-16, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-7946-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Tingting Yu, Lei Chen 0010, Xuewu Li, Shuo Wang, Jing Zhou |
Analyzing the Single Event Upset Sensitivity of Digital Clock Manager in Virtex-5 FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEA ![In: Proceedings of the 6th International Conference on Informatics, Environment, Energy and Applications, IEEA '17, Jeju, Republic of Korea, March 29-31, 2017, pp. 112-116, 2017, ACM, 978-1-4503-5230-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|