Search results for "adders"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
104	Seiji Kajihara, Tsutomu Sasao	On the Adders with Minimum Tests.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	ripple carry adder, minimum test set, test generation, stuck-at fault, carry look-ahead adders
92	Akhilesh Tyagi	A Reduced-Area Scheme for Carry-Select Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders
88	Javier Hormigo, Manuel Ortiz, Francisco J. Quiles 0002, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata	Efficient Implementation of Carry-Save Adders in FPGAs.	ASAP	2009	DBLP DOI BibTeX RDF
88	Mary D. Brown, Yale N. Patt	Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files.	HPCA	2002	DBLP DOI BibTeX RDF	redundant binary, limited bypass, pipelined register file, signed digit
88	Oscar Gustafsson, Henrik Ohlsson, Lars Wanhammar	Minimum-adder integer multipliers using carry-save adders.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
79	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Power-delay characteristics of CMOS adders.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
77	Stanislaw J. Piestrak	Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	residue generators, multioperand modular adders, arithmetic error detecting codes, binary-to-residue number system, residue generator, digital arithmetic, adders, Chinese remainder theorem, residue number system, arithmetic codes, residue arithmetic, carry-save adders
77	Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija	Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	delay optimisation, block carry-lookahead adders, multidimensional dynamic programming, worst-case carry propagation delays, minimum latency, fanin, dynamic programming, digital arithmetic, adders, gate delays, carry logic, fanout, critical path delay, carry-skip adders
76	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Easily Testable Cellular Carry Lookahead Adders.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model
73	Dilip P. Vasudevan, Parag K. Lala	A Technique for Modular Design of Self-Checking Carry-Select Adder.	DFT	2005	DBLP DOI BibTeX RDF
71	Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos	High-Speed Parallel-Prefix Modulo 2n-1 Adders.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Modulo $2^n-1$ adders, VLSI design, parallel-prefix adders, carry look-ahead adders
71	Hans Lindkvist, Per Andersson	Dynamic CMOS circuit techniques for delay and power reduction in parallel adders .	ARVLSI	1995	DBLP DOI BibTeX RDF	dynamic CMOS circuit techniques, delay reduction, parallel adders, high-speed adders, Manchester-carry chains, clock/data precharged dynamic logic blocks, carry calculation trees, parallel processing, VLSI, delays, logic design, digital arithmetic, power consumption, adders, CMOS logic circuits, power reduction, carry logic
64	Javier D. Bruguera, Tomás Lang	Multilevel Reverse-Carry Addition: Single and Dual Adders.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	prefix adders, dual adders, most-significant-carry detection, computer arithmetic, VLSI design
64	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
63	Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait	Area-time optimal adder with relative placement generator.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
62	Vitit Kantabutra	Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	accelerated two-level carry-skip adders, bit positions, bimodal, CMOS VLSI, 12.6 sec, VLSI, delays, adders, CMOS integrated circuits, unimodal, 2 micron
62	Luigi Dadda, Vincenzo Piuri	Pipelined Adders.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	high-speed adders, high-throughput adders, skewed arithmetic, Adders, pipelined computation
62	Hung Chi Lai, Saburo Muroga	Logic Networks of Carry-Save Adders.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders
62	Hung Chi Lai, Saburo Muroga	Minimum Parallel Binary Adders with NOR (NAND) Gates.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	NOR gates, carry-ripple adders, minimum adders, NAND gates, logic design, Adders
61	Jeong-Gun Lee, Jeong-A Lee, Byeong-Seok Lee, Milos D. Ercegovac	A Design Method for Heterogeneous Adders.	ICESS	2007	DBLP DOI BibTeX RDF
61	Sumeer Goel, Ashok Kumar 0001, Magdy A. Bayoumi	Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
61	Johannes Grad, James E. Stine	Low power binary addition using carry increment adders.	ISCAS	2006	DBLP DOI BibTeX RDF
61	Keshab K. Parhi	Low-energy CSMT carry generators and binary adders.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
58	Giorgos Dimitrakopoulos, Dimitris Nikolos	High-Speed Parallel-Prefix VLSI Ling Adders.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	parallel-prefix carry computation, computer arithmetic, VLSI design, Adders
58	Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel	Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders.	ASYNC	1997	DBLP DOI BibTeX RDF	completion detection, Brent-Kung, Carry-Bypass, asynchronous, adders, hazards, high-performance design
54	R. Mahesh 0001, A. Prasad Vinod 0001	A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
54	Ajay Kumar Verma, Paolo Ienne	Automatic synthesis of compressor trees: reevaluating large counters.	DATE	2007	DBLP DOI BibTeX RDF
54	Douglas L. Maskell, Jussipekka Leiwo, Jagdish Chandra Patra	The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity.	ISCAS	2006	DBLP DOI BibTeX RDF
54	Johannes Grad, James E. Stine	New algorithms for carry propagation.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	carry propagate addition, conditional sum adder, hybrid adder, ling adder, pseudo-complements, reed adder, domino logic, carry-skip adder
52	Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi 0001	A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
52	Ilya Obridko, Ran Ginosar	Minimal Energy Asynchronous Dynamic Adders.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
52	Giorgos Dimitrakopoulos, Pavlos Kolovos, P. Kalogerakis, Dimitris Nikolos	Design of High-Speed Low-Power Parallel-Prefix VLSI Adders.	PATMOS	2004	DBLP DOI BibTeX RDF
52	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin	Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders.	PATMOS	2003	DBLP DOI BibTeX RDF
52	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin	Automatic Generation of 1-of-M QDI Asynchronous Adders.	SBCCI	2003	DBLP DOI BibTeX RDF
52	Radomir S. Stankovic, Jaakko Astola	Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision Diagrams.	ISMVL	2002	DBLP DOI BibTeX RDF	Decision diagrams, Logic design, Switching functions, Spectral transforms
52	Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
52	Uming Ko, T. Balsara, Wai Lee	Low-power design techniques for high-performance CMOS adders.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
49	Giacomo Paci, Paul Marchal, Luca Benini	Exploration of Low Power Adders for a SIMD Data Path.	ASP-DAC	2007	DBLP DOI BibTeX RDF	SIMD data path, low power adders
49	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Modulo 2n±1 Adder Design Using Select-Prefix Blocks.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	modulo 2n± 1 adders, select-prefix adders, computer arithmetic, VLSI architectures
49	Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos	Diminished-One Modulo 2n+1 Adder Design.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Modulo $big. 2^{rm n}+1bigr.$ addition, carry look-ahead addition, diminished-one number representation, VLSI adders, parallel-prefix adders
46	Chien-Hung Lin, Shu-Chung Yi, Jin-Jia Chen	Low Power Adders Design for Portable Video Terminal.	IIH-MSP	2008	DBLP DOI BibTeX RDF	low power adders, portable video terminal, Full adders
46	Vitit Kantabutra	Designing Optimum One-Level Carry-Skip Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	one-level, 64 bit, 6.23 ns, logic design, digital simulation, adders, SPICE simulation, carry-skip adders, 1 micron
46	Branislava Perunicic, Salim Lakhani, Veljko M. Milutinovic	Stochastic Modeling and Analysis of Propagation Delays in GaAs Adders.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	GaAs adders, stochastic changes, III-V semiconductors, probability, combinational circuits, stochastic modelling, stochastic processes, adders, combinatorial circuits, propagation delays, gate delays, GaAs, gallium arsenide, probability distribution function
46	Bernd Becker 0001	Efficient Testing of Optimal Time Adders.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	optimal time adders, conditional sum adder, VLSI, logic testing, adders, integrated logic circuits, VLSI chip, carry look-ahead adder
46	Riyaz A. Patel, Mohammed Benaissa, Said Boussakta	Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Modulo 2n-1 adders, One's complement adders, computer arithmetic, VLSI design, parallel-prefix adders
45	Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi 0001	Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms.	ISMVL	2003	DBLP DOI BibTeX RDF
43	Haridimos T. Vergos, Dimitris Bakalis	On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components.	DSD	2008	DBLP DOI BibTeX RDF
43	Erdal Oruklu, Vibhuti B. Dave, Jafar Saniie	Performance analysis of flagged prefix adders with logical effort.	ISCAS	2008	DBLP DOI BibTeX RDF
43	Álvaro Vázquez, Elisardo Antelo	New insights on Ling adders.	ASAP	2008	DBLP DOI BibTeX RDF
43	Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy 0001	Fine-Grained Redundancy in Adders.	ISQED	2007	DBLP DOI BibTeX RDF
43	Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas	Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.	VLSI Design	2006	DBLP DOI BibTeX RDF
43	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Fast Parallel-Prefix Modulo 2^n+1 Adders.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
43	Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou	Deterministic BIST for RNS Adders.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	deterministic and pseudorandom tests, formal test sets, Built-In Self-Test, Residue Number System
43	Jean-Luc Beuchat	Some Modular Adders and Multipliers for Field Programmable Gate Arrays.	IPDPS	2003	DBLP DOI BibTeX RDF	modulo m addition, modulo m multiplication, FPGA, Computer arithmetic
43	Bernd Becker 0001, Reiner Kolla	On the Construction of Optimal Time Adders (Extended Abstract).	STACS	1988	DBLP DOI BibTeX RDF
40	Jianhua Liu, Yi Zhu 0002, Haikun Zhu, Chung-Kuan Cheng, John Lillis	Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space.	ASP-DAC	2007	DBLP DOI BibTeX RDF	optimum prefix adders, static power consumptions, dynamic power consumptions, high-level synthesis, integer linear programming, buffer insertion, gate sizing, power models, ASIC designs, parallel prefix adder, binary adder
40	Peter Kornerup	Reviewing 4-to-2 Adders for Multi-Operand Addition.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	redundant adders, digit sets, digit encodings, multiplier trees
40	Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald	Self-Timed Carry-Lookahead Adders.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	delay-insenstive circuits, tree iterative circuits, CMOS, Self-timed circuits, carry-lookahead adders
40	José Fernández Ramos, Alfonso Gago Bohórquez	Two Operand Binary Adders with Threshold Logic.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	neural networks, logic design, computer arithmetic, Threshold logic, threshold gate, binary adders
40	Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer	Testing Schemes for FIR Filter Structures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Complex multipliers, sign-extended adders, trees of adders, design for testability, FIR filters, pseudoexhaustive testing, state coverage, cell fault model
40	Priyadarsan Patra, Donald S. Fussell	Fully asynchronous, robust, high-throughput arithmetic structures.	VLSI Design	1995	DBLP DOI BibTeX RDF	fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers
36	Swaroop Ghosh, Kaushik Roy 0001	Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
36	Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie	Design and Synthesis of a Three Input Flagged Prefix Adder.	ISCAS	2007	DBLP DOI BibTeX RDF
36	A. Prasad Vinod 0001, Edmund Ming-Kit Lai	Low power and high-speed implementation of fir filters for software defined radio receivers.	IEEE Trans. Wirel. Commun.	2006	DBLP DOI BibTeX RDF
36	Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu	The new architecture of radix-4 Chinese abacus adder.	ISMVL	2006	DBLP DOI BibTeX RDF
36	A. Prasad Vinod 0001, Edmund Ming-Kit Lai	On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
36	Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal	On the Advantages of Serial Architectures for Low-Power Reliable Computations.	ASAP	2005	DBLP DOI BibTeX RDF
34	Jeff Rebacz, Erdal Oruklu, Jafar Saniie	High performance signed-digit decimal adders.	EIT	2009	DBLP DOI BibTeX RDF
34	Fatemeh Eslami, Amirali Baniasadi, Mostafa Farahani	Application Specific Transistor Sizing for Low Power Full Adders.	ASAP	2009	DBLP DOI BibTeX RDF
34	Wenjing Rao, Alex Orailoglu	Towards fault tolerant parallel prefix adders in nanoelectronic systems.	DATE	2008	DBLP DOI BibTeX RDF
34	Hirokatsu Shirahama, Takahiro Hanyu	Design of High-Performance Quaternary Adders Based on Output-Generator Sharing.	ISMVL	2008	DBLP DOI BibTeX RDF	Carry pre-addition, Differential-pair circuitry, Voltage-mode circuit, Transfer-gate circuitry, Current-mode circuit
34	Zine Abid, Wei Wang 0003	New designs of Redundant-Binary full Adders and its applications.	ISCAS	2008	DBLP DOI BibTeX RDF
34	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.	ISVLSI	2007	DBLP DOI BibTeX RDF
34	Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo	Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition.	DSD	2007	DBLP DOI BibTeX RDF
34	Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii	Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study.	ICESS	2007	DBLP DOI BibTeX RDF
34	Sheng Sun, Carl Sechen	Post-layout comparison of high performance 64b static adders in energy-delay space.	ICCD	2007	DBLP DOI BibTeX RDF
34	A. Neslin Ismailoglu, Murat Askar	Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
34	Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy 0001	Comparison of high-performance VLSI adders in the energy-delay space.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
34	Rumi Zhang, Wei Wang 0003, Konrad Walus, Graham A. Jullien	Performance comparison of quantum-dot cellular automata adders.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
34	Jin-Fu Li 0001, Jiunn-Der Yu, Yu-Jen Huang	A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
34	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Test Generation Methodology for High-Speed Floating Point Adders.	IOLTS	2005	DBLP DOI BibTeX RDF
34	Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata	On-line Multioperand Addition Based on On-line Full Adders.	ASAP	2005	DBLP DOI BibTeX RDF
34	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis	Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.	ISVLSI	2004	DBLP DOI BibTeX RDF
34	Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris	Fast adders in modern FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
34	Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy 0001	Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
34	Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
34	Simon Knowles	A Family of Adders.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
34	Viv A. Bartlett, Andrew G. Dempster	Using carry-save adders in low-power multiplier blocks.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
34	Henrik Eriksson, Per Larsson-Edefors, William P. Marnane	A regular parallel multiplier which utilizes multiple carry-propagate adders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
34	Athanasios Kakarountas, Kyriakos Papadomanolakis, Vasileios Kokkinos, Constantinos E. Goutis	Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance.	PATMOS	2000	DBLP DOI BibTeX RDF
34	Simon Knowles	A Family of Adders.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
34	Sae Hwan Kim, Shiu-Kai Chin	Formal Verification of Tree-Structured Carry-Lookahead Adders.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
34	Shanzhen Xing, William W. H. Yu	FPGA Adders: Performance Evaluation and Optimal Design.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
34	Yirng-An Chen, Randal E. Bryant	Verification of Floating-Point Adders.	CAV	1998	DBLP DOI BibTeX RDF
33	Levent Aksoy, Ece Olcay Günes	Area optimization algorithms in high-speed digital FIR filter synthesis.	SBCCI	2008	DBLP DOI BibTeX RDF	high-speed filter design, multiple constant multiplications, subexpression sharing, area optimization, carry-save adders
33	Luigi Dadda	Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	multioperand adders, Computer arithmetic, hardware design, decimal arithmetic
33	Ann Majchrzak, Christian Wagner 0001, Dave Yates	Corporate wiki users: results of a survey.	Int. Sym. Wikis	2006	DBLP DOI BibTeX RDF	corporate wiki, knowledge contribution, knowledge restructuring, survey, adders, knowledge reuse, synthesizers
32	Chandan Kumar Jha 0001, Ankita Nandi, Joycee Mekie	Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
32	Vishesh Mishra, Neelofar Hassan, Akshay Mehta, Urbi Chatterjee	DARK-Adders: Digital Hardware Trojan Attack on Block-based Approximate Adders.	VLSID	2023	DBLP DOI BibTeX RDF
32	Daniel Etiemble	Two New CNTFET Quaternary Full Adders for Carry-Propagate Adders.	CoRR	2022	DBLP DOI BibTeX RDF