Search results for "bitcell"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
109	Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy 0001	A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.	ISLPED	2007	DBLP DOI BibTeX RDF	low power SRAM, low voltage SRAM, schmitt trigger, subthreshold SRAM, process variations
68	R. Venkatraman, R. Castagnetti, S. Ramesh 0004	The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability.	ISQED	2006	DBLP DOI BibTeX RDF
65	Jaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy 0001	Process variation tolerant SRAM array for ultra low voltage applications.	DAC	2008	DBLP DOI BibTeX RDF	Schmitt trigger SRAM, low voltage/sub-threshold SRAM, process tolerance
65	Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim	Yield-driven near-threshold SRAM design.	ICCAD	2007	DBLP DOI BibTeX RDF
44	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan	Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.	VLSI Design	2009	DBLP DOI BibTeX RDF
36	Rabiul Islam, Adam Brand, Dave Lippincott	Low power SRAM techniques for handheld products.	ISLPED	2005	DBLP DOI BibTeX RDF	back-bias, bitcell, memory, leakage
25	Jae-Gun Lee, Shin-Uk Kang, Min-Seong Choo	Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application.	ICEIC	2024	DBLP DOI BibTeX RDF
25	Eunhwan Kim, Hyunmyung Oh, Nameun Kang, Jihoon Park, Jae-Joon Kim	A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
25	Hoichang Jeong, Seungbin Kim, Keonhee Park, Jueun Jung, Kyuho Jason Lee	A Ternary Neural Network Computing-in-Memory Processor With 16T1C Bitcell Architecture.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
25	Keonhee Park, Hoichang Jeong, Kyuho Lee	A 701.7 TOPS/W Time-Domain Spiking Neural Network Compute-in-Memory Processor with 9T1C Bitcell.	MWSCAS	2023	DBLP DOI BibTeX RDF
25	Gajanan Jedhe, Chetan Deshpande, Sushil Kumar, Cheng-Xin Xue, Zijie Guo, Ritesh Garg, Kim Soon Jway, En-Jui Chang, Jenwei Liang, Zhe Wan, Zhenhao Pan	A 12nm 137 TOPS/W Digital Compute-In-Memory using Foundry 8T SRAM Bitcell supporting 16 Kernel Weight Sets for AI Edge Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Wei-Xiang You, Cheng-Yin Wang, Yih Wang, Tsung-Yung Jonathan Chang, Szuya Sandy Liao	Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Joydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto	ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
25	Zizhao Ma, Xianwu Hu, Yihao Wang, Gan Wen, Xiaoyang Zeng, Yufeng Xie	A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation.	ISCAS	2023	DBLP DOI BibTeX RDF
25	Salimeh Shahrabadi	Challenges and solutions of working under threshold supply-voltage, for CNTFET-based SRAM-bitcell.	IET Circuits Devices Syst.	2022	DBLP DOI BibTeX RDF
25	Dashan Shi, Jia Yuan, Jialu Yin, Yulian Wang, Shushan Qiao	A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
25	Rishab Mehra, S. S. Teja Nibhanupudi, Jaydeep P. Kulkarni	Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation.	DRC	2022	DBLP DOI BibTeX RDF
25	Hidehiro Fujiwara, Yi-Hsin Nien, Chih-Yu Lin, Hsien-Yu Pan, Hao-Wen Hsu, Shin-Rung Wu, Yao-Yi Liu, Yen-Huei Chen, Hung-Jen Liao, Jonathan Chang	A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue.	ISSCC	2021	DBLP DOI BibTeX RDF
25	Hao Zhang, Jieyu Li, Weifeng He, Yanan Sun 0003, Mingoo Seok	An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM.	ISCAS	2021	DBLP DOI BibTeX RDF
25	Sarthak Jain, R. S. Gamad 0001, R. C. Gurjar	Design of a Low-Power One-Sided Schmitt-Trigger Based 13T SRAM Bitcell.	ICCCNT	2021	DBLP DOI BibTeX RDF
25	Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De	Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS.	VLSI Circuits	2020	DBLP DOI BibTeX RDF
25	Shamma Nasrin, Srikanth Ramakrishna, Theja Tulabandhula, Amit Ranjan Trivedi	Supported-BinaryNet: Bitcell Array-Based Weight Supports for Dynamic Accuracy-Energy Trade-Offs in SRAM-Based Binarized Neural Network.	ISCAS	2020	DBLP DOI BibTeX RDF
25	Chunyu Peng, Jiati Huang, Changyong Liu, Qiang Zhao 0007, Songsong Xiao, Xiulong Wu, Zhiting Lin, Junning Chen, Xuan Zeng 0001	Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
25	Shamma Nasrin, Srikanth Ramakrishna, Theja Tulabandhula, Amit Ranjan Trivedi	Supported-BinaryNet: Bitcell Array-based Weight Supports for Dynamic Accuracy-Latency Trade-offs in SRAM-based Binarized Neural Network.	CoRR	2019	DBLP BibTeX RDF
25	Robert Giterman, Osnat Keren, Alexander Fish	A 7T Security Oriented SRAM Bitcell.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
25	Mahmood Uddin Mohammed, Athiya Nizam, Liaquat Ali, Masud H. Chowdhury	A Low Leakage SRAM Bitcell Design Based on MOS-Type Graphene Nano-Ribbon FET.	ISCAS	2019	DBLP DOI BibTeX RDF
25	Jianwei Jiang 0001, Dianpeng Lin, Jun Xiao, Shichang Zou	Soft-Error-Tolerant Ultralow-Leakage 12T SRAM Bitcell Design.	ICICDT	2019	DBLP DOI BibTeX RDF
25	Zhewei Jiang, Shihui Yin, Jae-sun Seo, Mingoo Seok	XNOR-SRAM: In-Bitcell Computing SRAM Macro based on Resistive Computing Mechanism.	ACM Great Lakes Symposium on VLSI	2019	DBLP DOI BibTeX RDF
25	Debin Kong, Jia Yuan, Shan-Shan Li, Heng You, Shushan Qiao	A robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
25	Mahmood Uddin Mohammed, Nahid M. Hossain, Masud H. Chowdhury	A Disturb Free Read Port 8T SRAM Bitcell Circuit Design with Virtual Ground Scheme.	MWSCAS	2018	DBLP DOI BibTeX RDF
25	Roman Golman, Robert Giterman, Adam Teman	Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism.	ICECS	2018	DBLP DOI BibTeX RDF
25	Xin Fan 0002, Rui Wang, Tobias Gemmeke	Physical modeling of bitcell stability in subthreshold SRAMs for leakage-area optimization under PVT variations.	ICCAD	2018	DBLP DOI BibTeX RDF
25	Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Adam Makosiej, Marco Antonio Rios, Eduardo Esmanhotto, Emilien Bourde-Cicé, Mathis Bellet, David Turgis, Edith Beigné	Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology.	NANOARCH	2018	DBLP DOI BibTeX RDF
25	Mounia Kharbouche-Harrari, Jérémy Postel-Pellerin, Gregory di Pendina, Romain Wacquez, Driss Aboulkassimi, Marc Bocquet, R. Sousa, R. Delattre, Jean-Michel Portal	Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues.	IOLTS	2018	DBLP DOI BibTeX RDF
25	Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Kaya Can Akyel, Melanie Brocard, David Turgis, Edith Beigné	High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
25	Robert Giterman, Adam Teman, Pascal Meinerzhagen	Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
25	Nahid M. Hossain, Arif Iqbal, Hemanshu Shishupal, Masud H. Chowdhury	Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain.	MWSCAS	2017	DBLP DOI BibTeX RDF
25	Nikita Gupta, Pragati Thakur, Shashank Kumar Dubey, Aminul Islam 0002	Design of nonvolatile MRAM bitcell.	ISED	2017	DBLP DOI BibTeX RDF
25	Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel	1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell.	ESSCIRC	2017	DBLP DOI BibTeX RDF
25	Thomas Haine, Quoc-Khoi Nguyen, François Stas, Ludovic Moreau, Denis Flandre, David Bol	An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation.	ESSCIRC	2017	DBLP DOI BibTeX RDF
25	Lior Atias, Adam Teman, Robert Giterman, Pascal Meinerzhagen, Alexander Fish	A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
25	Yong Ye, Yong Kang, Chao Zhang, Yipeng Chan, Hanming Wu, Shiuhwuu Lee, Zhitang Song, Bomy Chen	A 40-nm 16-Mb Contact-Programming Mask ROM Using Dual Trench Isolation Diode Bitcell.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
25	Qingyu Chen, Haibin Wang, Li Chen 0001, Lixiang Li 0001, Xing Zhao, Rui Liu 0011, Mo Chen, Xuantian Li	An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology.	J. Electron. Test.	2016	DBLP DOI BibTeX RDF
25	Saket Gupta, Carl Monzel, Daniel S. Reed, Yifei Zhang, Mark Winter, Myron Buer	Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
25	Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel	16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell.	ESSDERC	2016	DBLP DOI BibTeX RDF
25	Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel	3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications.	DATE	2016	DBLP BibTeX RDF
25	Azeez Bhavnagarwala, Imran Iqbal, An Nguyen, David Ondricek, Vikas Chandra, Robert C. Aitken	A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um2 6T bitcell in a 16nm FinFET CMOS process.	VLSI Circuits	2016	DBLP DOI BibTeX RDF
25	Harsh N. Patel, Farah B. Yahya, Benton H. Calhoun	Optimizing SRAM bitcell reliability and energy for IoT applications.	ISQED	2016	DBLP DOI BibTeX RDF
25	Lixiang Li 0001, Yuanqing Li, Haibin Wang, Rui Liu 0011, Qiong Wu, Michael Newton, Yuan Ma, Li Chen 0001	Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
25	Samira Ataei, James E. Stine	A differential single-port 8T SRAM bitcell for variability tolerance and low voltage operation.	IGSC	2015	DBLP DOI BibTeX RDF
25	Jiangyi Li, Mingoo Seok	A 3.07μm2/bitcell physically unclonable function with 3.5% and 1% bit-instability across 0 to 80°C and 0.6 to 1.2V in a 65nm CMOS.	VLSIC	2015	DBLP DOI BibTeX RDF
25	Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel, Anis Feki, Sylvain Clerc, Lorenzo Ciampolini, Fabien Giner, Robin Wilson, Philippe Roche	Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
25	Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa	28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
25	Shusuke Yoshimoto, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2014	DBLP DOI BibTeX RDF
25	Arundhati Bhattacharya, Aminul Islam 0002	Design and Analysis of Robust Spin Transfer Torque Magnetic Random Access Memory Bitcell Using FinFET.	J. Low Power Electron.	2014	DBLP DOI BibTeX RDF
25	Adam Teman, Anatoli Mordakhay, Alexander Fish	Functionality and stability analysis of a 400 mV quasi-static RAM (QSRAM) bitcell.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
25	Fady Abouzeid, Audrey Bienfait, Kaya Can Akyel, Sylvain Clerc, Lorenzo Ciampolini, Philippe Roche	Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI.	ESSCIRC	2013	DBLP DOI BibTeX RDF
25	Arijit Raychowdhury	Pulsed READ in spin transfer torque (STT) memory bitcell for lower READ disturb.	NANOARCH	2013	DBLP DOI BibTeX RDF
25	Isha Garg, Prakhar Sharma	Estimation of SNM in latches and subsequent formation of a 10T CNFET bitcell.	WISES	2013	DBLP BibTeX RDF
25	Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure.	IEICE Trans. Electron.	2012	DBLP DOI BibTeX RDF
25	G. K. Reddy, Kapil Jainwal, Jawar Singh, Saraju P. Mohanty	Process variation tolerant 9T SRAM bitcell design.	ISQED	2012	DBLP DOI BibTeX RDF
25	Anis Feki, Bruno Allard, David Turgis, Jean-Christophe Lafont, Lorenzo Ciampolini	Proposal of a new ultra low leakage 10T sub threshold SRAM bitcell.	ISOCC	2012	DBLP DOI BibTeX RDF
25	Jaydeep P. Kulkarni, Ashish Goel, Patrick Ndai, Kaushik Roy 0001	A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
25	Seung Chul Song, M. Abu-Rahma, Geoffrey Yeap	FinFET based SRAM bitcell design for 32 nm node and below.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
25	Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure.	IOLTS	2011	DBLP DOI BibTeX RDF
25	Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto	Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control.	ISQED	2011	DBLP DOI BibTeX RDF
25	Brice Lhomme, Yann Carminati, Bertrand Borot, Olivier Callen, Thierry Burdeau, Sylvain Clerc	A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter.	ESSCIRC	2010	DBLP DOI BibTeX RDF
25	Lahcen Hamouche, Bruno Allard	SRAM portless bitcell and current-mode reading.	ISCAS	2010	DBLP DOI BibTeX RDF
25	Bai Na, Xuan Chen, Yang Jun, Longxin Shi	A differential read subthreshold SRAM bitcell with self-adaptive leakage cut off scheme.	SoCC	2010	DBLP DOI BibTeX RDF
25	Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan	A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead.	ISQED	2010	DBLP DOI BibTeX RDF
25	Qi Li, Tony T. Kim	A 9T subthreshold SRAM bitcell with data-independent bitline leakage for improved bitline swing and variation tolerance.	APCCAS	2010	DBLP DOI BibTeX RDF
25	Jawar Singh	Robust power aware SRAM bitcell designs.		2009	RDF
22	Sreeharsha Tavva, Dhireesha Kudithipudi	Variation tolerant 9T SRAM cell design.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bitline leakage, static random access memory (SRAM), process variations, static noise margin, embedded sram
22	Amith Singhee, Pamela Castalino	Pareto sampling: choosing the right weights by derivative pursuit.	DAC	2010	DBLP DOI BibTeX RDF	derivative pursuit, multi-objective optimization, tradeoff, Pareto
22	Oguz Ergin, Deniz Balkan, Dmitry Ponomarev 0001, Kanad Ghose	Early Register Deallocation Mechanisms Using Checkpointed Register Files.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	register file optimization, Superscalar processors, precise interrupts
22	Erwin J. Prinz	The zen of nonvolatile memories.	DAC	2006	DBLP DOI BibTeX RDF	FeRAM, SONOS, nanocrystal, oating gate, phase change memory, MRAM, nonvolatile memories
22	R. Castagnetti, R. Venkatraman, Brandon Bartz, Carl Monzel, T. Briscoe, Andres Teene, S. Ramesh 0004	A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC.	ISQED	2005	DBLP DOI BibTeX RDF
22	Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kanad Ghose	Increasing Processor Performance Through Early Register Release.	ICCD	2004	DBLP DOI BibTeX RDF
22	F. Duan, R. Castagnetti, R. Venkatraman, O. Kobozeva, S. Ramesh 0004	Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability.	ISQED	2003	DBLP DOI BibTeX RDF