Search results for "chip-multiprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
53	Satoshi Matsushita	Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification.	ISSS	2002	DBLP DOI BibTeX RDF	deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
51	Michael Gschwind	The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	compute-transfer parallelism, multi-level application parallelism, Chip multiprocessor, Cell Broadband Engine, heterogeneous chip multiprocessor
50	Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro	FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	secure mobile terminal, chip multiprocessor, linux
48	Slo-Li Chu	Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture.	LCPC	2007	DBLP DOI BibTeX RDF	Critical Block Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
45	Sebastian Herbert, Diana Marculescu	Characterizing chip-multiprocessor variability-tolerance.	DAC	2008	DBLP DOI BibTeX RDF	frequency islands, chip-multiprocessor, process variability
45	Slo-Li Chu	Toward to Utilize the Heterogeneous Multiple Processors of the Chip Multiprocessor Architecture.	EUC	2007	DBLP DOI BibTeX RDF	Swing Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory
45	Taeho Kgil, Shaun D'Souza, Ali G. Saidi, Nathan L. Binkert, Ronald G. Dreslinski, Trevor N. Mudge, Steven K. Reinhardt, Krisztián Flautner	PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor.	ASPLOS	2006	DBLP DOI BibTeX RDF	3D stacking technology, tier 1 server, web/file/streaming server, low power, chip multiprocessor, full-system simulation
45	Lucian Codrescu, D. Scott Wills, James D. Meindl	Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Thread speculation, multiscalar, parallelization, chip-multiprocessor, multithreading, value prediction
43	Kyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou	Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
42	Xi Zhang 0008, Dongsheng Wang 0002, Yibo Xue, Haixia Wang 0001, Jinglei Wang	A Novel Cache Organization for Tiled Chip Multiprocessor.	APPT	2009	DBLP DOI BibTeX RDF	Multi-level Directory, Chip Multiprocessor(CMP), Cache Organization, Tiled Architecture
42	Magnus Jahre, Lasse Natvig	A light-weight fairness mechanism for chip multiprocessor memory systems.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	dynamic miss handling architecture, miss status holding register, fairness, chip multiprocessor, interference, mechanism
42	Hiroaki Inoue, Junji Sakai, Sunao Torii, Masato Edahiro	FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	Secure mobile terminal, chip multiprocessor, SELinux
42	Yi-Neng Lin, Ying-Dar Lin, Yuan-Cheng Lai	Thread Allocation in Chip Multiprocessor Based Multithreaded Network Processors.	AINA	2008	DBLP DOI BibTeX RDF	thread allocation, simulation, modeling, Petri net, chip multiprocessor
42	Li Yang 0001, Lu Peng 0001	SecCMP: a secure chip-multiprocessor architecture.	ASID	2006	DBLP DOI BibTeX RDF	security, fault-tolerance, encryption, chip-multiprocessor
42	Peter G. Sassone, D. Scott Wills	Scaling Up the Atlas Chip-Multiprocessor.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Dynamic multithreading, chip-multiprocessor, scaling
42	Mladen Nikitovic, Mats Brorsson	An adaptive chip-multiprocessor architecture for future mobile terminals.	CASES	2002	DBLP DOI BibTeX RDF	chip-multiprocessor (CMP), power consumption, mobile terminals, energy-aware scheduling
41	Ozcan Ozturk 0001, Guangyu Chen, Mahmut T. Kandemir	Multi-compilation: capturing interactions among concurrently-executing applications.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	multi-compilation, compiler, chip multiprocessor
40	Akira Yamawaki 0002, Masahiko Iwane	Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor.	ISPAN	2005	DBLP DOI BibTeX RDF
40	Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi	Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.	ASP-DAC	2009	DBLP DOI BibTeX RDF
39	Masafumi Takahashi, Hiroyuki Takano, Emi Kaneko, Seigo Suzuki	A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor.	HPCA	1996	DBLP DOI BibTeX RDF
37	Raphael Fonte Boa, Dulcinéia Oliveira da Penha, Alexandre Marques Amaral, Márcio Oliveira Soares de Souza, Carlos Augusto Paiva da Silva Martins, Petr Yakovlevitch Ekel	RCMP: A Reconfigurable Chip-Multiprocessor Architecture.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
37	Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Kenneth G. Wilson, Kunyung Chang	The Case for a Single-Chip Multiprocessor.	ASPLOS	1996	DBLP DOI BibTeX RDF
36	Mainak Chaudhuri	PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches.	HPCA	2009	DBLP DOI BibTeX RDF
34	Vincent W. Freeh, Tyler K. Bletsch, Freeman L. Rawson III	Scaling and Packing on a Chip Multiprocessor.	IPDPS	2007	DBLP DOI BibTeX RDF
34	Degui Feng, Guanjun Jiang, Tiefei Zhang, Wei Hu 0001, Tianzhou Chen, Mingteng Cao	SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework.	APPT	2009	DBLP DOI BibTeX RDF	synchronization, Chip multiprocessor, transactional memory, scratchpad memory
34	Wan-Yu Lee, Iris Hui-Ru Jiang	VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, process variation, monte carlo analysis
34	Long Zheng 0001, Mianxiong Dong, Song Guo 0001, Minyi Guo, Li Li 0012	I-Cache Tag Reduction for Low Power Chip Multiprocessor.	ISPA	2009	DBLP DOI BibTeX RDF	tag reduction, chip multiprocessor, energy saving
34	Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003	Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor.	PACT	2008	DBLP DOI BibTeX RDF	ia32, on-chip integration, chip multiprocessor, heterogeneous
34	Christof Pitter	Time-predictable memory arbitration for a Java chip-multiprocessor.	JTRES	2008	DBLP DOI BibTeX RDF	Java, chip-multiprocessor, shared memory, worst-case execution time
34	Venkata Krishnan, Josep Torrellas	A Chip-Multiprocessor Architecture with Speculative Multithreading.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Chip-multiprocessor, speculative multithreading, data-dependence speculation, control speculation
33	Mainak Chaudhuri	Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.	MICRO	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, replacement policy, last-level cache
32	Lucian Codrescu, D. Scott Wills	Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications.	ICCD	1999	DBLP DOI BibTeX RDF
31	Pedro Trancoso, Paraskevas Evripidou, Kyriakos Stavrou, Costas Kyriacou	A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model.	Int. J. Parallel Program.	2006	DBLP DOI BibTeX RDF	data-driven execution, parallel processing, Chip multiprocessor, multithreading
31	Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi	Designing On-Chip Network Based on Optimal Latency Criteria.	ICESS	2005	DBLP DOI BibTeX RDF
30	Philip Machanick	Design principles for a virtual multiprocessor.	SAICSIT	2007	DBLP DOI BibTeX RDF	chip multiprocessor, instruction-level parallelism
30	Jugash Chandarlapati, Mainak Chaudhuri	LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation.	ICCD	2007	DBLP DOI BibTeX RDF
30	Haixia Wang 0001, Dongsheng Wang 0002, Peng Li 0031	Acceleration Techniques for Chip-Multiprocessor Simulator Debug.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
30	Wenbin Yao, Dongsheng Wang 0002, Weimin Zheng	A Fault-Tolerant Single-Chip Multiprocessor.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
30	Magnus Ekman, Per Stenström	Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores.	ICPP	2003	DBLP DOI BibTeX RDF
29	Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert 0001	GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications.	ARCS	2006	DBLP DOI BibTeX RDF
29	Mohamed M. Zahran	On cache memory hierarchy for Chip-Multiprocessor.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF
29	Markus Rudack, Dirk Niggemeyer	Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM.	DFT	1999	DBLP DOI BibTeX RDF
29	Lance Hammond, Mark Willey, Kunle Olukotun	Data Speculation Support for a Chip Multiprocessor.	ASPLOS	1998	DBLP DOI BibTeX RDF
28	Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Taylan Yemliha	SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors.	ICPADS (1)	2006	DBLP DOI BibTeX RDF	SPM (Scratch-Pad Memory), dynamic loop scheduling, parallelization, compiler, CMP (chip multiprocessor), data locality
28	Michael Gschwind	Chip multiprocessing and the cell broadband engine.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	compute-transfer parallelism (CTP), cell broadband engine, memory-level parallelism (MLP), chip multiprocessing, heterogeneous chip multiprocessor
28	Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Ozcan Ozturk 0001, Mustafa Karaköy, Ugur Sezer	Optimizing Array-Intensive Applications for On-Chip Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	On-chip multiprocessor, adaptive loop parallelization, embedded systems, energy consumption, integer linear programming, constrained optimization
28	Jaehyuk Huh 0001, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA substrate for flexible CMP cache sharing.	ICS	2005	DBLP DOI BibTeX RDF	cache sharing, non-uniform cache architecture, chip-multiprocessor
28	Shuichi Sakai	CMP on SoC: Architect's View.	ISSS	2002	DBLP DOI BibTeX RDF	CMP (Chip Multiprocessor), I/O centric, SoC (System on Chip), parallel processing, dependability
28	Venkata Krishnan, Josep Torrellas	The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	register communication, Chip-multiprocessor, speculative multithreading, data-dependence speculation
27	Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi	Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications.	VLSI Design	2009	DBLP DOI BibTeX RDF
27	Francisco J. Villa, Manuel E. Acacio, José M. García 0001	Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture.	HPCC	2005	DBLP DOI BibTeX RDF
27	Minoru Fujishima, Masahiro Shimura	On-chip high-speed solver of inverse problems based on quantum-computing principle.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Viktor K. Prasanna	Performance of On-Chip Multiprocessors for Vision Tasks.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
25	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network.	HiPC	2007	DBLP DOI BibTeX RDF	Heterogeneus On-Chip Interconnection Network, Chip-Multiprocessor, Energy-Efficient Architectures, Parallel Scientific Applications
25	Michela Becchi, Patrick Crowley	Dynamic thread assignment on heterogeneous multiprocessor architectures.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	simulation, chip multiprocessor, heterogeneous architectures
24	Takeshi Ogasawara	Scalability limitations when running a Java web server on a chip multiprocessor.	SYSTOR	2010	DBLP DOI BibTeX RDF	performance, multi-cores, JVMs, web servers
24	Martin Schoeberl, Peter P. Puschner, Raimund Kirner	A Single-Path Chip-Multiprocessor System.	SEUS	2009	DBLP DOI BibTeX RDF
24	Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho Ahn, Sungho Kang 0001	Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
24	Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz	Verification of chip multiprocessor memory systems using a relaxed scoreboard.	MICRO	2008	DBLP DOI BibTeX RDF
24	Xin Jin 0003, Stephen B. Furber, John V. Woods	Efficient modelling of spiking neural networks on a scalable chip multiprocessor.	IJCNN	2008	DBLP DOI BibTeX RDF
24	Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez	A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity.	IPDPS	2007	DBLP DOI BibTeX RDF
24	Hisashige Ando, Nestoras Tzartzanis, William W. Walker	A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
24	Kyriakos Stavrou, Paraskevas Evripidou, Pedro Trancoso	DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor.	SAMOS	2005	DBLP DOI BibTeX RDF
24	Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo	An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor.	DATE	2005	DBLP DOI BibTeX RDF
24	Weidong Shi, Hsien-Hsin S. Lee, Guofei Gu, Laura Falk, Trevor N. Mudge, Mrinmoy Ghosh	An Intrusion-Tolerant and Self-Recoverable Network Service System Using A Security Enhanced Chip Multiprocessor.	ICAC	2005	DBLP DOI BibTeX RDF	Intrusion-tolerant computing, survivable service, buffer overflow, self-healing, rootkits, chip multi processor
24	Seongbeom Kim, Dhruba Chandra, Yan Solihin	Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture.	IEEE PACT	2004	DBLP DOI BibTeX RDF
24	Chouki Aktouf	A Complete Strategy for Testing an On-Chip Multiprocessor Architecture.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
24	J. Robert Heath, Andrew Tan	Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF	Real-time reconfigurable architecture, analytic functional modeling, real-time testing and functional/performance verification, design, FPGA prototyping
24	Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata	An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism.	EUROMICRO	1999	DBLP DOI BibTeX RDF
23	Hyungjun Kim, Boris Grot, Paul V. Gratz, Daniel A. Jiménez	Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip.	IEEE Trans. Computers	2014	DBLP DOI BibTeX RDF
23	Francisco Triviño, José L. Sánchez 0002, Francisco J. Alfaro, José Flich	Network-on-Chip virtualization in Chip-Multiprocessor Systems.	J. Syst. Archit.	2012	DBLP DOI BibTeX RDF
23	Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh	Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP).	SBAC-PAD	2007	DBLP DOI BibTeX RDF
23	Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide	Chip size and performance evaluations of shared cache for on-chip multiprocessor.	Syst. Comput. Jpn.	2005	DBLP DOI BibTeX RDF
23	Naraig Manjikian, Huang Jin, James Reed, Nathan Cordeiro	Architecture and Implementation of Chip Multiprocessors: Custom Logic Components and Software for Rapid Prototyping.	ICPP	2004	DBLP DOI BibTeX RDF
22	Valentina Salapura	Scaling up next generation supercomputers.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	scalability of systems, chip multiprocessors (cmp), multicore, coherence protocols, blue gene
21	Jeffery A. Brown, Dean M. Tullsen	The shared-thread multiprocessor.	ICS	2008	DBLP DOI BibTeX RDF	chip multiprocessors, simultaneous multithreading
21	Mirko Loghi, Massimo Poncino, Luca Benini	Cache coherence tradeoffs in shared-memory MPSoCs.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	low power, multiprocessor, system-on-chip, Cache coherence
20	Tilman Wolf, Mark A. Franklin	Performance Models for Network Processor Design.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	Network processor design, network processor benchmark, performance model, power optimization, design optimization
20	Hangsheng Wang, Li-Shiuan Peh, Sharad Malik	Power-driven Design of Router Microarchitectures in On-chip Networks.	MICRO	2003	DBLP DOI BibTeX RDF
19	Kypros Constantinides, Onur Mutlu, Todd M. Austin	Online design bug detection: RTL analysis, flexible mechanisms, and evaluation.	MICRO	2008	DBLP DOI BibTeX RDF
19	Mahmut T. Kandemir, Ozcan Ozturk 0001, Vijay Degalahal	Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings.	VLSI Design	2007	DBLP DOI BibTeX RDF
19	Juan Chen 0001, Yong Dong, Xuejun Yang, Dan Wu	A Compiler-Directed Energy Saving Strategy for Parallelizing Applications in On-Chip Multiprocessors.	ISPDC	2005	DBLP DOI BibTeX RDF
19	Mahmut T. Kandemir, Wei Zhang 0002, Mustafa Karaköy	Runtime Code Parallelization for On-Chip Multiprocessors.	DATE	2003	DBLP DOI BibTeX RDF
18	Ahsan Shabbir, Akash Kumar 0001, Bart Mesman, Henk Corporaal	Enabling MPSoC Design Space Exploration on FPGAs.	IMTIC	2008	DBLP DOI BibTeX RDF	FPGAs, MPSoC, FIFO, FSL
18	Yurong Chen 0001, Ying Tan, Yimin Zhang 0002, Carole Dulong	Performance Analysis of Two Parallel Game-Tree Search Applications.	PARA	2006	DBLP DOI BibTeX RDF
18	Martin Karlsson, Kevin E. Moore, Erik Hagersten, David A. Wood 0001	Memory System Behavior of Java-Based Middleware.	HPCA	2003	DBLP DOI BibTeX RDF
18	Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara	Coarse-Grain Task Parallel Processing Using the OpenMP Backend of the OSCAR Multigrain Parallelizing Compiler.	ISHPC	2000	DBLP DOI BibTeX RDF
17	Xiaorui Wang, Kai Ma, Yefu Wang	Adaptive Power Control with Online Model Estimation for Chip Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	2011	DBLP DOI BibTeX RDF	power capping, cache resizing, online model estimation, chip multiprocessor, Power control, feedback control
17	Omer Khan, Sandip Kundu	Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors.	IEEE Trans. Dependable Secur. Comput.	2011	DBLP DOI BibTeX RDF	hard error detection, isolation and tolerance, Chip Multiprocessor (CMP), hardware/software codesign
17	Taecheol Oh, Kiyeon Lee, Sangyeun Cho	An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing.	MASCOTS	2011	DBLP DOI BibTeX RDF	simulation, performance modeling, Chip multiprocessor (CMP), resource sharing
17	Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström	Implications of Merging Phases on Scalability of Multi-core Architectures.	ICPP	2011	DBLP DOI BibTeX RDF	Redcution operations, Chip Multiprocessor, Amdahl's Law
17	Omer Khan, Sandip Kundu	Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	hard-error tolerance, virtualization, Chip multiprocessor (CMP), hardware/software codesign, hypervisor
17	Hyunjin Lee, Sangyeun Cho, Bruce R. Childers	PERFECTORY: A Fault-Tolerant Directory Memory Architecture.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	chip yield, lifetime reliability, Chip multiprocessor, cache coherence
17	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Tiled chip multiprocessor, heterogeneous on-chip interconnection network, cache coherence protocol, energy-efficient architectures, parallel scientific applications
17	Harold Ishebabi, Christophe Bobda	Heuristics for Flexible CMP Synthesis.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	chip multiprocessor systems, parallel programs, Reconfigurable computing
17	Antonio Flores, Juan L. Aragón, Manuel E. Acacio	Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects.	PDP	2010	DBLP DOI BibTeX RDF	tiled chip-multiprocessor, heterogeneous on-chip interconnection network, prefetching, energy-efficient architectures, parallel scientific applications
17	Chao Wang 0058, Bin Xie 0002, Jiexiang Kang, Tianzhou Chen, Wei Hu 0001, Zhenwei Zheng	On-Chip Operating System Design for NoC-Based CMP.	CIT	2010	DBLP DOI BibTeX RDF	operating system, network on chip, chip multiprocessor
17	Dan Gibson, David A. Wood 0001	Forwardflow: a scalable core for power-constrained CMPs.	ISCA	2010	DBLP DOI BibTeX RDF	scalable core, chip multiprocessor (cmp), power
17	Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	Understanding sources of inefficiency in general-purpose chips.	ISCA	2010	DBLP DOI BibTeX RDF	tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance
17	Muhammad Mukaram Khan, Javier Navaridas, Alexander D. Rast, Xin Jin 0003, Luis A. Plana, Mikel Luján, John V. Woods, José Miguel-Alonso, Steve B. Furber	Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric.	ISPDC	2009	DBLP DOI BibTeX RDF	Multi-CMP Configuration, Neural Networks, Fault-tolerance, Embedded Systems, Chip Multiprocessor, Real-time Application, Massively Parallel Computing