|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 526 occurrences of 280 keywords
|
|
|
Results
Found 503 publication records. Showing 503 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
53 | Satoshi Matsushita |
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 103-108, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading |
51 | Michael Gschwind |
The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 35(3), pp. 233-262, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
compute-transfer parallelism, multi-level application parallelism, Chip multiprocessor, Cell Broadband Engine, heterogeneous chip multiprocessor |
50 | Hiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro |
FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 178-183, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
secure mobile terminal, chip multiprocessor, linux |
48 | Slo-Li Chu |
Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 20th International Workshop, LCPC 2007, Urbana, IL, USA, October 11-13, 2007, Revised Selected Papers, pp. 261-275, 2007, Springer, 978-3-540-85260-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Critical Block Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory |
45 | Sebastian Herbert, Diana Marculescu |
Characterizing chip-multiprocessor variability-tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 313-318, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
frequency islands, chip-multiprocessor, process variability |
45 | Slo-Li Chu |
Toward to Utilize the Heterogeneous Multiple Processors of the Chip Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference, EUC 2007, Taipei, Taiwan, December 17-20, 2007, Proceedings, pp. 234-246, 2007, Springer, 978-3-540-77091-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Swing Scheduling, Octans, Chip Multiprocessor (CMP), Processor-in-Memory |
45 | Taeho Kgil, Shaun D'Souza, Ali G. Saidi, Nathan L. Binkert, Ronald G. Dreslinski, Trevor N. Mudge, Steven K. Reinhardt, Krisztián Flautner |
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 117-128, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
3D stacking technology, tier 1 server, web/file/streaming server, low power, chip multiprocessor, full-system simulation |
45 | Lucian Codrescu, D. Scott Wills, James D. Meindl |
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(1), pp. 67-82, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Thread speculation, multiscalar, parallelization, chip-multiprocessor, multithreading, value prediction |
43 | Kyriakos Stavrou, Pedro Trancoso, Paraskevas Evripidou |
Hardware Budget and Runtime System for Data-Driven Multithreaded Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 244-259, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Xi Zhang 0008, Dongsheng Wang 0002, Yibo Xue, Haixia Wang 0001, Jinglei Wang |
A Novel Cache Organization for Tiled Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 41-53, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Multi-level Directory, Chip Multiprocessor(CMP), Cache Organization, Tiled Architecture |
42 | Magnus Jahre, Lasse Natvig |
A light-weight fairness mechanism for chip multiprocessor memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 6th Conference on Computing Frontiers, 2009, Ischia, Italy, May 18-20, 2009, pp. 1-10, 2009, ACM, 978-1-60558-413-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic miss handling architecture, miss status holding register, fairness, chip multiprocessor, interference, mechanism |
42 | Hiroaki Inoue, Junji Sakai, Sunao Torii, Masato Edahiro |
FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(1), pp. 1:1-1:16, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Secure mobile terminal, chip multiprocessor, SELinux |
42 | Yi-Neng Lin, Ying-Dar Lin, Yuan-Cheng Lai |
Thread Allocation in Chip Multiprocessor Based Multithreaded Network Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: 22nd International Conference on Advanced Information Networking and Applications, AINA 2008, GinoWan, Okinawa, Japan, March 25-28, 2008, pp. 718-725, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
thread allocation, simulation, modeling, Petri net, chip multiprocessor |
42 | Li Yang 0001, Lu Peng 0001 |
SecCMP: a secure chip-multiprocessor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASID ![In: Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, ASID 2006, San Jose, California, USA, October 21, 2006, pp. 72-76, 2006, ACM, 1-59593-576-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
security, fault-tolerance, encryption, chip-multiprocessor |
42 | Peter G. Sassone, D. Scott Wills |
Scaling Up the Atlas Chip-Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(1), pp. 82-87, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Dynamic multithreading, chip-multiprocessor, scaling |
42 | Mladen Nikitovic, Mats Brorsson |
An adaptive chip-multiprocessor architecture for future mobile terminals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 43-49, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
chip-multiprocessor (CMP), power consumption, mobile terminals, energy-aware scheduling |
41 | Ozcan Ozturk 0001, Guangyu Chen, Mahmut T. Kandemir |
Multi-compilation: capturing interactions among concurrently-executing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 157-170, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multi-compilation, compiler, chip multiprocessor |
40 | Akira Yamawaki 0002, Masahiko Iwane |
Coherence Maintenances to realize an efficient parallel processing for a Cache Memory with Synchronization on a Chip-Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 8th International Symposium on Parallel Architectures, Algorithms, and Networks, ISPAN 2005, December 7-9. 2005, Las Vegas, Nevada, USA, pp. 324-333, 2005, IEEE Computer Society, 0-7695-2509-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi |
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 25-30, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Masafumi Takahashi, Hiroyuki Takano, Emi Kaneko, Seigo Suzuki |
A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Second International Symposium on High-Performance Computer Architecture, San Jose, CA, USA, February 3-7, 1996, pp. 314-322, 1996, IEEE Computer Society, 0-8186-7237-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
37 | Raphael Fonte Boa, Dulcinéia Oliveira da Penha, Alexandre Marques Amaral, Márcio Oliveira Soares de Souza, Carlos Augusto Paiva da Silva Martins, Petr Yakovlevitch Ekel |
RCMP: A Reconfigurable Chip-Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA Workshops ![In: Frontiers of High Performance Computing and Networking - ISPA 2006 Workshops, ISPA 2006 International Workshops, FHPCN, XHPC, S-GRACE, GridGIS, HPC-GTP, PDCE, ParDMCom, WOMP, ISDF, and UPWN, Sorrento, Italy, December 4-7, 2006, Proceedings, pp. 94-103, 2006, Springer, 3-540-49860-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Kenneth G. Wilson, Kunyung Chang |
The Case for a Single-Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VII Proceedings - Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, USA, October 1-5, 1996., pp. 2-11, 1996, ACM Press, 0-89791-767-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
36 | Mainak Chaudhuri |
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 227-238, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Vincent W. Freeh, Tyler K. Bletsch, Freeman L. Rawson III |
Scaling and Packing on a Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-8, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Degui Feng, Guanjun Jiang, Tiefei Zhang, Wei Hu 0001, Tianzhou Chen, Mingteng Cao |
SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 67-81, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
synchronization, Chip multiprocessor, transactional memory, scratchpad memory |
34 | Wan-Yu Lee, Iris Hui-Ru Jiang |
VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 39-44, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
chip-multiprocessor, process variation, monte carlo analysis |
34 | Long Zheng 0001, Mianxiong Dong, Song Guo 0001, Minyi Guo, Li Li 0012 |
I-Cache Tag Reduction for Low Power Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2009, Chengdu, Sichuan, China, 10-12 August 2009, pp. 196-202, 2009, IEEE Computer Society, 978-0-7695-3747-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
tag reduction, chip multiprocessor, energy saving |
34 | Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003 |
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 52-61, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ia32, on-chip integration, chip multiprocessor, heterogeneous |
34 | Christof Pitter |
Time-predictable memory arbitration for a Java chip-multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JTRES ![In: Proceedings of the 6th International Workshop on Java Technologies for Real-time and Embedded Systems, JTRES 2008, 24-26 September 2008, Santa Clara, California, USA, pp. 115-122, 2008, ACM, 978-1-60558-337-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Java, chip-multiprocessor, shared memory, worst-case execution time |
34 | Venkata Krishnan, Josep Torrellas |
A Chip-Multiprocessor Architecture with Speculative Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(9), pp. 866-880, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Chip-multiprocessor, speculative multithreading, data-dependence speculation, control speculation |
33 | Mainak Chaudhuri |
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 401-412, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
chip-multiprocessor, replacement policy, last-level cache |
32 | Lucian Codrescu, D. Scott Wills |
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 428-435, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | Pedro Trancoso, Paraskevas Evripidou, Kyriakos Stavrou, Costas Kyriacou |
A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 34(3), pp. 213-235, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
data-driven execution, parallel processing, Chip multiprocessor, multithreading |
31 | Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi |
Designing On-Chip Network Based on Optimal Latency Criteria. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, Second International Conference, ICESS 2005, Xi'an, China, December 16-18, 2005, Proceedings, pp. 287-298, 2005, Springer, 3-540-30881-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Philip Machanick |
Design principles for a virtual multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAICSIT ![In: Proceedings of the 2007 Annual Conference of the South African Institute of Computer Scientists and Information Technologists on IT Research in Developing Countries, SAICSIT 2007, Port Elizabeth, South Africa, October 2-3, 2007, pp. 76-82, 2007, ACM, 978-1-59593-775-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
chip multiprocessor, instruction-level parallelism |
30 | Jugash Chandarlapati, Mainak Chaudhuri |
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 423-430, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Haixia Wang 0001, Dongsheng Wang 0002, Peng Li 0031 |
Acceleration Techniques for Chip-Multiprocessor Simulator Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 509-515, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Wenbin Yao, Dongsheng Wang 0002, Weimin Zheng |
A Fault-Tolerant Single-Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings, pp. 137-145, 2004, Springer, 3-540-23003-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Magnus Ekman, Per Stenström |
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 32nd International Conference on Parallel Processing (ICPP 2003), 6-9 October 2003, Kaohsiung, Taiwan, pp. 359-368, 2003, IEEE Computer Society, 0-7695-2017-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert 0001 |
GigaNetIC - A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2006, 19th International Conference, Frankfurt/Main, Germany, March 13-16, 2006, Proceedings, pp. 268-282, 2006, Springer, 3-540-32765-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Mohamed M. Zahran |
On cache memory hierarchy for Chip-Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 31(1), pp. 39-48, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Markus Rudack, Dirk Niggemeyer |
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 31-39, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Lance Hammond, Mark Willey, Kunle Olukotun |
Data Speculation Support for a Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 58-69, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
28 | Liping Xue, Mahmut T. Kandemir, Guangyu Chen, Taylan Yemliha |
SPM Conscious Loop Scheduling for Embedded Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS (1) ![In: 12th International Conference on Parallel and Distributed Systems, ICPADS 2006, Minneapolis, Minnesota, USA, July 12-15, 2006, pp. 391-400, 2006, IEEE Computer Society, 0-7695-2612-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SPM (Scratch-Pad Memory), dynamic loop scheduling, parallelization, compiler, CMP (chip multiprocessor), data locality |
28 | Michael Gschwind |
Chip multiprocessing and the cell broadband engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 1-8, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
compute-transfer parallelism (CTP), cell broadband engine, memory-level parallelism (MLP), chip multiprocessing, heterogeneous chip multiprocessor |
28 | Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Ozcan Ozturk 0001, Mustafa Karaköy, Ugur Sezer |
Optimizing Array-Intensive Applications for On-Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(5), pp. 396-411, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
On-chip multiprocessor, adaptive loop parallelization, embedded systems, energy consumption, integer linear programming, constrained optimization |
28 | Jaehyuk Huh 0001, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler |
A NUCA substrate for flexible CMP cache sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 19th Annual International Conference on Supercomputing, ICS 2005, Cambridge, Massachusetts, USA, June 20-22, 2005, pp. 31-40, 2005, ACM, 1-59593-167-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
cache sharing, non-uniform cache architecture, chip-multiprocessor |
28 | Shuichi Sakai |
CMP on SoC: Architect's View. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 101-102, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
CMP (Chip Multiprocessor), I/O centric, SoC (System on Chip), parallel processing, dependability |
28 | Venkata Krishnan, Josep Torrellas |
The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 24-33, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
register communication, Chip-multiprocessor, speculative multithreading, data-dependence speculation |
27 | Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi |
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 499-504, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Francisco J. Villa, Manuel E. Acacio, José M. García 0001 |
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: High Performance Computing and Communications, First International Conference, HPCC 2005, Sorrento, Italy, September 21-23, 2005, Proceedings, pp. 213-222, 2005, Springer, 3-540-29031-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Minoru Fujishima, Masahiro Shimura |
On-chip high-speed solver of inverse problems based on quantum-computing principle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Viktor K. Prasanna |
Performance of On-Chip Multiprocessors for Vision Tasks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 242-249, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Antonio Flores, Juan L. Aragón, Manuel E. Acacio |
Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2007, 14th International Conference, Goa, India, December 18-21, 2007, Proceedings, pp. 133-146, 2007, Springer, 978-3-540-77219-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Heterogeneus On-Chip Interconnection Network, Chip-Multiprocessor, Energy-Efficient Architectures, Parallel Scientific Applications |
25 | Michela Becchi, Patrick Crowley |
Dynamic thread assignment on heterogeneous multiprocessor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 29-40, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
simulation, chip multiprocessor, heterogeneous architectures |
24 | Takeshi Ogasawara |
Scalability limitations when running a Java web server on a chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYSTOR ![In: Proceedings of of SYSTOR 2010: The 3rd Annual Haifa Experimental Systems Conference, Haifa, Israel, May 24-26, 2010, 2010, ACM, 978-1-60558-908-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance, multi-cores, JVMs, web servers |
24 | Martin Schoeberl, Peter P. Puschner, Raimund Kirner |
A Single-Path Chip-Multiprocessor System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEUS ![In: Software Technologies for Embedded and Ubiquitous Systems, 7th IFIP WG 10.2 International Workshop, SEUS 2009, Newport Beach, CA, USA, November 16-18, 2009, Proceedings, pp. 47-57, 2009, Springer, 978-3-642-10264-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho Ahn, Sungho Kang 0001 |
Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 2088-2092, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz |
Verification of chip multiprocessor memory systems using a relaxed scoreboard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 294-305, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Xin Jin 0003, Stephen B. Furber, John V. Woods |
Efficient modelling of spiking neural networks on a scalable chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2008, part of the IEEE World Congress on Computational Intelligence, WCCI 2008, Hong Kong, China, June 1-6, 2008, pp. 2812-2819, 2008, IEEE, 978-1-4244-1820-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez |
A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-6, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Hisashige Ando, Nestoras Tzartzanis, William W. Walker |
A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(7), pp. 865-868, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Kyriakos Stavrou, Paraskevas Evripidou, Pedro Trancoso |
DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings, pp. 364-373, 2005, Springer, 3-540-26969-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo |
An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 468-473, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Weidong Shi, Hsien-Hsin S. Lee, Guofei Gu, Laura Falk, Trevor N. Mudge, Mrinmoy Ghosh |
An Intrusion-Tolerant and Self-Recoverable Network Service System Using A Security Enhanced Chip Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAC ![In: Second International Conference on Autonomic Computing (ICAC 2005), 13-16 June 2005, Seattle, WA, USA, pp. 263-273, 2005, IEEE Computer Society, 0-7695-2276-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Intrusion-tolerant computing, survivable service, buffer overflow, self-healing, rootkits, chip multi processor |
24 | Seongbeom Kim, Dhruba Chandra, Yan Solihin |
Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September - 3 October 2004, Antibes Juan-les-Pins, France, pp. 111-122, 2004, IEEE Computer Society, 0-7695-2229-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Chouki Aktouf |
A Complete Strategy for Testing an On-Chip Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(1), pp. 18-28, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | J. Robert Heath, Andrew Tan |
Modeling, Design, Virtual and Physical Prototyping, Testing, and Verification of a Multifunctional Processor Queue for a Single-Chip Multiprocessor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 25-27 June 2001, Monterey, CA, USA, pp. 128-135, 2001, IEEE Computer Society, 0-7695-1206-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Real-time reconfigurable architecture, analytic functional modeling, real-time testing and functional/performance verification, design, FPGA prototyping |
24 | Ryotaro Kobayashi, Yukihiro Ogawa, Hideki Ando, Toshio Shimada, Mitsuaki Iwata |
An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1432-1440, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Hyungjun Kim, Boris Grot, Paul V. Gratz, Daniel A. Jiménez |
Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 63(3), pp. 543-556, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Francisco Triviño, José L. Sánchez 0002, Francisco J. Alfaro, José Flich |
Network-on-Chip virtualization in Chip-Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 58(3-4), pp. 126-139, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh |
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 24-27 October 2007, Gramado, RS, Brazil, pp. 211-218, 2007, IEEE Computer Society, 0-7695-3014-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide |
Chip size and performance evaluations of shared cache for on-chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 36(9), pp. 1-13, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Naraig Manjikian, Huang Jin, James Reed, Nathan Cordeiro |
Architecture and Implementation of Chip Multiprocessors: Custom Logic Components and Software for Rapid Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 33rd International Conference on Parallel Processing (ICPP 2004), 15-18 August 2004, Montreal, Quebec, Canada, pp. 483-492, 2004, IEEE Computer Society, 0-7695-2197-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Valentina Salapura |
Scaling up next generation supercomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008, pp. 1-2, 2008, ACM, 978-1-60558-077-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
scalability of systems, chip multiprocessors (cmp), multicore, coherence protocols, blue gene |
21 | Jeffery A. Brown, Dean M. Tullsen |
The shared-thread multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 73-82, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
chip multiprocessors, simultaneous multithreading |
21 | Mirko Loghi, Massimo Poncino, Luca Benini |
Cache coherence tradeoffs in shared-memory MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(2), pp. 383-407, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low power, multiprocessor, system-on-chip, Cache coherence |
20 | Tilman Wolf, Mark A. Franklin |
Performance Models for Network Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 17(6), pp. 548-561, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Network processor design, network processor benchmark, performance model, power optimization, design optimization |
20 | Hangsheng Wang, Li-Shiuan Peh, Sharad Malik |
Power-driven Design of Router Microarchitectures in On-chip Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 105-116, 2003, IEEE Computer Society, 0-7695-2043-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Kypros Constantinides, Onur Mutlu, Todd M. Austin |
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 282-293, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Mahmut T. Kandemir, Ozcan Ozturk 0001, Vijay Degalahal |
Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 227-232, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Juan Chen 0001, Yong Dong, Xuejun Yang, Dan Wu |
A Compiler-Directed Energy Saving Strategy for Parallelizing Applications in On-Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPDC ![In: 4th International Symposium on Parallel and Distributed Computing (ISPDC 2005), 4-6 July 2005, Lille, France, pp. 147-154, 2005, IEEE Computer Society, 0-7695-2434-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Mahmut T. Kandemir, Wei Zhang 0002, Mustafa Karaköy |
Runtime Code Parallelization for On-Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10510-10515, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Ahsan Shabbir, Akash Kumar 0001, Bart Mesman, Henk Corporaal |
Enabling MPSoC Design Space Exploration on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMTIC ![In: Wireless Networks, Information Processing and Systems, International Multi Topic Conference, IMTIC 2008, Jamshoro, Pakistan, April 11-12, 2008, Revised Selected Papers, pp. 412-421, 2008, Springer, 978-3-540-89852-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGAs, MPSoC, FIFO, FSL |
18 | Yurong Chen 0001, Ying Tan, Yimin Zhang 0002, Carole Dulong |
Performance Analysis of Two Parallel Game-Tree Search Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARA ![In: Applied Parallel Computing. State of the Art in Scientific Computing, 8th International Workshop, PARA 2006, Umeå, Sweden, June 18-21, 2006, Revised Selected Papers, pp. 1105-1114, 2006, Springer, 978-3-540-75754-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Martin Karlsson, Kevin E. Moore, Erik Hagersten, David A. Wood 0001 |
Memory System Behavior of Java-Based Middleware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), Anaheim, California, USA, February 8-12, 2003, pp. 217-228, 2003, IEEE Computer Society, 0-7695-1871-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Kazuhisa Ishizaka, Motoki Obata, Hironori Kasahara |
Coarse-Grain Task Parallel Processing Using the OpenMP Backend of the OSCAR Multigrain Parallelizing Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000. Proceedings, pp. 457-470, 2000, Springer, 3-540-41128-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Xiaorui Wang, Kai Ma, Yefu Wang |
Adaptive Power Control with Online Model Estimation for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 22(10), pp. 1681-1696, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
power capping, cache resizing, online model estimation, chip multiprocessor, Power control, feedback control |
17 | Omer Khan, Sandip Kundu |
Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Dependable Secur. Comput. ![In: IEEE Trans. Dependable Secur. Comput. 8(5), pp. 714-727, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
hard error detection, isolation and tolerance, Chip Multiprocessor (CMP), hardware/software codesign |
17 | Taecheol Oh, Kiyeon Lee, Sangyeun Cho |
An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 2011, 19th Annual IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, Singapore, 25-27 July, 2011, pp. 150-158, 2011, IEEE Computer Society, 978-1-4577-0468-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
simulation, performance modeling, Chip multiprocessor (CMP), resource sharing |
17 | Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström |
Implications of Merging Phases on Scalability of Multi-core Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: International Conference on Parallel Processing, ICPP 2011, Taipei, Taiwan, September 13-16, 2011, pp. 622-631, 2011, IEEE Computer Society, 978-1-4577-1336-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Redcution operations, Chip Multiprocessor, Amdahl's Law |
17 | Omer Khan, Sandip Kundu |
Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(5), pp. 651-665, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
hard-error tolerance, virtualization, Chip multiprocessor (CMP), hardware/software codesign, hypervisor |
17 | Hyunjin Lee, Sangyeun Cho, Bruce R. Childers |
PERFECTORY: A Fault-Tolerant Directory Memory Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(5), pp. 638-650, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
chip yield, lifetime reliability, Chip multiprocessor, cache coherence |
17 | Antonio Flores, Juan L. Aragón, Manuel E. Acacio |
Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(1), pp. 16-28, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Tiled chip multiprocessor, heterogeneous on-chip interconnection network, cache coherence protocol, energy-efficient architectures, parallel scientific applications |
17 | Harold Ishebabi, Christophe Bobda |
Heuristics for Flexible CMP Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(8), pp. 1091-1104, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
chip multiprocessor systems, parallel programs, Reconfigurable computing |
17 | Antonio Flores, Juan L. Aragón, Manuel E. Acacio |
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: Proceedings of the 18th Euromicro Conference on Parallel, Distributed and Network-based Processing, PDP 2010, Pisa, Italy, February 17-19, 2010, pp. 147-154, 2010, IEEE Computer Society, 978-0-7695-3939-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
tiled chip-multiprocessor, heterogeneous on-chip interconnection network, prefetching, energy-efficient architectures, parallel scientific applications |
17 | Chao Wang 0058, Bin Xie 0002, Jiexiang Kang, Tianzhou Chen, Wei Hu 0001, Zhenwei Zheng |
On-Chip Operating System Design for NoC-Based CMP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010, pp. 163-170, 2010, IEEE Computer Society, 978-0-7695-4108-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
operating system, network on chip, chip multiprocessor |
17 | Dan Gibson, David A. Wood 0001 |
Forwardflow: a scalable core for power-constrained CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 14-25, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
scalable core, chip multiprocessor (cmp), power |
17 | Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz |
Understanding sources of inefficiency in general-purpose chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 37-47, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance |
17 | Muhammad Mukaram Khan, Javier Navaridas, Alexander D. Rast, Xin Jin 0003, Luis A. Plana, Mikel Luján, John V. Woods, José Miguel-Alonso, Steve B. Furber |
Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPDC ![In: Eighth International Symposium on Parallel and Distributed Computing, ISPDC 2009, Lisbon, Portugal, June 30-July 4 2009, pp. 54-61, 2009, IEEE Computer Society, 978-0-7695-3680-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Multi-CMP Configuration, Neural Networks, Fault-tolerance, Embedded Systems, Chip Multiprocessor, Real-time Application, Massively Parallel Computing |
Displaying result #1 - #100 of 503 (100 per page; Change: ) Pages: [ 1][ 2][ 3][ 4][ 5][ 6][ >>] |
|