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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 57 occurrences of 51 keywords
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Results
Found 429 publication records. Showing 429 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
42 | Octavian Petre, Hans G. Kerkhoff |
On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 122-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Jyh-Horng Wen, Hsi-Chou Hsu |
Adaptive Filter for Delay Line Combination (DLC) Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CNSR ![In: Sixth Annual Conference on Communication Networks and Services Research (CNSR 2008), 5-8 May 2008, Halifax, Nova Scotia, Canada, pp. 410-414, 2008, IEEE Computer Society, 978-0-7695-3135-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
impulse radio (IR), delay line combination (DLC) receivers, ultra-wideband (UWB) |
32 | V. Ramakrishnan, Poras T. Balsara |
A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 197-202, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Time to digital converters, phase detectors, Vernier delay line, TDC |
30 | Yong Shim, Youngkwon Jo, Soo Hwan Kim, Suki Kim, Kwanjun Cho |
A register controlled delay locked loop using a TDC and a new fine delay line scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Ananta K. Majhi, Vishwani D. Agrawal |
Tutorial: Delay Fault Models and Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 364-369, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test |
29 | Masashi Imai, Takashi Nanya |
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 68-77, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Nan Lin, Wei Liu 0001, Richard J. Langley |
Performance analysis of a two-element linearly constrained minimum variance beamformer with sensor delay-line processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 2601-2604, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Chaeho Chung, Soobum Lee, Byung Man Kwak, Gawon Kim, Joungho Kim |
A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3), pp. 578-583, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Junmou Zhang, Simon R. Cooper, Andrew R. LaPietra, Michael W. Mattern, Robert M. Guidash, Eby G. Friedman |
A low power thyristor-based CMOS programmable delay element. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 769-772, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Nuno F. Paulino, M. Serrazina, João Goes, Adolfo Steiger-Garção |
Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 133-136, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Koenraad Laevens, Marc Moeneclaey, Herwig Bruneel |
Queueing analysis of a single-wavelength Fiber-Delay-Line buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Telecommun. Syst. ![In: Telecommun. Syst. 31(2-3), pp. 259-287, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Fiber delay lines, Loss heuristics, Maximum tolerable load, Generating functions, Queueing analysis, Optical buffers |
22 | Bryan Nelson, Mani Soma |
On-chip calibration technique for delay line based BIST jitter measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 944-947, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Sami Ur Rehman, Mohammad Mahdi Khafaji, Ali Ferschischi, Corrado Carta, Frank Ellinger |
A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(5), pp. 806-810, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim |
A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, CICC 1999, San Diego, CA, USA, May 16-19, 1999, pp. 299-302, 1999, IEEE, 0-7803-5443-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Ho-Ting Wu, Kai-Wei Ke, Wang-Rong Chang, Hui-Tang Lin |
A switched delay line based optical switch architecture with a bypass line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1533-1536, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Yifei Luo, Gang Chen, Kuan Zhou |
A picosecond TDC architecture for multiphase PLLs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 437-440, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
time-to-digital converter, vdl, vernier delay line, PLL, soi, tdc |
20 | Chih-Chiang Chia, Shiuh-Ku Weng, Ho-Hsuan Chang |
Using cascade time-space processing to detect multiple target signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the International Conference on Wireless Communications and Mobile Computing, IWCMC 2006, Vancouver, British Columbia, Canada, July 3-6, 2006, pp. 629-634, 2006, ACM, 1-59593-306-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
linearly constrained minimum variance (LCMV), tapped delay-line adaptive array antenna (TDL-AAA), time-space processing, ambiguity |
20 | Sandeep Dhar, Dragan Maksimovic, Bruno Kranzen |
Closed-loop adaptive voltage scaling controller for standard-cell ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 103-107, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
delay-line, variable-voltage, low-power, energy-efficient, design methodology, circuit design, standard-cell, DC-DC converter |
20 | S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta |
A single chip, pipelined, cascadable, multichannel, signal processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 150-155, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron |
20 | Christian Mehlführer, Markus Rupp |
Approximation and resampling of tapped delay line channel models with guaranteed channel properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 2869-2872, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Franklin Bien, Soumya Chandramouli, Hyoungsoo Kim, Edward Gebara, Joy Laskar |
Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 197-200, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jiun-Lang Huang |
Random Jitter Testing Using Low Tap-Count Delay Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 100-105, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
High-speed serial transmission, design-fortest, jitter testing |
19 | Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim |
A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9), pp. 1321-1337, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Jyh-Horng Wen, Hsi-Chou Hsu, Po-Wei Chen |
Parallel Signal Acquisition in Ultra-Wideband Systems with Shared Looped Delay-Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2008, Beijing, China, 19-23 May 2008, pp. 3780-3784, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Amir M. Amiri, Abdelhakim Khouas, Mounir Boukadoum |
On the Timing Uncertainty in Delay-Line-based Time Measurement Applications Targeting FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3772-3775, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | João Pedro 0001, Paulo P. Monteiro, João Pires 0001 |
Efficient optical burst-switched networks using only fiber delay line buffers for contention resolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BROADNETS ![In: Fourth International Conference on Broadband Communications, Networks and Systems, (BROADNETS 2007), 10-14 September 2007, Raleigh, North-Carolina, USA, pp. 2-11, 2007, IEEE, 978-1-4244-1432-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Vincenzo Italia, Marco Pisco, Stefania Campopiano, Andrea Cusano, Antonello Cutolo |
Chirped Fiber Bragg Grating as Electrically Tunable True Time Delay Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OpNeTec ![In: Optical Networks and Technologies, IFIP TC6 / WG6.10 First Optical Networks & Technologies Conference (OpNeTec), October 18-20, 2004, Pisa, Italy, pp. 474-480, 2004, Springer, 0-387-23177-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Hailong Li, Malvin Wei Liak Tan, Ian Li-Jin Thng, Xiaorong Li |
Fiber Delay Line-Random Early Detection QoS Scheme for Optical Burst Switching Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HSNMC ![In: High Speed Networks and Multimedia Communications, 7th IEEE International Conference, HSNMC 2004, Toulouse, France, June 30 - July 2, 2004, Proceedings, pp. 761-765, 2004, Springer, 3-540-22262-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson 0001 |
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 45-51, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Duan-Shin Lee, Cheng-Shang Chang, Jay Cheng, Horng-Sheng Yan |
Queueing Analysis of Loss Systems with Variable Optical Delay Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: INFOCOM 2008. 27th IEEE International Conference on Computer Communications, Joint Conference of the IEEE Computer and Communications Societies, 13-18 April 2008, Phoenix, AZ, USA, pp. 637-645, 2008, IEEE, 978-1-4244-2026-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Yang Chen, Zhaoyang Qiu, Xiaofei Di, Xianqing Chen, Yu-Dong Zhang 0001 |
Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 30(8), pp. 2150146:1-2150146:14, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Russell Ovans, David Murphy, Timothy Bartoo |
The Infinite Delay Line: Granulation as an In-Line Effect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMC ![In: Proceedings of the 1995 International Computer Music Conference, ICMC 1995, Banff, AB, Canada, September 3-7, 1995, 1995, Michigan Publishing. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP BibTeX RDF |
|
16 | Wenle Zhang |
On Momentum and Learning Rate of the Generalized ADLINE Neural Network for Time Varying System Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (1) ![In: Advances in Neural Networks - ISNN 2009, 6th International Symposium on Neural Networks, ISNN 2009, Wuhan, China, May 26-29, 2009, Proceedings, Part I, pp. 1002-1013, 2009, Springer, 978-3-642-01506-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Tapped delay line feedback, Neural network, System identification, ADALINE |
16 | Hong-Wei Huang, Hsin-Hsin Ho, Ke-Horng Chen, Sy-Yen Kuo |
Dithering skip modulator with a novel load sensor for ultra-wide-load high-efficiency DC-DC converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 388-393, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
delay-line chain, dithering skip modulation, load sensing circuit, switching converter |
16 | Man-Jae Yang, Goen Hoe Kim, Kang-Yoon Lee |
A Small Area Cyclic Vernier Delay Line TDC Based ADDLL using Linear Delay Inverter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 20th International SoC Design Conference, ISOCC 2023, Jeju, Republic of Korea, October 25-28, 2023, pp. 25-26, 2023, IEEE, 979-8-3503-2703-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
16 | Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim |
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 56(6), pp. 1886-1896, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
16 | Thomas Van den Dries, Hans Ingelberts, Sven Boulanger, Maarten Kuijk |
A 5 ps resolution, 8.6 ns delay range digital delay line using combinatorial redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIME ![In: 15th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2019, Lausanne, Switzerland, July 15-18, 2019, pp. 21-24, 2019, IEEE, 978-1-7281-3549-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Zheng-Hong Zhang, Wei Chu, Shi-Yu Huang |
The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019, pp. 231, 2019, ACM, 978-1-4503-6725-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Yang Chen, Wenyuan Li |
Compact and Broadband Variable True-Time Delay Line with DLL-Based Delay-Time Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 37(3), pp. 1007-1027, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Adel Rezaeian, Gholamreza Ardeshir, Mohammad Gholami |
Low-power and wide-band delay-locked loop with switching delay line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 46(12), pp. 2189-2201, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada |
A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 100-C(9), pp. 736-745, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong |
A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9), pp. 1393-1403, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Jinn-Shyan Wang, Chun-Yuan Cheng, Pei-Yuan Chou, Tzu-Yi Yang |
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(11), pp. 2635-2644, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Chia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang |
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(3), pp. 567-574, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Ahmed Galib Reza, Hyotaek Lim |
Throughput and delay performance analysis of feed-forward and feedback shared fiber delay line based hybrid buffering optical packet switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICOIN ![In: 2011 International Conference on Information Networking, ICOIN 2011, Kuala Lumpur, Malaysia, January 26-28, 2011, pp. 414-418, 2011, IEEE Computer Society, 978-1-61284-661-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
16 | Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang |
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 45(5), pp. 1036-1047, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Duan-Shin Lee, Cheng-Shang Chang, Jay Cheng, Hung-Shih Chueh, Kuan-Ting Wang |
Emulation of an Optical Flexible Delay Line by Parallel Variable Optical Delay Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Commun. Lett. ![In: IEEE Commun. Lett. 14(8), pp. 770-772, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Duan-Shin Lee, Kai-Jie Hsu, Cheng-Shang Chang, Jay Cheng |
Emulation and Approximation of a Flexible Delay Line by Parallel Non-Overtaking Delay Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INFOCOM ![In: INFOCOM 2009. 28th IEEE International Conference on Computer Communications, Joint Conference of the IEEE Computer and Communications Societies, 19-25 April 2009, Rio de Janeiro, Brazil, pp. 720-728, 2009, IEEE, 978-1-4244-3513-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Chao-Chyun Chen, Shen-Iuan Liu |
An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 43(11), pp. 2413-2421, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Federico Baronti, Diego Lunardini, Roberto Roncella, Roberto Saletti |
A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 39(2), pp. 384-387, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim |
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 35(3), pp. 377-384, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Manuel Mota, Jorgen Christiansen |
A high-resolution time interpolator based on a delay locked loop and an RC delay line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(10), pp. 1360-1366, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Cédric Majek, Yann Deval, Hervé Lapuyade, Jean-Baptiste Bégueret |
Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CMOS-SOI, factorial delay locked loop, multi-standard frequency synthesizer, quadrature phase signals, voltage controlled delay element |
15 | Hiroaki Harai, Masayuki Murata 0001 |
Optical fiber-delay-line buffer management in output-buffered photonic packet switch to support service differentiation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 24(S-8), pp. 108-116, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang |
Self-sampled vernier delay line for built-in clock jitter measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Wouter Rogiest, Koenraad Laevens, Dieter Fiems, Herwig Bruneel |
Quantifying the Impact of Wavelength Conversion on the Performance of Fiber Delay Line Buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BROADNETS ![In: 3rd International Conference on Broadband Communications, Networks, and Systems (BROADNETS 2006), 1-5 October 2006, San José, California, USA, 2006, IEEE, 978-1-4244-0425-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Frederick K. H. Lee, Peter J. McLane |
Design of nonuniformly spaced tapped-delay-line equalizers for sparse multipath channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 52(4), pp. 530-535, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu |
A mixed-mode delay-locked loop for wide-range operation and multiphase outputs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 196-199, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu, Shu-Yin Hung |
A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 90-93, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Niklas Lotze, Maurits Ortmanns, Yiannos Manoli |
A Study on self-timed asynchronous subthreshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 533-540, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Jiun-Lang Huang |
On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 387-398, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
jitter measurement, random jitter, analog/mixed-signal testing, design-for-test |
12 | Antonio A. D'Amico, Umberto Mengali |
Code-multiplexed UWB transmitted-reference radio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 56(12), pp. 2125-2132, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Jindong Liu, Harry R. Erwin, Stefan Wermter |
Mobile robot broadband sound localisation using a biologically inspired spiking neural network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems, September 22-26, 2008, Acropolis Convention Center, Nice, France, pp. 2191-2196, 2008, IEEE, 978-1-4244-2057-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
12 | Giulio Maggiore, Letterio Pirrone, Gaethan Donlap Kouang, Federico Piovan, Biagio Ricco Galluzzo |
Soip Over Satellite Testing - TIM Experience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TestCom ![In: Testing of Communicating Systems, 16th IFIP International Conerence, TestCom 2004, Oxford, UK, March 17-19, 2004, Proceedings, pp. 112-127, 2004, Springer, 3-540-21219-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Masashi Imai, Metehan Özcan, Takashi Nanya |
Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 62-71, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
12 | Xiaofeng Lin, Jin Liu 0004 |
A CMOS analog continuous-time FIR filter for 1Gbps cable equalizer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 296-299, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Cheng Jia, Linda S. Milor |
A BIST Solution for The Test of I/O Speed. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1023-1030, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
12 | Neil Barakat, Edward H. Sargent |
Separating resource reservations from service requests to improve the performance of optical burst-switching networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 24(S-4), pp. 95-107, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
12 | Luca Fanucci, Roberto Roncella, Roberto Saletti |
Non-linearity reduction technique for delay-locked delay-lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 430-433, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
10 | Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He |
A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(1), pp. 19-28, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Philipp Schulmeyer, Manfred Weihnacht, Hagen Schmidt |
A Dual-Mode Surface Acoustic Wave Delay Line for the Detection of Ice on 64°-Rotated Y-Cut Lithium Niobate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 24(7), pp. 2292, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | Rajendra Prasath Palanisamy, Luis A. Chavez, Raymond Castro, Alp T. Findikoglu |
Void-Engineered Metamaterial Delay Line with Built-In Impedance Matching for Ultrasonic Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 24(3), pp. 995, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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10 | Marco Knipfer, Stefan Meier, Tobias Volk, Jonas Heimerl, Peter Hommelhoff, Sergei Gleyzer |
Deep learning-based spatiotemporal multi-event reconstruction for delay line detectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Mach. Learn. Sci. Technol. ![In: Mach. Learn. Sci. Technol. 5(2), pp. 25019, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
10 | R. Sivaraman, D. Muralidaran, R. Muthaiah, V. S. Shankar Sriram |
Characteristic Exploitation of Programmable Delay Line Influenced Oscillator Circuit as Hardware Security Primitive. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, VLSID 2024, Kolkata, India, January 6-10, 2024, pp. 480-485, 2024, IEEE, 979-8-3503-8440-6. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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10 | Erislandy Mozo Bigñotte, Paul Unterhuber, Arrate Alonso Gómez, Stephan Sand, Mikel Mendicute Errasti |
Measurement Based Tapped Delay Line Model for Train-to-Train Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Veh. Technol. ![In: IEEE Trans. Veh. Technol. 72(4), pp. 4168-4181, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Jaewook Kim, Jaekwang Yun, Joo-Hyung Chae, Suhwan Kim |
A 50-1600 MHz Wide-Range Digital Duty-Cycle Corrector With Counter-Based Half-Cycle Delay Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 30555-30561, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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10 | Yongnu Jin, Jiancheng Sun, Liyun Dai, Peng Cai, Kyung Sup Kwak, Sang-Jo Yoo |
A Solution to the Non-Ideal Delay Line Problem in Transmitted Reference Pulse Cluster Schemes for UWB Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Internet Things J. ![In: IEEE Internet Things J. 10(2), pp. 1162-1170, January 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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10 | Ritesh Baranwal, Brij Bihari Tiwari |
Performance evaluation of FBMC versus OFDM in tapped delay line doubly selective channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Wirel. Mob. Comput. ![In: Int. J. Wirel. Mob. Comput. 24(1), pp. 1-8, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Yuan Hua, Qi Lu, Shuangmu Li, Bo Zhao, Sijun Du |
A 90.6% Efficient, 0.333 W/mm2 Power Density Direct 48V-to-1V Dual Inductor Hybrid Converter With Delay-Line-Based V2D Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(3), pp. 1014-1018, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Marco Knipfer, Stefan Meier, Jonas Heimerl, Peter Hommelhoff, Sergei Gleyzer |
Deep Learning-Based Spatiotemporal Multi-Event Reconstruction for Delay Line Detectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2306.09359, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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10 | Kai Braungardt, Axel Diewald, Benjamin Nuss, Thomas Zwick |
Optimizing the Coupling Factor of a Tapped Delay Line for Analog Radar Target Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WiSNeT ![In: 2023 IEEE Topical Conference on Wireless Sensors and Sensor Networks, Las Vegas, NV, USA, January 22-25, 2023, pp. 46-48, 2023, IEEE, 978-1-6654-9321-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Mao-Ling Chiu, I-Fang Lo, Tsung-Hsien Lin |
A Time-Domain CCM/DCM Current-Mode Buck Converter with a PI Compensator Incorporating an Infinite Phase Shift Delay Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 49th IEEE European Solid State Circuits Conference, ESSCIRC 2023, Lisbon, Portugal, September 11-14, 2023, pp. 441-444, 2023, IEEE, 979-8-3503-0420-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Rongliang Fu, Olivia Chen, Bei Yu 0001, Nobuyuki Yoshikawa, Tsung-Yi Ho |
DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer Aided Design, ICCAD 2023, San Francisco, CA, USA, October 28 - Nov. 2, 2023, pp. 1-8, 2023, IEEE, 979-8-3503-2225-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Feng Tai, Qiang Li 0021 |
Improved Dynamic Comparator With Adaptive Delay Line for the Latch Conduction and Regenerative Feedback Assisted FIA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, United Kingdom, June 26-28, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-0024-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He |
A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023, pp. 112-113, 2023, IEEE, 978-1-6654-9016-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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10 | Essam Berikaa, Md Samiul Alam, Yixiang Hu, Weijia Li, David V. Plant |
C-band 100 Gb/s Transmission over 40 km SSMF Using a Silicon Photonic Vestigial Sideband Transmitter Based on Dual-Drive MZM and Passive Optical Delay Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OFC ![In: Optical Fiber Communications Conference and Exhibition, OFC 2023, San Diego, CA, USA, March 5-9, 2023, pp. 1-3, 2023, IEEE, 978-1-957171-18-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Tian Gan, Susan Stepney, Martin A. Trefzer |
Combining Multiple Inputs to a Delay-line Reservoir Computer: Control of a Forced Van der Pol Oscillator System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: International Joint Conference on Neural Networks, IJCNN 2023, Gold Coast, Australia, June 18-23, 2023, pp. 1-7, 2023, IEEE, 978-1-6654-8867-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Jie Wu, Yubo Ma |
Implementation of time interleaved ADC based on delay line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EITCE ![In: Proceedings of the 2023 7th International Conference on Electronic Information Technology and Computer Engineering, EITCE 2023, Xiamen, China, October 20-22, 2023, pp. 504-509, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Siva Charan Nimmagadda, Hari Bilash Dubey |
Programmable Delay Line With Inherent Duty Cycle Correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, VLSID 2023, Hyderabad, India, January 8-12, 2023, pp. 81-86, 2023, IEEE, 979-8-3503-4678-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
10 | Mohmad Aasif Bhat, Imon Mondal |
A Low-Loss, Compact Wideband True-Time-Delay Line for Sub-6GHz Applications Using N - Path Filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, India, November 19-22, 2023, pp. 149-153, 2023, IEEE, 979-8-3503-8119-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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10 | Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu |
ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, India, November 19-22, 2023, pp. 100-104, 2023, IEEE, 979-8-3503-8119-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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10 | Xingyuan Tong, Jinwu Wu, Dong Chen |
Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(1), pp. 25-29, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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10 | Parth Parekh, Fei Yuan 0005, Yushi Zhou |
Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 119, pp. 105316, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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10 | Georgios Tzimpragos, Jennifer Volk, Alex Wynn, Evan Golden, Timothy Sherwood |
Pulsar: A Superconducting Delay-Line Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2205.08016, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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10 | Taiki Yamae, Naoki Takeuchi, Nobuyuki Yoshikawa |
Adiabatic Quantum-Flux-Parametron with Delay-Line Clocking Using Square Excitation Currents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 105-C(6), pp. 277-282, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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10 | Alessandra Farina, Alessandro Nicolosi, Edoardo Bonizzoni |
A Fully-Differential Delay-Line Based Control for Resonant Switched-Capacitor Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIME ![In: 17th Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2022, Villasimius, SU, Italy, June 12-15, 2022, pp. 265-268, 2022, IEEE, 978-1-6654-6700-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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10 | Mykola Servetnyk, Wei-Han Hsiao, Alisher Mukashev |
Performance Evaluation of Polarization Effects on 5G Clustered Delay Line Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACT ![In: 24th International Conference on Advanced Communication Technology, ICACT 2022, Pyeongchang, Korea, February 13-16, 2022, pp. 1-6, 2022, IEEE, 979-11-88428-08-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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10 | Zijie Wang, Jiajun Lu, José L. Núñez-Yáñez |
A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 101-108, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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10 | Yue Xu, Jie Xie, Zhiwei Xing, Wenqiang Yuan, Guanqun Yu, Zhongmin Zeng, Baoshun Zhang, Dongmin Wu |
A Bin-by-Bin Calibration with Neural Network for FPGA-Based Tapped-Delay-Line Time-to-Digital Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RCAR ![In: IEEE International Conference on Real-time Computing and Robotics, RCAR 2022, Guiyang, China, July 17-22, 2022, pp. 681-686, 2022, IEEE, 978-1-6654-6983-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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10 | Samer B. Idres, Hossein Hashemi 0001 |
Optical Binary Switched Delay Line based on Low Loss Multimode Waveguide. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OFC ![In: Optical Fiber Communications Conference and Exhibition, OFC 2022, San Diego, CA, USA, March 6-10, 2022, pp. 1-3, 2022, IEEE, 978-1-55752-466-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
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