Search results for "delay-line"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
42	Octavian Petre, Hans G. Kerkhoff	On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
35	Jyh-Horng Wen, Hsi-Chou Hsu	Adaptive Filter for Delay Line Combination (DLC) Receivers.	CNSR	2008	DBLP DOI BibTeX RDF	impulse radio (IR), delay line combination (DLC) receivers, ultra-wideband (UWB)
32	V. Ramakrishnan, Poras T. Balsara	A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter.	VLSI Design	2006	DBLP DOI BibTeX RDF	Time to digital converters, phase detectors, Vernier delay line, TDC
30	Yong Shim, Youngkwon Jo, Soo Hwan Kim, Suki Kim, Kwanjun Cho	A register controlled delay locked loop using a TDC and a new fine delay line scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
29	Ananta K. Majhi, Vishwani D. Agrawal	Tutorial: Delay Fault Models and Coverage.	VLSI Design	1998	DBLP DOI BibTeX RDF	delay fault models, gate delay model, line delay model, path delay model, segment delay model, transition model, Delay test
29	Masashi Imai, Takashi Nanya	A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations.	ASYNC	2006	DBLP DOI BibTeX RDF
25	Nan Lin, Wei Liu 0001, Richard J. Langley	Performance analysis of a two-element linearly constrained minimum variance beamformer with sensor delay-line processing.	ICASSP	2008	DBLP DOI BibTeX RDF
25	Chaeho Chung, Soobum Lee, Byung Man Kwak, Gawon Kim, Joungho Kim	A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
24	Junmou Zhang, Simon R. Cooper, Andrew R. LaPietra, Michael W. Mattern, Robert M. Guidash, Eby G. Friedman	A low power thyristor-based CMOS programmable delay element.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
24	Nuno F. Paulino, M. Serrazina, João Goes, Adolfo Steiger-Garção	Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
22	Koenraad Laevens, Marc Moeneclaey, Herwig Bruneel	Queueing analysis of a single-wavelength Fiber-Delay-Line buffer.	Telecommun. Syst.	2006	DBLP DOI BibTeX RDF	Fiber delay lines, Loss heuristics, Maximum tolerable load, Generating functions, Queueing analysis, Optical buffers
22	Bryan Nelson, Mani Soma	On-chip calibration technique for delay line based BIST jitter measurement.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
21	Sami Ur Rehman, Mohammad Mahdi Khafaji, Ali Ferschischi, Corrado Carta, Frank Ellinger	A 0.2-1.3 ns Range Delay-Control Scheme for a 25 Gb/s Data-Receiver Using a Replica Delay-Line-Based Delay-Locked-Loop in 45-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
21	Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim	A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells.	CICC	1999	DBLP DOI BibTeX RDF
21	Ho-Ting Wu, Kai-Wei Ke, Wang-Rong Chang, Hui-Tang Lin	A switched delay line based optical switch architecture with a bypass line.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
20	Yifei Luo, Gang Chen, Kuan Zhou	A picosecond TDC architecture for multiphase PLLs.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	time-to-digital converter, vdl, vernier delay line, PLL, soi, tdc
20	Chih-Chiang Chia, Shiuh-Ku Weng, Ho-Hsuan Chang	Using cascade time-space processing to detect multiple target signals.	IWCMC	2006	DBLP DOI BibTeX RDF	linearly constrained minimum variance (LCMV), tapped delay-line adaptive array antenna (TDL-AAA), time-space processing, ambiguity
20	Sandeep Dhar, Dragan Maksimovic, Bruno Kranzen	Closed-loop adaptive voltage scaling controller for standard-cell ASICs.	ISLPED	2002	DBLP DOI BibTeX RDF	delay-line, variable-voltage, low-power, energy-efficient, design methodology, circuit design, standard-cell, DC-DC converter
20	S. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta	A single chip, pipelined, cascadable, multichannel, signal processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay lines, single chip signal processor, cascadable processor, multichannel signal processor, programmable delay line, memory mapped peripheral, online diagnostics, shadow accumulators, double metal CMOS process, 144 pin CPGA, VLSI, timing, pipeline processing, digital signal processing chips, pipelined processor, CMOS digital integrated circuits, array multipliers, DSP architecture, 2 micron
20	Christian Mehlführer, Markus Rupp	Approximation and resampling of tapped delay line channel models with guaranteed channel properties.	ICASSP	2008	DBLP DOI BibTeX RDF
20	Franklin Bien, Soumya Chandramouli, Hyoungsoo Kim, Edward Gebara, Joy Laskar	Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Jiun-Lang Huang	Random Jitter Testing Using Low Tap-Count Delay Lines.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	High-speed serial transmission, design-fortest, jitter testing
19	Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim	A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
18	Jyh-Horng Wen, Hsi-Chou Hsu, Po-Wei Chen	Parallel Signal Acquisition in Ultra-Wideband Systems with Shared Looped Delay-Line.	ICC	2008	DBLP DOI BibTeX RDF
18	Amir M. Amiri, Abdelhakim Khouas, Mounir Boukadoum	On the Timing Uncertainty in Delay-Line-based Time Measurement Applications Targeting FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
18	João Pedro 0001, Paulo P. Monteiro, João Pires 0001	Efficient optical burst-switched networks using only fiber delay line buffers for contention resolution.	BROADNETS	2007	DBLP DOI BibTeX RDF
18	Vincenzo Italia, Marco Pisco, Stefania Campopiano, Andrea Cusano, Antonello Cutolo	Chirped Fiber Bragg Grating as Electrically Tunable True Time Delay Line.	OpNeTec	2004	DBLP DOI BibTeX RDF
18	Hailong Li, Malvin Wei Liak Tan, Ian Li-Jin Thng, Xiaorong Li	Fiber Delay Line-Random Early Detection QoS Scheme for Optical Burst Switching Networks.	HSNMC	2004	DBLP DOI BibTeX RDF
18	George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson 0001	An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems.	ASYNC	2000	DBLP DOI BibTeX RDF
17	Duan-Shin Lee, Cheng-Shang Chang, Jay Cheng, Horng-Sheng Yan	Queueing Analysis of Loss Systems with Variable Optical Delay Lines.	INFOCOM	2008	DBLP DOI BibTeX RDF
16	Yang Chen, Zhaoyang Qiu, Xiaofei Di, Xianqing Chen, Yu-Dong Zhang 0001	Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
16	Russell Ovans, David Murphy, Timothy Bartoo	The Infinite Delay Line: Granulation as an In-Line Effect.	ICMC	1995	DBLP BibTeX RDF
16	Wenle Zhang	On Momentum and Learning Rate of the Generalized ADLINE Neural Network for Time Varying System Identification.	ISNN (1)	2009	DBLP DOI BibTeX RDF	Tapped delay line feedback, Neural network, System identification, ADALINE
16	Hong-Wei Huang, Hsin-Hsin Ho, Ke-Horng Chen, Sy-Yen Kuo	Dithering skip modulator with a novel load sensor for ultra-wide-load high-efficiency DC-DC converters.	ISLPED	2006	DBLP DOI BibTeX RDF	delay-line chain, dithering skip modulation, load sensing circuit, switching converter
16	Man-Jae Yang, Goen Hoe Kim, Kang-Yoon Lee	A Small Area Cyclic Vernier Delay Line TDC Based ADDLL using Linear Delay Inverter.	ISOCC	2023	DBLP DOI BibTeX RDF
16	Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim	A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line.	IEEE J. Solid State Circuits	2021	DBLP DOI BibTeX RDF
16	Thomas Van den Dries, Hans Ingelberts, Sven Boulanger, Maarten Kuijk	A 5 ps resolution, 8.6 ns delay range digital delay line using combinatorial redundancy.	PRIME	2019	DBLP DOI BibTeX RDF
16	Zheng-Hong Zhang, Wei Chu, Shi-Yu Huang	The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop.	DAC	2019	DBLP DOI BibTeX RDF
16	Yang Chen, Wenyuan Li	Compact and Broadband Variable True-Time Delay Line with DLL-Based Delay-Time Control.	Circuits Syst. Signal Process.	2018	DBLP DOI BibTeX RDF
16	Adel Rezaeian, Gholamreza Ardeshir, Mohammad Gholami	Low-power and wide-band delay-locked loop with switching delay line.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
16	Tomohiko Yano, Toru Nakura, Tetsuya Iizuka, Kunihiro Asada	A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring.	IEICE Trans. Electron.	2017	DBLP DOI BibTeX RDF
16	Woo-Rham Bae, Gyu-Seob Jeong, Kwanseo Park, Sung-Yong Cho, Yoonsoo Kim, Deog-Kyoon Jeong	A 0.36 pJ/bit, 0.025 mm2, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
16	Jinn-Shyan Wang, Chun-Yuan Cheng, Pei-Yuan Chou, Tzu-Yi Yang	A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
16	Chia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang	Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
16	Ahmed Galib Reza, Hyotaek Lim	Throughput and delay performance analysis of feed-forward and feedback shared fiber delay line based hybrid buffering optical packet switch.	ICOIN	2011	DBLP DOI BibTeX RDF
16	Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang	A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
16	Duan-Shin Lee, Cheng-Shang Chang, Jay Cheng, Hung-Shih Chueh, Kuan-Ting Wang	Emulation of an Optical Flexible Delay Line by Parallel Variable Optical Delay Lines.	IEEE Commun. Lett.	2010	DBLP DOI BibTeX RDF
16	Duan-Shin Lee, Kai-Jie Hsu, Cheng-Shang Chang, Jay Cheng	Emulation and Approximation of a Flexible Delay Line by Parallel Non-Overtaking Delay Lines.	INFOCOM	2009	DBLP DOI BibTeX RDF
16	Chao-Chyun Chen, Shen-Iuan Liu	An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
16	Federico Baronti, Diego Lunardini, Roberto Roncella, Roberto Saletti	A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
16	Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim	An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
16	Manuel Mota, Jorgen Christiansen	A high-resolution time interpolator based on a delay locked loop and an RC delay line.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
15	Cédric Majek, Yann Deval, Hervé Lapuyade, Jean-Baptiste Bégueret	Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS-SOI, factorial delay locked loop, multi-standard frequency synthesizer, quadrature phase signals, voltage controlled delay element
15	Hiroaki Harai, Masayuki Murata 0001	Optical fiber-delay-line buffer management in output-buffered photonic packet switch to support service differentiation.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
15	Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang	Self-sampled vernier delay line for built-in clock jitter measurement.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Wouter Rogiest, Koenraad Laevens, Dieter Fiems, Herwig Bruneel	Quantifying the Impact of Wavelength Conversion on the Performance of Fiber Delay Line Buffers.	BROADNETS	2006	DBLP DOI BibTeX RDF
15	Frederick K. H. Lee, Peter J. McLane	Design of nonuniformly spaced tapped-delay-line equalizers for sparse multipath channels.	IEEE Trans. Commun.	2004	DBLP DOI BibTeX RDF
14	Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu	A mixed-mode delay-locked loop for wide-range operation and multiphase outputs.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
14	Kuo-Hsing Cheng, Yu-Lung Lo, Wen Fang Yu, Shu-Yin Hung	A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation.	IWSOC	2003	DBLP DOI BibTeX RDF
14	Niklas Lotze, Maurits Ortmanns, Yiannos Manoli	A Study on self-timed asynchronous subthreshold logic.	ICCD	2007	DBLP DOI BibTeX RDF
14	Jiun-Lang Huang	On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	jitter measurement, random jitter, analog/mixed-signal testing, design-for-test
12	Antonio A. D'Amico, Umberto Mengali	Code-multiplexed UWB transmitted-reference radio.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
12	Jindong Liu, Harry R. Erwin, Stefan Wermter	Mobile robot broadband sound localisation using a biologically inspired spiking neural network.	IROS	2008	DBLP DOI BibTeX RDF
12	Giulio Maggiore, Letterio Pirrone, Gaethan Donlap Kouang, Federico Piovan, Biagio Ricco Galluzzo	Soip Over Satellite Testing - TIM Experience.	TestCom	2004	DBLP DOI BibTeX RDF
12	Masashi Imai, Metehan Özcan, Takashi Nanya	Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model.	ASYNC	2004	DBLP DOI BibTeX RDF
12	Xiaofeng Lin, Jin Liu 0004	A CMOS analog continuous-time FIR filter for 1Gbps cable equalizer.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
12	Cheng Jia, Linda S. Milor	A BIST Solution for The Test of I/O Speed.	ITC	2003	DBLP DOI BibTeX RDF
12	Neil Barakat, Edward H. Sargent	Separating resource reservations from service requests to improve the performance of optical burst-switching networks.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
12	Luca Fanucci, Roberto Roncella, Roberto Saletti	Non-linearity reduction technique for delay-locked delay-lines.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
10	Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He	A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
10	Philipp Schulmeyer, Manfred Weihnacht, Hagen Schmidt	A Dual-Mode Surface Acoustic Wave Delay Line for the Detection of Ice on 64°-Rotated Y-Cut Lithium Niobate.	Sensors	2024	DBLP DOI BibTeX RDF
10	Rajendra Prasath Palanisamy, Luis A. Chavez, Raymond Castro, Alp T. Findikoglu	Void-Engineered Metamaterial Delay Line with Built-In Impedance Matching for Ultrasonic Applications.	Sensors	2024	DBLP DOI BibTeX RDF
10	Marco Knipfer, Stefan Meier, Tobias Volk, Jonas Heimerl, Peter Hommelhoff, Sergei Gleyzer	Deep learning-based spatiotemporal multi-event reconstruction for delay line detectors.	Mach. Learn. Sci. Technol.	2024	DBLP DOI BibTeX RDF
10	R. Sivaraman, D. Muralidaran, R. Muthaiah, V. S. Shankar Sriram	Characteristic Exploitation of Programmable Delay Line Influenced Oscillator Circuit as Hardware Security Primitive.	VLSID	2024	DBLP DOI BibTeX RDF
10	Erislandy Mozo Bigñotte, Paul Unterhuber, Arrate Alonso Gómez, Stephan Sand, Mikel Mendicute Errasti	Measurement Based Tapped Delay Line Model for Train-to-Train Communications.	IEEE Trans. Veh. Technol.	2023	DBLP DOI BibTeX RDF
10	Jaewook Kim, Jaekwang Yun, Joo-Hyung Chae, Suhwan Kim	A 50-1600 MHz Wide-Range Digital Duty-Cycle Corrector With Counter-Based Half-Cycle Delay Line.	IEEE Access	2023	DBLP DOI BibTeX RDF
10	Yongnu Jin, Jiancheng Sun, Liyun Dai, Peng Cai, Kyung Sup Kwak, Sang-Jo Yoo	A Solution to the Non-Ideal Delay Line Problem in Transmitted Reference Pulse Cluster Schemes for UWB Communications.	IEEE Internet Things J.	2023	DBLP DOI BibTeX RDF
10	Ritesh Baranwal, Brij Bihari Tiwari	Performance evaluation of FBMC versus OFDM in tapped delay line doubly selective channels.	Int. J. Wirel. Mob. Comput.	2023	DBLP DOI BibTeX RDF
10	Yuan Hua, Qi Lu, Shuangmu Li, Bo Zhao, Sijun Du	A 90.6% Efficient, 0.333 W/mm2 Power Density Direct 48V-to-1V Dual Inductor Hybrid Converter With Delay-Line-Based V2D Controller.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
10	Marco Knipfer, Stefan Meier, Jonas Heimerl, Peter Hommelhoff, Sergei Gleyzer	Deep Learning-Based Spatiotemporal Multi-Event Reconstruction for Delay Line Detectors.	CoRR	2023	DBLP DOI BibTeX RDF
10	Kai Braungardt, Axel Diewald, Benjamin Nuss, Thomas Zwick	Optimizing the Coupling Factor of a Tapped Delay Line for Analog Radar Target Simulation.	WiSNeT	2023	DBLP DOI BibTeX RDF
10	Mao-Ling Chiu, I-Fang Lo, Tsung-Hsien Lin	A Time-Domain CCM/DCM Current-Mode Buck Converter with a PI Compensator Incorporating an Infinite Phase Shift Delay Line.	ESSCIRC	2023	DBLP DOI BibTeX RDF
10	Rongliang Fu, Olivia Chen, Bei Yu 0001, Nobuyuki Yoshikawa, Tsung-Yi Ho	DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits.	ICCAD	2023	DBLP DOI BibTeX RDF
10	Feng Tai, Qiang Li 0021	Improved Dynamic Comparator With Adaptive Delay Line for the Latch Conduction and Regenerative Feedback Assisted FIA.	NEWCAS	2023	DBLP DOI BibTeX RDF
10	Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He	A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS.	ISSCC	2023	DBLP DOI BibTeX RDF
10	Essam Berikaa, Md Samiul Alam, Yixiang Hu, Weijia Li, David V. Plant	C-band 100 Gb/s Transmission over 40 km SSMF Using a Silicon Photonic Vestigial Sideband Transmitter Based on Dual-Drive MZM and Passive Optical Delay Line.	OFC	2023	DBLP DOI BibTeX RDF
10	Tian Gan, Susan Stepney, Martin A. Trefzer	Combining Multiple Inputs to a Delay-line Reservoir Computer: Control of a Forced Van der Pol Oscillator System.	IJCNN	2023	DBLP DOI BibTeX RDF
10	Jie Wu, Yubo Ma	Implementation of time interleaved ADC based on delay line.	EITCE	2023	DBLP DOI BibTeX RDF
10	Siva Charan Nimmagadda, Hari Bilash Dubey	Programmable Delay Line With Inherent Duty Cycle Correction.	VLSID	2023	DBLP DOI BibTeX RDF
10	Mohmad Aasif Bhat, Imon Mondal	A Low-Loss, Compact Wideband True-Time-Delay Line for Sub-6GHz Applications Using N - Path Filters.	APCCAS	2023	DBLP DOI BibTeX RDF
10	Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu	ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications.	APCCAS	2023	DBLP DOI BibTeX RDF
10	Xingyuan Tong, Jinwu Wu, Dong Chen	Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
10	Parth Parekh, Fei Yuan 0005, Yushi Zhou	Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
10	Georgios Tzimpragos, Jennifer Volk, Alex Wynn, Evan Golden, Timothy Sherwood	Pulsar: A Superconducting Delay-Line Memory.	CoRR	2022	DBLP DOI BibTeX RDF
10	Taiki Yamae, Naoki Takeuchi, Nobuyuki Yoshikawa	Adiabatic Quantum-Flux-Parametron with Delay-Line Clocking Using Square Excitation Currents.	IEICE Trans. Electron.	2022	DBLP DOI BibTeX RDF
10	Alessandra Farina, Alessandro Nicolosi, Edoardo Bonizzoni	A Fully-Differential Delay-Line Based Control for Resonant Switched-Capacitor Converter.	PRIME	2022	DBLP DOI BibTeX RDF
10	Mykola Servetnyk, Wei-Han Hsiao, Alisher Mukashev	Performance Evaluation of Polarization Effects on 5G Clustered Delay Line Channels.	ICACT	2022	DBLP DOI BibTeX RDF
10	Zijie Wang, Jiajun Lu, José L. Núñez-Yáñez	A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher.	DSD	2022	DBLP DOI BibTeX RDF
10	Yue Xu, Jie Xie, Zhiwei Xing, Wenqiang Yuan, Guanqun Yu, Zhongmin Zeng, Baoshun Zhang, Dongmin Wu	A Bin-by-Bin Calibration with Neural Network for FPGA-Based Tapped-Delay-Line Time-to-Digital Converter.	RCAR	2022	DBLP DOI BibTeX RDF
10	Samer B. Idres, Hossein Hashemi 0001	Optical Binary Switched Delay Line based on Low Loss Multimode Waveguide.	OFC	2022	DBLP BibTeX RDF