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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 12478 occurrences of 5080 keywords
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Results
Found 19048 publication records. Showing 19048 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
78 | Gholamreza B. Khosrovshahi, Behruz Tayfeh-Rezaie |
Some Indecomposable t-Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 32(1-3), pp. 235-238, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
indecomposable designs, large sets of t-designs, disjoint designs, t-designs |
64 | Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar |
A multiplier generator for Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 322-323, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multiplier generator, Xilinx FPGAs, LUT based FPGA, sequential designs, combinational designs, pipelined designs, IDEAS synthesis system, XC3000 family, XC4000 family, dedicated carry logic, XACT tool, XBLOX tool, field programmable gate arrays, high level synthesis, sequential circuits, combinational circuits, digital arithmetic, logic CAD, pipeline processing, integrated circuit design, circuit CAD, table lookup, multiplying circuits, module generator, carry logic, multiplier designs |
60 | Eric S. Lee, Thomas Whalen |
Synthetic designs: a new form of true experimental design for use in information systems development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2007, San Diego, California, USA, June 12-16, 2007, pp. 191-202, 2007, ACM, 978-1-59593-639-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
synthetic experimental designs, experimental designs |
60 | Michael Braun, Adalbert Kerber, Reinhard Laue |
Systematic Construction of q-Analogs of t-(v, k, lambda)-Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 34(1), pp. 55-70, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
designs over finite fields, Kramer-Mesner method, group actions, q-analogs, t-designs |
52 | Dean S. Hoskins, Charles J. Colbourn, Douglas C. Montgomery |
Software performance testing using covering arrays: efficient screening designs with categorical factors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WOSP ![In: Proceedings of the Fifth International Workshop on Software and Performance, WOSP 2005, Palma, Illes Balears, Spain, July 12-14, 2005, pp. 131-136, 2005, ACM, 1-59593-087-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
D-optimal designs, performance testing, covering arrays |
50 | Jianzhong Shi, Akash Randhar, Dinesh Bhatia |
Macro Block Based FPGA Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 21-26, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
macro block based FPGA floorplanning, FPGA based designs, very large designs, performance driven designs, constraint-based FPGA floorplanning, flexible macro blocks, fixed macro blocks, input constraint set, topological placement, FPGA architectural constraints, large benchmark examples, VLSI floorplanning, heuristic algorithm, integrated circuit layout, ASIC design |
48 | Ziba Eslami, Gholamreza B. Khosrovshahi, Morteza Mohammad Noori |
Enumeration of t-Designs Through Intersection Matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 32(1-3), pp. 185-191, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
derived designs, intersection matrices, t-designs |
45 | Ronald H. Hardin, Neil J. A. Sloane |
McLaren's Improved Snub Cube and Other New Spherical Designs in Three Dimensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Comput. Geom. ![In: Discret. Comput. Geom. 15(4), pp. 429-441, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
41 | Behruz Tayfeh-Rezaie |
On the Existence of Large Sets of t-designs of Prime Sizes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 37(1), pp. 143-149, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
large sets of t-designs, (N, t)-partitionable sets, recursive constructions, t-designs |
41 | Usman Khalid, Jahanzeb Anwer, Nor Hisham Hamid, Vijanth S. Asirvadam |
The Impact of Sensitive Inputs on the Reliability of Nanoscale Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 249-269, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Yann Kieffer, Lilia Zaourar |
Applying Operations Research to Design for Test Insertion Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 159-187, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Quentin Angermann, Aymeric Histace, Olivier Romain, Xavier Dray, Andréa Pinna 0001, Bertrand Granado |
Smart Videocapsule for Early Diagnosis of Colorectal Cancer: Toward Embedded Image Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 325-350, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Kunal Das, Arijit Dey, Dipannita Podder, Mallika De, Debashis De |
Quantum Dot Cellular Automata: A Promising Paradigm Beyond Moore. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 295-323, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Oana Stan, Renaud Sirdey |
Introduction to Optimization Under Uncertainty Techniques for High-Performance Multicore Embedded Systems Compilation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 97-130, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Jai Narayan Tripathi, Jayanta Mukherjee 0002 |
Decoupling Network Optimization by Swarm Intelligence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 223-245, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Houman Zarrabi, A. J. Al-Khalili, Yvon Savaria |
Design Intelligence for Interconnection Realization in Power-Managed SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 69-96, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Mohamed Ibrahim, Cherif R. Salama, M. Watheq El-Kharashi, Ayman Wahba |
Pin-Count and Wire Length Optimization for Electrowetting-on-Dielectric Chips: A Metaheuristics-Based Routing Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 271-294, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Sayed Taha Muhammad, Rabab Ezz-Eldin, Magdy A. El-Moursy, Amr M. Refaat |
Low-Power NoC Using Optimum Adaptation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 191-221, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Ayan Palchaudhuri, Rajat Subhra Chakraborty |
A Fabric Component Based Approach to the Architecture and Design Automation of High-Performance Integer Arithmetic Circuits on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 33-68, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Yu Wang 0021, Weishan Dong, Junchi Yan, Li Li 0022, Chunhua Tian, Chao Zhang 0010, Zhihu Wang, Chunyang Ma |
Digital IIR Filter Design with Fix-Point Representation Using Effective Evolutionary Local Search Enhanced Differential Evolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 131-157, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
41 | Logan Rakai, Amin Farshidi |
Sizing Digital Circuits Using Convex Optimization Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computational Intelligence in Digital and Network Designs and Applications ![In: Computational Intelligence in Digital and Network Designs and Applications, pp. 3-32, 2015, Springer, 978-3-319-20070-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
38 | Eric Merchant |
Exponentially Many Hadamard Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 38(2), pp. 297-308, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Hadamard designs, symmetric designs, BIBD |
38 | Mahsa Vahidi, Alex Orailoglu |
Testability metrics for synthesis of self-testable designs and effective test plans. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 170-175, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testability metrics, self-testable designs, effective test plans, unified metrics, synthesis phases, VLSI, VLSI, built-in self test, high level synthesis, high level synthesis, design for testability, BIST, DFT, logic CAD, integrated circuit design, benchmark designs |
37 | Michael Zapf, Ute Lindheimer, Armin Heinzl |
The myth of accelerating business processes through parallel job designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Syst. E Bus. Manag. ![In: Inf. Syst. E Bus. Manag. 5(2), pp. 117-137, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Job parallelization, Order processing, Process simulation, Coordination theory, Business process design, Parallel designs |
37 | Stelios Georgiou, Christos Koukouvinos |
Self-Orthogonal and Self-Dual Codes Constructed via Combinatorial Designs and Diophantine Equations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 32(1-3), pp. 193-206, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
generalized orthogonal designs, construction, self-dual codes, Diophantine equations |
35 | Jun-Wu Dong, Dingyi Pei, Xueli Wang |
A Key Predistribution Scheme Based on 3-Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inscrypt ![In: Information Security and Cryptology, Third SKLOIS Conference, Inscrypt 2007, Xining, China, August 31 - September 5, 2007, Revised Selected Papers, pp. 81-92, 2007, Springer, 978-3-540-79498-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
key predistribution schemes, 3-designs, Möbius planes, sensor networks, combinatorial designs |
35 | Gennian Ge, Alan C. H. Ling |
Group Divisible Designs with Block Size Four and Group Type gum1 with Minimum m. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 34(1), pp. 117-126, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
group divisible designs, double group divisible designs |
35 | Kowen Lai, Christos A. Papachristou, Mikhail Baklashov |
BIST testability enhancement using high level test synthesis for behavioral and structural designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 338-342, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
BIST testability, behavioral designs, industrial benchmark, controllability, built-in self test, observability, DFT, transparency, fidelity, structural designs, high level test synthesis |
34 | Jun Hu, Xiaofeng Yu, Yan Zhang 0007, Tian Zhang 0001, Xuandong Li, Guoliang Zheng |
Checking Component-Based Embedded Software Designs for Scenario-Based Timing Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 395-404, 2005, Springer, 3-540-30807-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
embedded software designs, real-time systems, model checking, UML sequence diagrams, interface automata |
34 | Sherif M. Yacoub, Hany H. Ammar, Tom Robinson |
Dynamic Metrics for Object Oriented Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE METRICS ![In: 6th IEEE International Software Metrics Symposium (METRICS 1999), 4-6 November 1999, Boca Raton, FL, USA, pp. 50-61, 1999, IEEE Computer Society, 0-7695-0403-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Object-Oriented Designs and Real-Time OO Modeling, Dynamic Metrics, Design Quality |
33 | Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11102-11103, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Keith M. Martin |
On the Applicability of Combinatorial Designs to Key Predistribution for Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCC ![In: Coding and Cryptology, Second International Workshop, IWCC 2009, Zhangjiajie, China, June 1-5, 2009. Proceedings, pp. 124-145, 2009, Springer, 978-3-642-01813-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
sensor networks, Key predistribution, combinatorial designs |
31 | Bernhard Peischl, Naveed Riaz, Franz Wotawa |
Advances in Automated Source-Level Debugging of Verilog Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
New Challenges in Applied Intelligence Technologies ![In: New Challenges in Applied Intelligence Technologies, pp. 363-372, 2008, Springer, 978-3-540-79354-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
debugging of hardware designs, multiple testcases, model-based diagnosis, software debugging |
31 | Haibin Kan, Hong Shen 0001 |
The maximal rates of more general complex orthogonal designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2005), 5-8 December 2005, Dalian, China, pp. 177-180, 2005, IEEE Computer Society, 0-7695-2405-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
complex orthogonal designs, maximal rates, delays, space-time block codes |
31 | Franz Wotawa |
Debugging VHDL Designs: Introducing Multiple Models and First Empirical Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Intell. ![In: Appl. Intell. 21(2), pp. 159-172, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
debugging hardware designs, modeling for diagnosis, model-based diagnosis |
31 | Kwang-Ting Cheng |
Partial scan designs without using a separate scan clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 277-282, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
flip-flop selection method, flip-flop test generation method, scan registers ordering, scan-shifting concept, test vector compaction, delay fault detection, cycle breaking, logic testing, delays, timing, design for testability, logic design, automatic testing, DFT, fault coverage, flip-flops, circuit optimisation, boundary scan testing, scan chain, combinatorial optimization problem, test generation algorithm, partial scan designs, system clock |
30 | David M. Cohen, Siddhartha R. Dalal, Michael L. Fredman, Gardner C. Patton |
The AETG System: An Approach to Testing Based on Combinatiorial Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 23(7), pp. 437-444, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Testing, experimental designs, combinatorial designs, orthogonal arrays |
30 | Jacob Savir |
Generator choices for delay test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 214-221, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
BIST based delay test, generator choices, delay test vector generator, nonscan designs, transition test, skewed-load delay test, shift dependency, digital logic circuits, performance, VLSI, fault diagnosis, logic testing, delays, built-in self test, integrated circuit testing, ATPG, automatic testing, flexibility, linear feedback shift register, cost, shift registers, scan designs, boundary scan testing, test vectors, timing requirement, pseudo-random test |
30 | Ling Zhuo, Viktor K. Prasanna |
High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(8), pp. 1057-1071, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Jacob E. Boon |
Generating exact D-optimal designs for polynomial models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SpringSim (3) ![In: Proceedings of the 2007 Spring Simulation Multiconference, SpringSim 2007, Norfolk, Virginia, USA, March 25-29, 2007, Volume 3, pp. 121-126, 2007, SCS/ACM, 1-56555-314-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
general linear regression, optimal experimental design, mathematical optimization |
30 | Zhijiang Chang, Georgi Gaydadjiev, Stamatis Vassiliadis |
Infrastructure for Cross-Layer Designs Interaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 16th International Conference on Computer Communications and Networks, IEEE ICCCN 2007, Turtle Bay Resort, Honolulu, Hawaii, USA, August 13-16, 2007, pp. 19-25, 2007, IEEE, 978-1-4244-1251-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
30 | Love Singhal, Elaheh Bozorgzadeh |
Multi-layer Floorplanning on a Sequence of Reconfigurable Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-8, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
30 | Jingzhao Ou, Viktor K. Prasanna |
PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 20-23 April 2004, Napa, CA, USA, Proceedings, pp. 47-56, 2004, IEEE Computer Society, 0-7695-2230-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Dean S. Hoskins, Renée Turban, Charles J. Colbourn |
Experimental designs in software engineering: d-optimal designs and covering arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISER ![In: Proceedings of the ACM Workshop on Interdisciplinary Software Engineering Research, WISER 2004, Newport Beach, CA, USA, November 5, 2004, pp. 55-66, 2004, ACM, 1-58113-988-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
d-optimal designs, factorial experiments, covering arrays |
28 | Thomas W. Williams |
Testing in Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 5-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai |
DFM/DFY practices during physical designs for timing, signal integrity, and power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 232-237, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
0.13 micron, DFY, dynamic IR drop, process variation, physical designs, DFM, design for manufacturability, signal integrity, timing integrity, yield analysis, design for yield |
28 | Sushmita Ruj, Bimal K. Roy |
Key Predistribution Using Partially Balanced Designs in Wireless Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, 5th International Symposium, ISPA 2007, Niagara Falls, Canada, August 29-31, 2007, Proceedings, pp. 431-445, 2007, Springer, 978-3-540-74741-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
PBIBD designs, Resiliency, Combinatorial Design |
28 | Ilias S. Kotsireas, Christos Koukouvinos |
Inequivalent Hadamard matrices from orthogonal designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PASCO ![In: Parallel Symbolic Computation, PASCO 2007, International Workshop, 27-28 July 2007, University of Western Ontario, London, Ontario, Canada, pp. 95-96, 2007, ACM, 978-1-59593-741-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
orthogonal designs, systems of polynomial equations, Hadamard matrices |
28 | Elli Georgiadou, Eleni Berki, Maria del Brezo Cordero, Margaret Ross 0001, Geoff Staples |
Towards Formalised Guidelines for Migrating Structured Designs to UML: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Softw. Qual. J. ![In: Softw. Qual. J. 13(1), pp. 31-69, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
isomorphic models, UML, testing, reuse, re-engineering, structured designs, OO |
28 | Dong-Joon Shin, P. Vijay Kumar, Tor Helleseth |
An Assmus-Mattson-Type Approach for Identifying 3-Designs from Linear Codes over Z4. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 31(1), pp. 75-92, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Z 4 codes, Assmus-Mattson, complete weight enumerator, t-designs |
28 | David Masson |
Designs and Representation of the Symmetric Group. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 28(3), pp. 283-302, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
association scheme, Specht module, Hahn polynomials, Designs, tableaux, self-dual codes, symmetric group |
28 | Daniel Köb, Bernhard Peischl, Franz Wotawa |
Debugging VHDL Designs Using Temporal Process Instances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE ![In: Developments in Applied Artificial Intelligence, 16th International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, IEA/AIE 2003, Laughborough, UK, June 23-26, 2003, Proceedings, pp. 402-415, 2003, Springer, 3-540-40455-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
debugging of hardware designs, model-based diagnosis, software debugging |
28 | John R. Samson Jr., Wilfrido Alejandro Moreno, Fernando J. Falquez |
Validating fault tolerant designs using laser fault injection (LFI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 175-185, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fault tolerant designs validation, laser fault injection, VHSIC technology, in situ testing, transient error conditions, VLSI, faults, automated testing, transient, VLSI technology |
28 | William W. Agresti, William M. Evanco |
Projecting Software Defects From Analyzing Ada Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 18(11), pp. 988-997, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
software defects projection, context coupling, Ada designs, process characteristics, import-export of declarations, reuse level, regression analyses, Ada, static analysis, software quality, software quality, software metrics, software reliability, statistical analysis, visibility, defect density |
27 | Norifumi Kamiya, Marc P. C. Fossorier |
Quasi-Cyclic Codes from a Finite Affine Plane. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 38(3), pp. 311-329, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
affine planes, incidence matrices, oval designs, combinatorial designs, quasi-cyclic codes |
27 | Artan Dimnaku, Rex K. Kincaid, Michael W. Trosset |
Approximate Solutions of Continuous Dispersion Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 136(1), pp. 65-80, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
maximin distance designs, space-filling designs, nonlinear programming, location theory, computer experiments |
27 | Vamsi Krishna, N. Ranganathan |
A Methodology for High Level Power Estimation and Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 420-425, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Low Power Designs, Power Estimation, Switching Activity, High Level Designs |
27 | David B. Skillicorn |
A New Class of Fault-Tolerant Static Interconnection Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(11), pp. 1468-1470, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
balanced incomplete block designs, performance-cost tradeoffs, fault-tolerant static interconnection networks, combinatorial block designs, fault-tolerant properties, performance evaluation, fault tolerant computing, multiprocessor interconnection networks, graceful degradation |
26 | Ling Zhuo, Viktor K. Prasanna |
Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(12), pp. 1661-1675, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | John Arhin |
On the structure of 1-designs with at most two block intersection numbers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 43(2-3), pp. 103-114, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
05B25, AMS Classifications 05B05 |
26 | Yinghui Li, Hlaing Minn, Naofal Al-Dhahir, A. Robert Calderbank |
Pilot Designs for Consistent Frequency-Offset Estimation in OFDM Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 55(5), pp. 864-877, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Ling Zhuo, Viktor K. Prasanna |
Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS (1) ![In: 12th International Conference on Parallel and Distributed Systems, ICPADS 2006, Minneapolis, Minnesota, USA, July 12-15, 2006, pp. 87-95, 2006, IEEE Computer Society, 0-7695-2612-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Masahiro Fujita, Shunsuke Sasaki, Ken Matsui |
Object-oriented analysis and design of hardware/software co-designs with dependence analysis for design reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRI ![In: Proceedings of the 2005 IEEE International Conference on Information Reuse and Integration, IRI - 2005, August 15-17, 2005, Las Vegas Hilton, Las Vegas, NV, USA, pp. 318-325, 2005, IEEE Systems, Man, and Cybernetics Society, 0-7803-9093-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Byungjeong Lee, Chisu Wu |
An Automatic Restructuring Approach Preserving the Behavior of Object-Oriented Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSEC ![In: 8th Asia-Pacific Software Engineering Conference (APSEC 2001), 4-7 December 2001, Macau, China, pp. 400-, 2001, IEEE Computer Society, 0-7695-1408-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Masayoshi Yoshimura |
Implementation of Multiobjective Optimization Procedures at the Product Design Planning Stage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
System Modelling and Optimization ![In: System Modeling and Optimization, Proceedings of the 22nd IFIP TC7 Conference held from July 18-22, 2005, in Turin, Italy, pp. 181-191, 2005, Springer, 0-387-32774-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Product design planning stage, Pareto optimum solutions, Comparison of alternative designs, Hierarchical optimization problem, Rapid evaluation, Deeper insight into design solutions, Multiobjective optimization |
26 | Reinhard Rauscher |
A Design Assistant for Scheduling of Design Decisions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 88-95, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
scheduling, scheduling, VLSI designs, design decisions, design assistant |
26 | Douglas E. Harms, Bruce W. Weide |
Copying and Swapping: Influences on the Design of Reusable Software Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 17(5), pp. 424-435, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
data movement primitive, generic reusable software components, generic module designs, swapping style, data structures, software reusability |
25 | Min-Lun Chuang, Chun-Yao Wang |
Synthesis of reversible sequential elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 3(4), pp. 4:1-4:19, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
sequential elements, sequential circuits, Reversible logic |
25 | Ju-wook Jang, Seonil B. Choi, Viktor K. Prasanna |
Energy- and time-efficient matrix multiplication on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1305-1319, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Yingmin Li, Mark Hempstead, Patrick Mauro, David M. Brooks, Zhigang Hu, Kevin Skadron |
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 173-178, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
architecture, power, temperature, clock gating |
25 | Seonil Choi, Viktor K. Prasanna |
Time and Energy Efficient Matrix Factorization Using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 507-519, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | John W. Byers, Michael Mitzenmacher, Georgios Zervas |
Adaptive weighing designs for keyword value computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSDM ![In: Proceedings of the Third International Conference on Web Search and Web Data Mining, WSDM 2010, New York, NY, USA, February 4-6, 2010, pp. 331-340, 2010, ACM, 978-1-60558-889-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
weighing designs, regression, least squares, design of experiments |
25 | Xinlu Zhang, Jun Guo 0004, Suogang Gao |
Two new error-correcting pooling designs from d -bounded distance-regular graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comb. Optim. ![In: J. Comb. Optim. 17(3), pp. 339-345, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
s e -disjunct matrix, Distance-regular graph, Strongly closed subgraphs, Pooling designs |
25 | Christos Koukouvinos, Dimitris E. Simos |
Self-dual Codes over Small Prime Fields from Combinatorial Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAI ![In: Algebraic Informatics, Third International Conference, CAI 2009, Thessaloniki, Greece, May 19-22, 2009, Proceedings, pp. 278-287, 2009, Springer, 978-3-642-03563-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
construction, combinatorial designs, Self-dual codes |
25 | Sudhir Vinjamuri, Viktor K. Prasanna |
Hierarchical Dependency Graphs: Abstraction and Methodology for Mapping Systolic Array Designs to Multicore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 10th International Conference, PaCT 2009, Novosibirsk, Russia, August 31-September 4, 2009. Proceedings, pp. 284-298, 2009, Springer, 978-3-642-03274-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
systolic array designs, parallel programming, high performance computing, multicore, dependency graphs |
25 | Hong-Bin Chen, Hung-Lin Fu, Frank K. Hwang |
An upper bound of the number of tests in pooling designs for the error-tolerant complex model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Optim. Lett. ![In: Optim. Lett. 2(3), pp. 425-431, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Nonadaptive algorithms, Disjunct matrices, Pooling designs |
25 | Mohammad Tehranipoor, Kenneth M. Butler |
Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(3), pp. 214-215, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
PSN, IR drop, power supply noise, deep-submicron designs |
25 | Rosa Gil 0001, César A. Collazos 0001 |
Integrating Emotions and Knowledge in Aesthetics Designs Using Cultural Profiles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCI (11) ![In: Usability and Internationalization. Global and Local User Interfaces, Second International Conference on Usability and Internationalization, UI-HCII 2007, Held as Part of HCI International 2007, Beijing, China, July 22-27, 2007, Proceedings, Part II, pp. 344-353, 2007, Springer, 978-3-540-73288-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
aesthetics designs, cultural relations, interfaces, emotions |
25 | Mohamed H. Zaki, Ghiath Al Sammane, Sofiène Tahar |
Formal Verification of Analog and Mixed Signal Designs in Mathematica. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (2) ![In: Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27 - 30, 2007, Proceedings, Part II, pp. 263-267, 2007, Springer, 978-3-540-72585-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
AMS Designs, Formal Verification, Mathematica |
25 | Ulrich Dempwolff |
Affine Rank 3 Groups on Symmetric Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 31(2), pp. 159-168, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
rank 3 groups, symmetric designs |
25 | Dong-Joon Shin, P. Vijay Kumar, Tor Helleseth |
3-Designs from the Z4-Goethals Codes via a New Kloosterman Sum Identity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 28(3), pp. 247-263, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Z 4-Goethals codes, Kloosterman sums, t-designs |
25 | Frank K. Hwang, Yu-Chi Liu |
Random Pooling Designs Under Various Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comb. Optim. ![In: J. Comb. Optim. 7(4), pp. 339-352, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
random pooling designs, clone library screening, k-clique |
25 | Víctor A. Braberman, Fabio Pieniazek |
Duration Properties over Real Time System Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSSD ![In: Proceedings of the 10th International Workshop on Software Specification and Design, Shelter Island, San Diego, California, USA, November 5-7, 2000, pp. 51-62, 2000, IEEE Computer Society, 0-7695-0884-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
Duration Properties, Model-Checking, Timed Automata, Real-Time System Designs |
25 | Hans T. Heineken, Wojciech Maly |
Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 368-373, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Standard Cell Designs, Synthesis, Interconnects, Manufacturability, Yield |
25 | Ching-Long Su, Alvin M. Despain |
Cache designs for energy efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 306-315, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits |
25 | Frank Poirot, Gerard Tarroux, Ramine Roane |
Optimization using implicit techniques for industrial designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 8-14, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
implicit techniques, Boolean functions, Boolean functions, logic synthesis, logic CAD, binary decision diagrams, hardware description languages, hardware description languages, industrial designs, circuit optimisation, optimization techniques, design complexity |
25 | William L. Bradley, Ranga Vemuri |
Transformations for functional verification of synthesized designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 243-248, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
low-level functional verification, synthesized designs, clocking mechanisms, provably equivalent model, hierarchical network of modules, reduced state set, de-phase transform, align transform, algorithm, formal verification, transforms, transforms, logic CAD, clocks, hierarchical system, reachable states |
25 | Sergio Cárdenas-García, Marvin V. Zelkowitz |
A Management Tool For Evaluation of Software Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 17(9), pp. 961-971, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
economic decision theory, prototyping investigative system, equilibrium probabilities, software tools, decision support system, decision support systems, program verification, program verification, software designs, software prototyping, risk analysis, functional model, evaluation strategy, Selector, management tool |
24 | Emre Kolotoglu, Emine Sule Yazici |
On Minimal Defining Sets of Full Designs and Self-Complementary Designs, and a New Algorithm for Finding Defining Sets of t-Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Graphs Comb. ![In: Graphs Comb. 26(2), pp. 259-281, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
23 | David Ahlström, Andy Cockburn, Carl Gutwin, Pourang Irani |
Why it's quick to be square: modelling new and existing hierarchical menu designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI ![In: Proceedings of the 28th International Conference on Human Factors in Computing Systems, CHI 2010, Atlanta, Georgia, USA, April 10-15, 2010, pp. 1371-1380, 2010, ACM, 978-1-60558-929-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance models, menus, hierarchical menus |
23 | Vummintala Shashidhar, B. Sundar Rajan, P. Vijay Kumar |
Asymptotic-Information-Lossless Designs and the Diversity-Multiplexing Tradeoff. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 55(1), pp. 255-268, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Jennifer Seberry, Kenneth Finlayson, Sarah Spence Adams, Tadeusz A. Wysocki, Tianbing Xia, Beata J. Wysocki |
The Theory of Quaternion Orthogonal Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 56(1), pp. 256-265, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Christopher G. Jennings, Arthur E. Kirkpatrick |
Design as traversal and consequences: an exploration tool for experimental designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Graphics Interface ![In: Proceedings of the Graphics Interface 2007 Conference, May 28-30, 2007, Montreal, Canada, pp. 79-86, 2007, ACM Press, 978-1-56881-337-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
history capture, design space exploration, experimental design, design rationale, design spaces, creativity support |
23 | Mustafa Gök, Çaglar Yilmaz |
Efficient Cell Designs for Systolic Smith-Waterman Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Mustafa Gök, Çaglar Yilmaz |
Hardware Designs for Local Alignment of Protein Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCIS ![In: Computer and Information Sciences - ISCIS 2006, 21th International Symposium, Istanbul, Turkey, November 1-3, 2006, Proceedings, pp. 277-285, 2006, Springer, 3-540-47242-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Kyung-Yong Jung |
Automatic Classification for Grouping Designs in Fashion Design Recommendation Agent System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (1) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 10th International Conference, KES 2006, Bournemouth, UK, October 9-11, 2006, Proceedings, Part I, pp. 310-317, 2006, Springer, 3-540-46535-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu |
Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 594-597, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Genyuan Wang, Xiang-Gen Xia 0001 |
On optimal multilayer cyclotomic space-time code designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 51(3), pp. 1102-1135, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Haibin Kan, Hong Shen 0001 |
A counterexample for the open problem on the minimal delays of orthogonal designs with maximal rates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 51(1), pp. 355-359, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty |
Untestable Multi-Cycle Path Delay Faults in Industrial Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 194-201, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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