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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1250 occurrences of 575 keywords
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Results
Found 1028 publication records. Showing 1028 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
57 | Tai M. Chung, Henry G. Dietz |
Static scheduling of hard real-time code with instruction-level timing accuracy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: Third International Workshop on Real-Time Computing Systems Application (RTCSA '96), October 30 - November 01, 1996, Seoul, Korea, pp. 203-, 1996, IEEE Computer Society, 0-8186-7626-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
timing fault, instruction-level timing accuracy, high-level language code, instruction-level, compiler code scheduling, genetic search algorithm, real-time systems, timing analysis, processor scheduling, search space |
57 | Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria |
An instruction-level energy model for embedded VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9), pp. 998-1010, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
54 | Pierre Michaud, André Seznec, Stéphan Jourdan |
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 2-10, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, branch prediction, superscalar processors, instruction fetch |
49 | Antonio González 0001, Jordi Tubella, Carlos Molina |
Trace-Level Reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the International Conference on Parallel Processing 1999, ICPP 1999, Wakamatsu, Japan, September 21-24, 1999, pp. 30-39, 1999, IEEE Computer Society, 0-7695-0350-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
data value reuse, instruction-level reuse, Instruction-level parallelism |
47 | Toshinori Sato, Itsujiro Arita |
Simplifying Instruction Issue Logic in Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 341-346, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
47 | Glenn Reinman, Brad Calder, Todd M. Austin |
Optimizations Enabled by a Decoupled Front-End Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(4), pp. 338-355, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
fetch architectures, branch prediction, Decoupled architectures, instruction prefetching |
46 | Hai-Chen Wang, Chung-Kwong Yuen |
Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen |
Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 15(3), pp. 322-354, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference |
45 | Radu Muresan, Catherine H. Gebotys |
Instantaneous current modeling in a complex VLIW processor core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 4(2), pp. 415-451, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Instruction-level current model, current and power measurement in a processor, instantaneous current model, power and energy model |
42 | Demid Borodin, Ben H. H. Juurlink, Said Hamdioui, Stamatis Vassiliadis |
Instruction-Level Fault Tolerance Configurability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(1), pp. 89-105, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Instruction-level configurability, Fault tolerance, Performance, Reliability, Energy consumption |
41 | Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi |
Instruction-level test methodology for CPU core self-testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(4), pp. 673-689, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing |
39 | Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam |
A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 376-386, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Complexity-effective design, Temporal Redundancy, Instruction Reuse |
39 | Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau |
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(1), pp. 123-146, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers |
38 | James E. Smith 0001 |
Instruction-Level Distributed Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 34(4), pp. 59-65, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Tor E. Jeremiassen |
Sleipnir - An Instruction-Level Simulator Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 23-31, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Nicola Zingirian, Massimo Maresca |
Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 261-269, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
loop regularization, instruction level parallel architectures, instruction reordering, image processing, embedded systems, embedded systems, video processing, digital signal processors, register renaming |
37 | Hidehiko Tanaka |
Toward more advanced usage of instruction level parallelism by a very large data path processor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 437-443, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
very large data path processor, instruction analysis, parallel gain, parallel architectures, microprocessor, instruction level parallelism, processor architecture, performance gain |
37 | Chandra Chekuri, Richard Johnson, Rajeev Motwani 0001, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker |
Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 58-67, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
linear code regions, long-instruction-word machines, optimum scheduling, profile-driven instruction level parallel scheduling, profile-sensitive scheduler, ranking branch instructions, compiler optimization, scheduling heuristic, abstract model, optimising compilers, code scheduling |
36 | Norman P. Jouppi, David W. Wall |
Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989., pp. 272-282, 1989, ACM Press, 0-89791-300-0. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
35 | Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith |
Exploring Hypermedia Processor Design Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 27(1-2), pp. 171-186, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
hypermedia processor, synthesis framework, instruction-level parallelism, workload characterization |
35 | Ivano Barbieri, Massimo Bariani, Alberto Cabitto, Marco Raggio |
A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 41(2), pp. 153-168, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Hw-Sw co-design, simulation speed, simulation accuracy, simulation, multimedia, system on chip, DSP, flexibility, VLIW, architecture exploration, ISA |
35 | Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon |
Energy estimation and optimization of embedded VLIW processors based on instruction clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 886-891, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
power estimation, vliw architectures |
34 | Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede |
Superscalar Coprocessor for High-Speed Curve-Based Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 415-429, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
curve-based cryptography, HECC, ECC, instruction-level parallelism, scalar multiplication, Superscalar, coprocessor |
34 | Jingfei Kong, Cliff Changchun Zou, Huiyang Zhou |
Improving software security via runtime instruction-level taint checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASID ![In: Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, ASID 2006, San Jose, California, USA, October 21, 2006, pp. 18-24, 2006, ACM, 1-59593-576-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
format string, hardware tagging, buffer overflow |
34 | Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster 0001 |
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Tony Werner, Venkatesh Akella |
An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 140-151, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
34 | J. H. Jacobs, Augustus K. Uht, R. C. Ord |
Modeling the effects of instruction queue loading on a static instruction stream micro-architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28 - December 2, 1988, pp. 11-20, 1988, ACM/IEEE, 0-8186-1919-8. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
33 | Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve |
The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(2), pp. 218-226, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
performance evaluation, instruction-level parallelism, Shared-memory multiprocessors, software prefetching |
33 | Siamak Arya, Howard Sachs, Sreeram Duvvuru |
An architecture for high instruction level parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 153-162, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, program control structures, branches, registers, functional units, multiple instructions, conditional execution |
33 | Demid Borodin, Ben H. H. Juurlink |
Protective redundancy overhead reduction using instruction vulnerability factor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 319-326, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
instruction vulnerability, selective protection, performance, redundancy, fault detection |
32 | Weifeng Xu, Russell Tessier |
Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(3), pp. 11:1-11:40, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure |
32 | Andrei Sergeevich Terechko, Henk Corporaal |
Inter-cluster communication in VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(2), pp. 11, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
intercluster communication, pipelining, Instruction-level parallelism, register allocation, VLIW, instruction scheduler, optimizing compiler, clock frequency, cluster assignment |
32 | Weifeng Xu, Russell Tessier |
Tetris: a new register pressure control technique for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 113-122, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
register pressure control, very long instruction word (VLIW) processor, instruction level parallelism |
32 | Kemal Ebcioglu, Erik R. Altman, Michael Gschwind, Sumedh W. Sathaye |
Dynamic Binary Translation and Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(6), pp. 529-548, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
adaptive code generation, profile-directed feedback, very long instruction word architectures, instruction set layering, virtual machines, instruction-level parallelism, dynamic optimization, just-in-time compilation, binary translation, Dynamic compilation, instruction set architectures |
32 | Shyh-Kwei Chen, W. Kent Fuchs |
Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(12), pp. 1293-1304, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
compilers, Fault-tolerant computing, instruction level parallelism, VLIW architectures, instruction retry |
32 | Toshinori Sato, Itsujiro Arita |
Partial Resolution in Data Value Predictors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the 2000 International Conference on Parallel Processing, ICPP 2000, Toronto, Canada, August 21-24, 2000, pp. 69-76, 2000, IEEE Computer Society, 0-7695-0768-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
partial resolution, tag bitwidth, instruction level parallelism, value prediction, data speculation |
32 | Allen Leung, Krishna V. Palem, Amir Pnueli |
A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 12-18, 1998, pp. 158-, 1998, IEEE Computer Society, 0-8186-8591-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Compiler-optimizations, instruction level parallelism, instruction scheduling, embedded applications |
32 | Narayan Ranganathan, Manoj Franklin |
An Empirical Study of Decentralized ILP Execution Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 272-281, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
execution unit dependence, hardware window, instruction-level parallelism, data dependence, dynamic scheduling, speculative execution, control dependence, decentralization |
32 | John D. Bunda, Donald S. Fussell, William C. Athas |
Energy-efficient instruction set architecture for CMOS microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 298-305, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density |
32 | Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris |
Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 60(9), pp. 1260-1273, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
instruction-level error, microprocessor controller, Fault simulation, concurrent error detection |
31 | James E. Smith 0001 |
Instruction Level Distributed Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2000, 7th International Conference, Bangalore, India, December 17-20, 2000, Proceedings, pp. 245-258, 2000, Springer, 3-540-41429-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
31 | Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria |
Instruction-level power estimation for embedded VLIW cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA, 2000, pp. 34-38, 2000, ACM, 1-58113-268-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Keizo Saisho, Takeshi Sano, Keniti Iwata, Akira Fukuda |
The Architecture of OCMP and its Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 71-77, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
on chip multiprocessor, instruction level dispatch, fork-join type parallel processing, evaluation using simulation, shared cache, private cache |
30 | Spiridon Nikolaidis 0001, Nikolaos Kavvadias, Theodore Laopoulos, Labros Bisdounis, Spyros Blionas |
Instruction Level Energy Modeling for Pipelined Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 279-288, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | James E. Smith 0001 |
Instruction Level Distributed Processing: Adapting to Future Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000. Proceedings, pp. 1-6, 2000, Springer, 3-540-41128-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Walter Lee, Rajeev Barua, Matthew I. Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman P. Amarasinghe |
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 46-57, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Carlos Molina, Antonio González 0001, Jordi Tubella |
Dynamic removal of redundant computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 13th international conference on Supercomputing, ICS 1999, Rhodes, Greece, June 20-25, 1999, pp. 474-481, 1999, ACM, 1-58113-164-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
data-value reuse, instruction-level reuse, instruction-level parallelism |
29 | Jyh-Shian Wang, I-Wei Wu, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wei-Chung Hsu |
Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 174-181, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Hai Lin 0004, Yunsi Fei |
Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 758-763, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero |
Kilo-instruction processors, runahead and prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 269-278, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
runahead, prefetching, speculative execution, memory wall, Kilo-instruction processors |
29 | Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi |
Dynamic Speculation and Synchronization of Data Dependences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 181-193, 1997, ACM, 0-89791-901-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
29 | Nicola Zingirian, Massimo Maresca |
Run-Time Support to Register Allocation for Loop Parallelization of Image Processing Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCN ![In: High-Performance Computing and Networking, 8th International Conference, HPCN Europe 2000, Amsterdam, The Netherlands, May 8-10, 2000, Proceedings, pp. 343-352, 2000, Springer, 3-540-67553-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Dynamic Register Renaming, Image Processing, Instruction Level Parallelism, Register Allocation, Loop Parallelization |
29 | Kai Wang, Manoj Franklin |
Highly Accurate Data Value Prediction Using Hybrid Predictors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 281-290, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Instruction-level parallel (ILP) processing Speculative execution, Stride-based prediction, Two-level prediction, Data speculation |
29 | Toshio Nakatani, Kemal Ebcioglu |
Making Compaction-Based Parallelization Affordable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(9), pp. 1014-1029, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
compaction-based parallelization, code explosion problem, software lookahead heuristic, VLIW parallelizing compiler, branch-intensive code, AIX utilities, fgrep, sed, parallel programming, parallel architectures, compress, program, sort, instruction-level parallelism, software pipelining, pipeline processing, instruction sets, loop parallelization, yacc |
29 | Jean-Luc Gaudiot |
Parallel Computer Architecture and Instruction-Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2002, Parallel Processing, 8th International Euro-Par Conference Paderborn, Germany, August 27-30, 2002, Proceedings, pp. 457, 2002, Springer, 3-540-44049-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffrey E. Nelson, Sean M. Pieper, Anthony G. Rowe |
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(6), pp. 684-697, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
performance analysis, low-power design, power management, System architectures, energy-aware systems, integration and modeling, design aids |
28 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
Register Constrained Modulo Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 15(5), pp. 417-430, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Instruction level parallelism, register allocation, instruction scheduling, modulo scheduling, spill code |
28 | Sebastian Unger, Frank Mueller 0001 |
Handling irreducible loops: optimized node splitting versus DJ-graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 24(4), pp. 299-333, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
irreducible flowgraphs, reducible flowgraphs, compilation, instruction-level parallelism, Code optimization, loops, control flow graphs, node splitting |
28 | Toshinori Sato, Itsujiro Arita |
Table size reduction for data value predictors by exploiting narrow width values. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000, pp. 196-205, 2000, ACM, 1-58113-270-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
narrow width operands, instruction level parallelism, hardware implementation, value prediction, data speculation |
28 | Jeffrey J. Cook, Craig B. Zilles |
A characterization of instruction-level error derating and its implications for error detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 482-491, 2008, IEEE Computer Society, 978-1-4244-2397-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Chaitali Chakrabarti, Dinesh Gaitonde |
Instruction level power model of microcontrollers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 76-79, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Jack L. Lo, Susan J. Eggers |
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN'95 Conference on Programming Language Design and Implementation (PLDI), La Jolla, California, USA, June 18-21, 1995, pp. 151-162, 1995, ACM, 0-89791-697-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
28 | Timothy Furtak, José Nelson Amaral, Robert Niewiadomski |
Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, San Diego, California, USA, June 9-11, 2007, pp. 348-357, 2007, ACM, 978-1-59593-667-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
sorting, instruction-level parallelism, SIMD, vectorization, sorting networks, quicksort |
28 | Jose Rizo-Morente, Miguel Casas-Sanchez, Chris J. Bleakley |
Dynamic current modeling at the instruction level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 95-100, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
current and power measurement in a processor, dynamic instruction-level current model |
28 | Sid Ahmed Ali Touati |
Register Saturation in Instruction Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 33(4), pp. 393-449, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Register requirement, instruction level parallelism, integer linear programming, optimizing compilation, register pressure |
28 | Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
Adapting instruction level parallelism for optimizing leakage in VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'03). San Diego, California, USA, June 11-13, 2003, pp. 275-283, 2003, ACM, 1-58113-647-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
power supply gating, instruction level parallelism, instruction scheduling, VLIW architecture, leakage energy, functional units |
28 | Meng-chou Chang, Feipei Lai |
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(3), pp. 278-293, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multilevel boosting, shadow register file, conjugate register file, scheduling-conflict graph, Instruction-level parallelism, speculative execution, superscalar processors |
28 | Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park |
Eliminating Conditional Branches for Enhancing Instruction Level Parallelism in VLIW Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1996 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '96), June 12-14, 1996, Beijing, China, pp. 193-199, 1996, IEEE Computer Society, 0-8186-7460-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Compiler, Instruction Level Parallelism, VLIW, Superscalar, Conditional Branches |
28 | Michael A. Schuette, John Paul Shen |
Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(2), pp. 129-140, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
control-flow monitoring, machine parallelism, idle resources, Multiflow TRACE 14/300 processor, TRACE 14/300, available resource-driven control-flow monitoring, parallel architectures, fault tolerant computing, error detection, instruction-level parallelism, concurrent error detection |
28 | Norman P. Jouppi |
The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(12), pp. 1645-1658, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
machine performance, first-order estimate, machine parallelism, instruction-level, machine pipelines, MultiTitan, superscalar machine, performance evaluation, parallel architectures, pipeline processing, CRAY-1 |
27 | Jia Chen, Shengyuan Wang, Yuan Dong, Guilan Dai, Yang Yang |
A Functionality Based Instruction Level Software Power Estimation Model for Embedded RISC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, First International Conference, ICESS 2004, Hangzhou, China, December 9-10, 2004, Revised Selected Papers, pp. 443-448, 2004, Springer, 3-540-28128-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau |
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 402-408, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Glenn Reinman, Todd M. Austin, Brad Calder |
A Scalable Front-End Architecture for Fast Instruction Delivery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 234-245, 1999, IEEE Computer Society, 0-7695-0170-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita |
Influence of Compiler Optimizations on Value Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCN ![In: High-Performance Computing and Networking, 9th International Conference, HPCN Europe 2001, Amsterdam, The Netherlands, June 25-27, 2001, Proceedings, pp. 312-321, 2001, Springer, 3-540-42293-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
optimization level, high-performance compilers, instruction level parallelism, value prediction, data speculation |
26 | K. Ashwin Kumar, Aasish Kumar Pappu, K. Sarath Kumar, Sudip Sanyal |
Hybrid Approach for Parallelization of Sequential Code with Function Level and Block Level Parallelization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 13-17 September 2006, Bialystok, Poland, pp. 161-166, 2006, IEEE Computer Society, 0-7695-2554-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Block level parallelization, Function level parallelization, Instruction level parallelization, Automatic parallelization, Loop level parallelization |
26 | Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto |
An instruction-level functionally-based energy estimation model for 32-bits microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 346-351, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Demid Borodin, Ben H. H. Juurlink, Stamatis Vassiliadis |
Instruction-Level Fault Tolerance Configurability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007, pp. 110-117, 2007, IEEE, 1-4244-1058-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Mehrdad Reshadi, Prabhat Mishra 0001, Nikil D. Dutt |
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(3), pp. 20:1-20:27, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
interpretive simulation, partial evaluation, instruction set architecture, Compiled simulation |
25 | Suriya Subramanian, Kathryn S. McKinley |
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings, pp. 308-323, 2009, Springer, 978-3-540-92989-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato |
Indirect Tag Search Mechanism for Instruction Window Energy Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Seventh International Conference on Computer and Information Technology (CIT 2007), October 16-19, 2007, University of Aizu, Fukushima, Japan, pp. 841-846, 2007, IEEE Computer Society, 978-0-7695-2983-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Shu Xiao 0001, Edmund Ming-Kit Lai |
Instruction scheduling of VLIW architectures for balanced power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 824-829, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan |
An analysis of a resource efficient checkpoint architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(4), pp. 418-444, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
checkpoint architecture, high-performance computing, Computer architecture, scalable architecture |
25 | Daniel Tate, Gordon B. Steven, Fleur L. Steven |
Static Scheduling for Out-of-order Instruction Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACAC ![In: 5th Australasian Computer Architecture Conference (ACAC 2000), 31 January - 3 February 2000, Canberra, Australia, pp. 90-96, 2000, IEEE Computer Society, 0-7695-0512-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Byron Cook, John Launchbury, John Matthews, Richard B. Kieburtz |
Formal Verification of Explicitly Parallel Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHARME ![In: Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings, pp. 23-36, 1999, Springer, 3-540-66559-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino |
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 8-12, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Low-Power Design, Microprocessors |
25 | Rad Silvera, Jian Wang, Ramaswamy Govindarajan, Guang R. Gao |
A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 78-89, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Scheduling, register renaming, out-of-order issue, Register Pressure |
25 | Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis, Nectarios Koziris |
Exploring the performance limits of simultaneous multithreading for memory intensive applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 44(1), pp. 64-97, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Speculative precomputation, Performance analysis, Instruction-level parallelism, Thread-level parallelism, Simultaneous multithreading, Software prefetching |
25 | Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch |
Accurate and Practical Profile-driven Compilation Using the Profile Buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 36-45, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
profile buffer, superblock scheduling, profiling, compiler optimization, instruction-level parallelism |
25 | Shlomit S. Pinter, Adi Yoaz |
Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 214-225, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
LRU mechanism, SPEC92 benchmark, Tango, base line architecture, hardware-based data prefetching technique, memory reference instructions, program progress graph, performance, parallel processing, instruction level parallelism, simulation results, superscalar processors, branch target buffer, instruction prefetching, hardware resources, slack time |
24 | Georgi Gaydadjiev, Stamatis Vassiliadis |
SCISM vs IA-64 Tagging: Differences/Code Density Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2004 Parallel Processing, 10th International Euro-Par Conference, Pisa, Italy, August 31-September 3, 2004, Proceedings, pp. 571-577, 2004, Springer, 3-540-22924-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Instruction Tagging, SCISM, Instruction Level Parallelism, IA-64 |
24 | Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero |
MIRS: Modulo Scheduling with Integrated Register Spilling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 14th International Workshop, LCPC 2001, Cumberland Falls, KY, USA, August 1-3, 2001. Revised Papers, pp. 239-253, 2001, Springer, 3-540-04029-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Instruction-Level Parallelism, Register Allocation, Software Pipelining, Spill Code |
24 | Ireneusz Karkowski, Henk Corporaal |
Design of Heterogenous Multi-Processor Embedded Systems: Applying Functional Pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), San Francisco, CA, USA, October 11-15, 1997, pp. 156-165, 1997, IEEE Computer Society, 0-8186-8090-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
heterogenous multiprocessor embedded system design, functional pipelining, embedded program mapping, ANSI C program, application specific processor pipeline, frequency tracking system, two-processor system, highly optimized single core solution, architecture, multiprocessing systems, instruction level parallelism, speedup, efficient algorithm, loops |
24 | Kemal Ebcioglu, Erik R. Altman |
DAISY: Dynamic Compilation for 100% Architectural Compatibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 26-37, 1997, ACM, 0-89791-901-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
object code compatible VLIW, instruction-level parallelism, superscalar, binary translation, dynamic compilation |
24 | Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith 0001 |
The Performance Potential of Data Dependence Speculation & Collapsing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 238-247, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
address generation-load dependences, address prediction rate, base instruction level parallel machine, dependence collapsing, performance potential, true data dependences, parallel programming, trace-driven simulation, data dependence speculation, address prediction |
24 | Manu Gulati, Nader Bagherzadeh |
Performance Study of a Multithreaded Superscalar Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Second International Symposium on High-Performance Computer Architecture, San Jose, CA, USA, February 3-7, 1996, pp. 291-301, 1996, IEEE Computer Society, 0-8186-7237-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multithreading, instruction-level parallelism, Superscalars, out-of-order execution |
24 | Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe |
Load Balancing in Superscalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 651-, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources |
24 | Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita |
Power analysis and low-power scheduling techniques for embedded DSP software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 110-115, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor |
24 | William F. Richardson, Erik Brunvand |
Precise exception handling for a self-timed processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 32-37, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
precise exception handling, self-timed processor, multiple concurrent processes, self-timed queues, decoupled computer architectures, micropipelined processor, Fred, pipelined computer architecture, out-of-order instruction completion, parallel architectures, exception handling, instruction level parallelism, self-adjusting systems, self-timed systems |
24 | Roger A. Bringmann, Scott A. Mahlke, Wen-mei W. Hwu |
A study of the effects of compiler-controlled speculation on instruction and data caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 211-220, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
compiler-controlled speculation, nonnumeric programs, speculatively scheduled code, aggressive speculation models, scheduling, performance evaluation, parallel programming, time, instruction level parallelism, program compilers, data caches, cache storage, instruction cache, cache misses, performance results |
24 | Min Li 0001, David Novo, Bruno Bougard, Trevor E. Carlson, Liesbet Van der Perre, Francky Catthoor |
Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 57(4), pp. 1604-1615, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
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