Search results for "instruction-level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
57	Tai M. Chung, Henry G. Dietz	Static scheduling of hard real-time code with instruction-level timing accuracy.	RTCSA	1996	DBLP DOI BibTeX RDF	timing fault, instruction-level timing accuracy, high-level language code, instruction-level, compiler code scheduling, genetic search algorithm, real-time systems, timing analysis, processor scheduling, search space
57	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria	An instruction-level energy model for embedded VLIW architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
54	Pierre Michaud, André Seznec, Stéphan Jourdan	Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	instruction-level parallelism, branch prediction, superscalar processors, instruction fetch
49	Antonio González 0001, Jordi Tubella, Carlos Molina	Trace-Level Reuse.	ICPP	1999	DBLP DOI BibTeX RDF	data value reuse, instruction-level reuse, Instruction-level parallelism
47	Toshinori Sato, Itsujiro Arita	Simplifying Instruction Issue Logic in Superscalar Processors.	DSD	2002	DBLP DOI BibTeX RDF
47	Glenn Reinman, Brad Calder, Todd M. Austin	Optimizations Enabled by a Decoupled Front-End Architecture.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	fetch architectures, branch prediction, Decoupled architectures, instruction prefetching
46	Hai-Chen Wang, Chung-Kwong Yuen	Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processor.	IPDPS	2006	DBLP DOI BibTeX RDF
46	Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen	Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.	ACM Trans. Comput. Syst.	1997	DBLP DOI BibTeX RDF	multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference
45	Radu Muresan, Catherine H. Gebotys	Instantaneous current modeling in a complex VLIW processor core.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	Instruction-level current model, current and power measurement in a processor, instantaneous current model, power and energy model
42	Demid Borodin, Ben H. H. Juurlink, Said Hamdioui, Stamatis Vassiliadis	Instruction-Level Fault Tolerance Configurability.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Instruction-level configurability, Fault tolerance, Performance, Reliability, Energy consumption
41	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Instruction-level test methodology for CPU core self-testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing
39	Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam	A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy.	ISCA	2004	DBLP DOI BibTeX RDF	Complexity-effective design, Temporal Redundancy, Instruction Reuse
39	Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau	Compilation framework for code size reduction using reduced bit-width ISAs (rISAs).	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers
38	James E. Smith 0001	Instruction-Level Distributed Processing.	Computer	2001	DBLP DOI BibTeX RDF
38	Tor E. Jeremiassen	Sleipnir - An Instruction-Level Simulator Generator.	ICCD	2000	DBLP DOI BibTeX RDF
38	Nicola Zingirian, Massimo Maresca	Loop Regularization for Image and Video Processing on Instruction Level Parallel Architectures.	CAMP	2000	DBLP DOI BibTeX RDF	loop regularization, instruction level parallel architectures, instruction reordering, image processing, embedded systems, embedded systems, video processing, digital signal processors, register renaming
37	Hidehiko Tanaka	Toward more advanced usage of instruction level parallelism by a very large data path processor architecture.	ISPAN	1997	DBLP DOI BibTeX RDF	very large data path processor, instruction analysis, parallel gain, parallel architectures, microprocessor, instruction level parallelism, processor architecture, performance gain
37	Chandra Chekuri, Richard Johnson, Rajeev Motwani 0001, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker	Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks.	MICRO	1996	DBLP DOI BibTeX RDF	linear code regions, long-instruction-word machines, optimum scheduling, profile-driven instruction level parallel scheduling, profile-sensitive scheduler, ranking branch instructions, compiler optimization, scheduling heuristic, abstract model, optimising compilers, code scheduling
36	Norman P. Jouppi, David W. Wall	Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines.	ASPLOS	1989	DBLP DOI BibTeX RDF
35	Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith	Exploring Hypermedia Processor Design Space.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	hypermedia processor, synthesis framework, instruction-level parallelism, workload characterization
35	Ivano Barbieri, Massimo Bariani, Alberto Cabitto, Marco Raggio	A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	Hw-Sw co-design, simulation speed, simulation accuracy, simulation, multimedia, system on chip, DSP, flexibility, VLIW, architecture exploration, ISA
35	Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon	Energy estimation and optimization of embedded VLIW processors based on instruction clustering.	DAC	2002	DBLP DOI BibTeX RDF	power estimation, vliw architectures
34	Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Superscalar Coprocessor for High-Speed Curve-Based Cryptography.	CHES	2006	DBLP DOI BibTeX RDF	curve-based cryptography, HECC, ECC, instruction-level parallelism, scalar multiplication, Superscalar, coprocessor
34	Jingfei Kong, Cliff Changchun Zou, Huiyang Zhou	Improving software security via runtime instruction-level taint checking.	ASID	2006	DBLP DOI BibTeX RDF	format string, hardware tagging, buffer overflow
34	Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster 0001	Extracting Speedup From C-Code With Poor Instruction-Level Parallelism.	IPDPS	2005	DBLP DOI BibTeX RDF
34	Tony Werner, Venkatesh Akella	An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism.	ASYNC	2001	DBLP DOI BibTeX RDF
34	J. H. Jacobs, Augustus K. Uht, R. C. Ord	Modeling the effects of instruction queue loading on a static instruction stream micro-architecture.	MICRO	1988	DBLP BibTeX RDF
33	Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita V. Adve	The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	performance evaluation, instruction-level parallelism, Shared-memory multiprocessors, software prefetching
33	Siamak Arya, Howard Sachs, Sreeram Duvvuru	An architecture for high instruction level parallelism.	HICSS (1)	1995	DBLP DOI BibTeX RDF	high instruction level parallelism, sequential order, code execution, dataflow problems, condition bits, nonblocking cache, Software Scheduled SuperScalar, parallel programming, compiler, parallel architectures, parallel architecture, pipelining, program compilers, data flow analysis, software pipelining, pipeline processing, data flow, processor architecture, speculative execution, control flow, hardware support, program control structures, branches, registers, functional units, multiple instructions, conditional execution
33	Demid Borodin, Ben H. H. Juurlink	Protective redundancy overhead reduction using instruction vulnerability factor.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	instruction vulnerability, selective protection, performance, redundancy, fault detection
32	Weifeng Xu, Russell Tessier	Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure
32	Andrei Sergeevich Terechko, Henk Corporaal	Inter-cluster communication in VLIW architectures.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	intercluster communication, pipelining, Instruction-level parallelism, register allocation, VLIW, instruction scheduler, optimizing compiler, clock frequency, cluster assignment
32	Weifeng Xu, Russell Tessier	Tetris: a new register pressure control technique for VLIW processors.	LCTES	2007	DBLP DOI BibTeX RDF	register pressure control, very long instruction word (VLIW) processor, instruction level parallelism
32	Kemal Ebcioglu, Erik R. Altman, Michael Gschwind, Sumedh W. Sathaye	Dynamic Binary Translation and Optimization.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	adaptive code generation, profile-directed feedback, very long instruction word architectures, instruction set layering, virtual machines, instruction-level parallelism, dynamic optimization, just-in-time compilation, binary translation, Dynamic compilation, instruction set architectures
32	Shyh-Kwei Chen, W. Kent Fuchs	Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures.	IEEE Trans. Parallel Distributed Syst.	2001	DBLP DOI BibTeX RDF	compilers, Fault-tolerant computing, instruction level parallelism, VLIW architectures, instruction retry
32	Toshinori Sato, Itsujiro Arita	Partial Resolution in Data Value Predictors.	ICPP	2000	DBLP DOI BibTeX RDF	partial resolution, tag bitwidth, instruction level parallelism, value prediction, data speculation
32	Allen Leung, Krishna V. Palem, Amir Pnueli	A Fast Algorithm for Scheduling Time-Constrained Instructions on Processors with ILP.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Compiler-optimizations, instruction level parallelism, instruction scheduling, embedded applications
32	Narayan Ranganathan, Manoj Franklin	An Empirical Study of Decentralized ILP Execution Models.	ASPLOS	1998	DBLP DOI BibTeX RDF	execution unit dependence, hardware window, instruction-level parallelism, data dependence, dynamic scheduling, speculative execution, control dependence, decentralization
32	John D. Bunda, Donald S. Fussell, William C. Athas	Energy-efficient instruction set architecture for CMOS microprocessors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density
32	Michail Maniatakos, Naghmeh Karimi, Chandra Tirumurti, Abhijit Jas, Yiorgos Makris	Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	instruction-level error, microprocessor controller, Fault simulation, concurrent error detection
31	James E. Smith 0001	Instruction Level Distributed Processing.	HiPC	2000	DBLP DOI BibTeX RDF
31	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria	Instruction-level power estimation for embedded VLIW cores.	CODES	2000	DBLP DOI BibTeX RDF
30	Keizo Saisho, Takeshi Sano, Keniti Iwata, Akira Fukuda	The Architecture of OCMP and its Evaluation.	ISPAN	1997	DBLP DOI BibTeX RDF	on chip multiprocessor, instruction level dispatch, fork-join type parallel processing, evaluation using simulation, shared cache, private cache
30	Spiridon Nikolaidis 0001, Nikolaos Kavvadias, Theodore Laopoulos, Labros Bisdounis, Spyros Blionas	Instruction Level Energy Modeling for Pipelined Processors.	PATMOS	2003	DBLP DOI BibTeX RDF
30	James E. Smith 0001	Instruction Level Distributed Processing: Adapting to Future Technology.	ISHPC	2000	DBLP DOI BibTeX RDF
30	Walter Lee, Rajeev Barua, Matthew I. Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman P. Amarasinghe	Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine.	ASPLOS	1998	DBLP DOI BibTeX RDF
30	Carlos Molina, Antonio González 0001, Jordi Tubella	Dynamic removal of redundant computations.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF	data-value reuse, instruction-level reuse, instruction-level parallelism
29	Jyh-Shian Wang, I-Wei Wu, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wei-Chung Hsu	Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor.	CSE (2)	2009	DBLP DOI BibTeX RDF
29	Hai Lin 0004, Yunsi Fei	Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency.	DATE	2008	DBLP DOI BibTeX RDF
29	Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero	Kilo-instruction processors, runahead and prefetching.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	runahead, prefetching, speculative execution, memory wall, Kilo-instruction processors
29	Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi	Dynamic Speculation and Synchronization of Data Dependences.	ISCA	1997	DBLP DOI BibTeX RDF
29	Nicola Zingirian, Massimo Maresca	Run-Time Support to Register Allocation for Loop Parallelization of Image Processing Programs.	HPCN	2000	DBLP DOI BibTeX RDF	Dynamic Register Renaming, Image Processing, Instruction Level Parallelism, Register Allocation, Loop Parallelization
29	Kai Wang, Manoj Franklin	Highly Accurate Data Value Prediction Using Hybrid Predictors.	MICRO	1997	DBLP DOI BibTeX RDF	Instruction-level parallel (ILP) processing Speculative execution, Stride-based prediction, Two-level prediction, Data speculation
29	Toshio Nakatani, Kemal Ebcioglu	Making Compaction-Based Parallelization Affordable.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	compaction-based parallelization, code explosion problem, software lookahead heuristic, VLIW parallelizing compiler, branch-intensive code, AIX utilities, fgrep, sed, parallel programming, parallel architectures, compress, program, sort, instruction-level parallelism, software pipelining, pipeline processing, instruction sets, loop parallelization, yacc
29	Jean-Luc Gaudiot	Parallel Computer Architecture and Instruction-Level Parallelism.	Euro-Par	2002	DBLP DOI BibTeX RDF
28	Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffrey E. Nelson, Sean M. Pieper, Anthony G. Rowe	Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	performance analysis, low-power design, power management, System architectures, energy-aware systems, integration and modeling, design aids
28	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	Register Constrained Modulo Scheduling.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	Instruction level parallelism, register allocation, instruction scheduling, modulo scheduling, spill code
28	Sebastian Unger, Frank Mueller 0001	Handling irreducible loops: optimized node splitting versus DJ-graphs.	ACM Trans. Program. Lang. Syst.	2002	DBLP DOI BibTeX RDF	irreducible flowgraphs, reducible flowgraphs, compilation, instruction-level parallelism, Code optimization, loops, control flow graphs, node splitting
28	Toshinori Sato, Itsujiro Arita	Table size reduction for data value predictors by exploiting narrow width values.	ICS	2000	DBLP DOI BibTeX RDF	narrow width operands, instruction level parallelism, hardware implementation, value prediction, data speculation
28	Jeffrey J. Cook, Craig B. Zilles	A characterization of instruction-level error derating and its implications for error detection.	DSN	2008	DBLP DOI BibTeX RDF
28	Chaitali Chakrabarti, Dinesh Gaitonde	Instruction level power model of microcontrollers.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
28	Jack L. Lo, Susan J. Eggers	Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism.	PLDI	1995	DBLP DOI BibTeX RDF
28	Timothy Furtak, José Nelson Amaral, Robert Niewiadomski	Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms.	SPAA	2007	DBLP DOI BibTeX RDF	sorting, instruction-level parallelism, SIMD, vectorization, sorting networks, quicksort
28	Jose Rizo-Morente, Miguel Casas-Sanchez, Chris J. Bleakley	Dynamic current modeling at the instruction level.	ISLPED	2006	DBLP DOI BibTeX RDF	current and power measurement in a processor, dynamic instruction-level current model
28	Sid Ahmed Ali Touati	Register Saturation in Instruction Level Parallelism.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	Register requirement, instruction level parallelism, integer linear programming, optimizing compilation, register pressure
28	Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Adapting instruction level parallelism for optimizing leakage in VLIW architectures.	LCTES	2003	DBLP DOI BibTeX RDF	power supply gating, instruction level parallelism, instruction scheduling, VLIW architecture, leakage energy, functional units
28	Meng-chou Chang, Feipei Lai	Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	multilevel boosting, shadow register file, conjugate register file, scheduling-conflict graph, Instruction-level parallelism, speculative execution, superscalar processors
28	Seong-Uk Choi, Sung-Soon Park, Myong-Soon Park	Eliminating Conditional Branches for Enhancing Instruction Level Parallelism in VLIW Compiler.	ISPAN	1996	DBLP DOI BibTeX RDF	Compiler, Instruction Level Parallelism, VLIW, Superscalar, Conditional Branches
28	Michael A. Schuette, John Paul Shen	Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	control-flow monitoring, machine parallelism, idle resources, Multiflow TRACE 14/300 processor, TRACE 14/300, available resource-driven control-flow monitoring, parallel architectures, fault tolerant computing, error detection, instruction-level parallelism, concurrent error detection
28	Norman P. Jouppi	The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	machine performance, first-order estimate, machine parallelism, instruction-level, machine pipelines, MultiTitan, superscalar machine, performance evaluation, parallel architectures, pipeline processing, CRAY-1
27	Jia Chen, Shengyuan Wang, Yuan Dong, Guilan Dai, Yang Yang	A Functionality Based Instruction Level Software Power Estimation Model for Embedded RISC Processors.	ICESS	2004	DBLP DOI BibTeX RDF
26	Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau	An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.	DATE	2002	DBLP DOI BibTeX RDF
26	Glenn Reinman, Todd M. Austin, Brad Calder	A Scalable Front-End Architecture for Fast Instruction Delivery.	ISCA	1999	DBLP DOI BibTeX RDF
26	Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita	Influence of Compiler Optimizations on Value Prediction.	HPCN	2001	DBLP DOI BibTeX RDF	optimization level, high-performance compilers, instruction level parallelism, value prediction, data speculation
26	K. Ashwin Kumar, Aasish Kumar Pappu, K. Sarath Kumar, Sudip Sanyal	Hybrid Approach for Parallelization of Sequential Code with Function Level and Block Level Parallelization.	PARELEC	2006	DBLP DOI BibTeX RDF	Block level parallelization, Function level parallelization, Instruction level parallelization, Automatic parallelization, Loop level parallelization
26	Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto	An instruction-level functionally-based energy estimation model for 32-bits microprocessors.	DAC	2000	DBLP DOI BibTeX RDF
26	Demid Borodin, Ben H. H. Juurlink, Stamatis Vassiliadis	Instruction-Level Fault Tolerance Configurability.	ICSAMOS	2007	DBLP DOI BibTeX RDF
25	Mehrdad Reshadi, Prabhat Mishra 0001, Nikil D. Dutt	Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	interpretive simulation, partial evaluation, instruction set architecture, Compiled simulation
25	Suriya Subramanian, Kathryn S. McKinley	HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic.	HiPEAC	2009	DBLP DOI BibTeX RDF
25	Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato	Indirect Tag Search Mechanism for Instruction Window Energy Reduction.	CIT	2007	DBLP DOI BibTeX RDF
25	Shu Xiao 0001, Edmund Ming-Kit Lai	Instruction scheduling of VLIW architectures for balanced power consumption.	ASP-DAC	2005	DBLP DOI BibTeX RDF
25	Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan	An analysis of a resource efficient checkpoint architecture.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	checkpoint architecture, high-performance computing, Computer architecture, scalable architecture
25	Daniel Tate, Gordon B. Steven, Fleur L. Steven	Static Scheduling for Out-of-order Instruction Issue Processors.	ACAC	2000	DBLP DOI BibTeX RDF
25	Byron Cook, John Launchbury, John Matthews, Richard B. Kieburtz	Formal Verification of Explicitly Parallel Microprocessors.	CHARME	1999	DBLP DOI BibTeX RDF
25	Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino	Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Low-Power Design, Microprocessors
25	Rad Silvera, Jian Wang, Ramaswamy Govindarajan, Guang R. Gao	A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors.	IEEE PACT	1997	DBLP DOI BibTeX RDF	Scheduling, register renaming, out-of-order issue, Register Pressure
25	Evangelia Athanasaki, Nikos Anastopoulos, Kornilios Kourtis, Nectarios Koziris	Exploring the performance limits of simultaneous multithreading for memory intensive applications.	J. Supercomput.	2008	DBLP DOI BibTeX RDF	Speculative precomputation, Performance analysis, Instruction-level parallelism, Thread-level parallelism, Simultaneous multithreading, Software prefetching
25	Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch	Accurate and Practical Profile-driven Compilation Using the Profile Buffer.	MICRO	1996	DBLP DOI BibTeX RDF	profile buffer, superblock scheduling, profiling, compiler optimization, instruction-level parallelism
25	Shlomit S. Pinter, Adi Yoaz	Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors.	MICRO	1996	DBLP DOI BibTeX RDF	LRU mechanism, SPEC92 benchmark, Tango, base line architecture, hardware-based data prefetching technique, memory reference instructions, program progress graph, performance, parallel processing, instruction level parallelism, simulation results, superscalar processors, branch target buffer, instruction prefetching, hardware resources, slack time
24	Georgi Gaydadjiev, Stamatis Vassiliadis	SCISM vs IA-64 Tagging: Differences/Code Density Effects.	Euro-Par	2004	DBLP DOI BibTeX RDF	Instruction Tagging, SCISM, Instruction Level Parallelism, IA-64
24	Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero	MIRS: Modulo Scheduling with Integrated Register Spilling.	LCPC	2001	DBLP DOI BibTeX RDF	Instruction-Level Parallelism, Register Allocation, Software Pipelining, Spill Code
24	Ireneusz Karkowski, Henk Corporaal	Design of Heterogenous Multi-Processor Embedded Systems: Applying Functional Pipelining.	IEEE PACT	1997	DBLP DOI BibTeX RDF	heterogenous multiprocessor embedded system design, functional pipelining, embedded program mapping, ANSI C program, application specific processor pipeline, frequency tracking system, two-processor system, highly optimized single core solution, architecture, multiprocessing systems, instruction level parallelism, speedup, efficient algorithm, loops
24	Kemal Ebcioglu, Erik R. Altman	DAISY: Dynamic Compilation for 100% Architectural Compatibility.	ISCA	1997	DBLP DOI BibTeX RDF	object code compatible VLIW, instruction-level parallelism, superscalar, binary translation, dynamic compilation
24	Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith 0001	The Performance Potential of Data Dependence Speculation & Collapsing.	MICRO	1996	DBLP DOI BibTeX RDF	address generation-load dependences, address prediction rate, base instruction level parallel machine, dependence collapsing, performance potential, true data dependences, parallel programming, trace-driven simulation, data dependence speculation, address prediction
24	Manu Gulati, Nader Bagherzadeh	Performance Study of a Multithreaded Superscalar Microprocessor.	HPCA	1996	DBLP DOI BibTeX RDF	multithreading, instruction-level parallelism, Superscalars, out-of-order execution
24	Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe	Load Balancing in Superscalar Architectures.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources
24	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita	Power analysis and low-power scheduling techniques for embedded DSP software.	ISSS	1995	DBLP DOI BibTeX RDF	circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
24	William F. Richardson, Erik Brunvand	Precise exception handling for a self-timed processor.	ICCD	1995	DBLP DOI BibTeX RDF	precise exception handling, self-timed processor, multiple concurrent processes, self-timed queues, decoupled computer architectures, micropipelined processor, Fred, pipelined computer architecture, out-of-order instruction completion, parallel architectures, exception handling, instruction level parallelism, self-adjusting systems, self-timed systems
24	Roger A. Bringmann, Scott A. Mahlke, Wen-mei W. Hwu	A study of the effects of compiler-controlled speculation on instruction and data caches.	HICSS (1)	1995	DBLP DOI BibTeX RDF	compiler-controlled speculation, nonnumeric programs, speculatively scheduled code, aggressive speculation models, scheduling, performance evaluation, parallel programming, time, instruction level parallelism, program compilers, data caches, cache storage, instruction cache, cache misses, performance results
24	Min Li 0001, David Novo, Bruno Bougard, Trevor E. Carlson, Liesbet Van der Perre, Francky Catthoor	Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures.	IEEE Trans. Signal Process.	2009	DBLP DOI BibTeX RDF