Search results for "intra-chip"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
47	Md. Sajjad Rahaman, Masud H. Chowdhury	Improved ber performance in intra-chip rf/wireless interconnect systems.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	RF interconnect, intra-chip channel, wireless interconnect, interleaver, error control coding, channel coding
39	Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu 0016, Michael C. Huang 0001, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore	An intra-chip free-space optical interconnect.	ISCA	2010	DBLP DOI BibTeX RDF	free-space optical interconnect, intra-chip, 3d
36	Eli Yablonovitch	Can nano-photonic silicon circuits become an INTRA-chip interconnect technology?	ICCAD	2007	DBLP DOI BibTeX RDF
32	Claudio Favi, Edoardo Charbon	Techniques for fully integrated intra-/inter-chip optical communication.	DAC	2008	DBLP DOI BibTeX RDF	intra-chip & inter-chip communication, low power optical communication, miniaturized optical channel and detector
32	Louis Scheffer	An overview of on-chip interconnect variation.	SLIP	2006	DBLP DOI BibTeX RDF	causes of variability, on-chip variation, design rules
29	Walker J. Turner, John W. Poulton, John M. Wilson 0002, Xi Chen 0033, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray	Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects.	CICC	2018	DBLP DOI BibTeX RDF
26	Pranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy	Silicon-photonic network architectures for scalable, power-efficient multi-chip systems.	ISCA	2010	DBLP DOI BibTeX RDF	interconnection networks, nanophotonics
25	Ian O'Connor	Optical solutions for system-level interconnect.	SLIP	2004	DBLP DOI BibTeX RDF	interconnect technology, optical network on chip, optical interconnect
25	Louis Scheffer	Explicit computation of performance as a function of process variation.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	static timing, process variation, yield, statistical timing
24	Md. Sajjad Rahaman, Masud H. Chowdhury	Time diversity approach for intra-chip RF/wireless interconnect systems.	ISCAS	2008	DBLP DOI BibTeX RDF
24	Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama	Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer.	ISMVL	2005	DBLP DOI BibTeX RDF
23	Shirish Bahirat, Sudeep Pasricha	Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	photonic interconnect, network-on-chip, chip multiprocessor
23	Assaf Shacham, Keren Bergman, Luca P. Carloni	Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
23	Michele Petracca, Keren Bergman, Luca P. Carloni	Photonic networks-on-chip: Opportunities and challenges.	ISCAS	2008	DBLP DOI BibTeX RDF
22	D. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama	Correlation method of circuit-performance and technology fluctuations for improved design reliability.	ASP-DAC	2001	DBLP DOI BibTeX RDF
22	Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu	Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip.	IEICE Trans. Inf. Syst.	2014	DBLP DOI BibTeX RDF
22	Everton Alceu Carara	Serviços de comunicação diferenciados em sistemas multiprocessados em chip baseados em redes intra-chip.		2011	RDF
22	Xiaowen Wu, Yaoyao Ye, Wei Zhang 0012, Weichen Liu, Mahdi Nikdast, Xuan Wang 0001, Jiang Xu 0001	UNION: A unified inter/intra-chip optical network for chip multiprocessors.	NANOARCH	2010	DBLP DOI BibTeX RDF
22	Phi-Hung Pham, Phuong Mau, Chulwoo Kim	A 64-PE folded-torus intra-chip communication fabric for guaranteed throughput in Network-on-Chip based applications.	CICC	2009	DBLP DOI BibTeX RDF
22	Kenichi Okada, Hidetoshi Onodera	Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2003	DBLP BibTeX RDF
22	Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera	A statistical gate delay model for intra-chip and inter-chip variabilities.	ASP-DAC	2003	DBLP DOI BibTeX RDF
22	Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera	Statistical modeling of gate-delay variation with consideration of intra-gate variability.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
19	Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi	VLSI architecture based on packet data transfer scheme and its application.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
17	Dan Zhao 0001, Yi Wang 0007	MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
17	Chun-Lung Hsu, Chang-Hsin Cheng, Yu-Sheng Huang, Chih-Jung Chen	An Adaptive Low-Power Control Scheme for On-Chip Network Applications.	APCCAS	2006	DBLP DOI BibTeX RDF
17	Dan Zhao 0001, Shambhu J. Upadhyaya, Martin Margala	Control Constrained Resource Partitioning for Complex SoCs.	DFT	2003	DBLP DOI BibTeX RDF
16	George Almási 0001, Eduard Ayguadé, Calin Cascaval, José G. Castaños, Jesús Labarta, Francisco Martínez, Xavier Martorell, José E. Moreira	Evaluation of OpenMP for the Cyclops Multithreaded Architecture.	WOMPAT	2003	DBLP DOI BibTeX RDF
16	Fan Jiang, Min Lin 0002, Xiao Chen, Lei Zhang, Xuyang Sheng	A Novel Low Power High Speed Gbps UWB Transmitter Design Using Fractional DTC and High Spectrum Efficiency Intra-Chip PPM.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
16	Marco Eppenberger, Mattia Bonomi, David Moor, Marco Mueller, Bertold Ian Bitachon, Thomas Burger, Luca Alloatti	10Gb/s Intra-Chip Compact Electro-Optical Interconnect.	OFC	2021	DBLP BibTeX RDF
16	Xavier Timoneda, Sergi Abadal, Antonio Franques, Dionysios Manessis, Jin Zhou 0001, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio	Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication.	IEEE Trans. Commun.	2020	DBLP DOI BibTeX RDF
16	Mohammadreza F. Imani, Sergi Abadal, Philipp del Hougne	Toward Dynamically Adapting Wireless Intra-Chip Channels to Traffic Needs with a Programmable Metasurface.	NanoCoCoA@SenSys	2020	DBLP DOI BibTeX RDF
16	Qian Chen 0027, Chirn Chye Boon, Xueyong Zhang, Chenyang Li, Yuan Liang, Zhe Liu 0038, Ting Guo	Multi-Channel FSK Inter/Intra-Chip Communication by Exploiting Field-Confined Slow-Wave Transmission Line.	ISCAS	2020	DBLP DOI BibTeX RDF
16	Luan H. K. Duong, Peng Yang 0003, Zhifei Wang, Yi-Shing Chang, Jiang Xu 0001, Zhehui Wang, Xuanqi Chen	Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
16	Xavier Timoneda, Sergi Abadal, Antonio Franques, Dionysios Manessis, Jin Zhou 0001, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio	Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication.	CoRR	2019	DBLP BibTeX RDF
16	Peng Yang 0003, Zhengbin Pang, Zhifei Wang, Zhehui Wang, Min Xie, Xuanqi Chen, Luan H. K. Duong, Jiang Xu 0001	RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems.	DATE	2018	DBLP DOI BibTeX RDF
16	Tanmay Shinde, Suryanarayanan Subramaniam, Padmanabh Deshmukh, M. Meraj Ahmed, Mark A. Indovina, Amlan Ganguly	A 0.24pJ/bit, 16Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects.	ACM Great Lakes Symposium on VLSI	2018	DBLP DOI BibTeX RDF
16	Vitaly Petrov, Dmitri Moltchanov, Maria Komar, Alexander Antonov, Pavel Kustarev, Shaloo Rakheja, Yevgeni Koucheryavy	Terahertz Band Intra-Chip Communications: Can Wireless Links Scale Modern x86 CPUs?	IEEE Access	2017	DBLP DOI BibTeX RDF
16	Md Shahriar Shamim, Naseef Mansoor, Rounak Singh Narde, Vignesh Kothandapani, Amlan Ganguly, Jayanti Venkataraman	A Wireless Interconnection Framework for Seamless Inter and Intra-Chip Communication in Multichip Systems.	IEEE Trans. Computers	2017	DBLP DOI BibTeX RDF
16	Muhammad Sana Ullah, Abdullah G. Alharbi, Masud H. Chowdhury	BPSK modulation based exact BER computation for network intra-chip RF interconnect.	ICM	2017	DBLP DOI BibTeX RDF
16	Amlan Ganguly, Naseef Mansoor, Md Shahriar Shamim, M. Meraj Ahmed, Rounak Singh Narde, Abhishek Vashist, Jayanti Venkataraman	Intra-chip Wireless Interconnect: The Road Ahead.	NoCArc@MICRO	2017	DBLP DOI BibTeX RDF
16	Sagar Saxena, Deekshith Shenoy Manur, M. Meraj Ahmed, Amlan Ganguly	Energy-efficiency in interconnection fabrics for inter and intra-chip communication using Graphene-based THz-band antennas.	IGSC	2017	DBLP DOI BibTeX RDF
16	Suryanarayanan Subramaniam, Tanmay Shinde, Padmanabh Deshmukh, Md Shahriar Shamim, Mark A. Indovina, Amlan Ganguly	A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects.	SoCC	2017	DBLP DOI BibTeX RDF
16	Zhehui Wang, Zhengbin Pang, Peng Yang 0003, Jiang Xu 0001, Xuanqi Chen, Rafael K. V. Maeda, Zhifei Wang, Luan H. K. Duong, Haoran Li 0002, Zhe Wang 0003	MOCA: an Inter/Intra-Chip Optical Network for Memory.	DAC	2017	DBLP DOI BibTeX RDF
16	Zhehui Wang, Jiang Xu 0001, Peng Yang 0003, Luan Huu Kinh Duong, Zhifei Wang, Xuan Wang 0001, Zhe Wang 0003, Haoran Li 0002, Rafael Kioji Vivas Maeda	A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
16	Hesam Shabani, Arman Roohi, Akram Reza, Midia Reshadi, Nader Bagherzadeh, Ronald F. DeMara	Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
16	Peng Yang 0003, Shigeru Nakamura, Kenichiro Yashiki, Zhehui Wang, Luan H. K. Duong, Zhifei Wang, Xuanqi Chen, Yuichi Nakamura 0002, Jiang Xu 0001	Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations.	NOCS	2016	DBLP DOI BibTeX RDF
16	Naoto Sugaya, Masanori Natsui, Takahiro Hanyu	Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission.	ISMVL	2016	DBLP DOI BibTeX RDF
16	Jose Eduardo Chiarelli Bueno Filho, Jorge Luis Gonzalez Reano, Jiang Chau Wang	Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation.	SoCC	2016	DBLP DOI BibTeX RDF
16	Xiaowen Wu, Jiang Xu 0001, Yaoyao Ye, Xuan Wang 0001, Mahdi Nikdast, Zhehui Wang, Zhe Wang 0003	An Inter/Intra-Chip Optical Network for Manycore Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
16	Md Shahriar Shamim, Jagan Muralidharan, Amlan Ganguly	An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links.	NOCS	2015	DBLP DOI BibTeX RDF
16	Erman Timurdogan, Zhan Su 0001, Krishna T. Settaluri, Sen Lin, Sajjad Moazeni, Chen Sun 0003, Gerald Leake, Douglas D. Coolbaugh, Benjamin R. Moss, Michele Moresco, Vladimir Stojanovic, Michael R. Watts	An ultra low power 3D integrated intra-chip silicon electronic-photonic link.	OFC	2015	DBLP DOI BibTeX RDF
16	Mohamad Hamieh, Myriam Ariaudo, Sébastien Quintanel, Yves Louët	Sizing of the physical layer of a RF intra-chip communications.	ICECS	2014	DBLP DOI BibTeX RDF
16	Yassir Madhour, Michael Zervas, Gerd Schlottig, Thomas Brunschwiler, Yusuf Leblebici, John Richard Thome, Bruno Michel	Integration of intra chip stack fluidic cooling using thin-layer solder bonding.	3DIC	2013	DBLP DOI BibTeX RDF
16	Ghaith Tarawneh, Terrence S. T. Mak, Alex Yakovlev	Intra-chip physical parameter sensor for FPGAS using flip-flop metastability.	FPL	2012	DBLP DOI BibTeX RDF
16	Sergio Johann Filho	Suporte para aplicações dinâmicas em sistemas multiprocessados intra-chip homogêneos.		2012	RDF
16	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	Wave-pipelined intra-chip signaling for on-FPGA communications.	Integr.	2010	DBLP DOI BibTeX RDF
16	Md. Sajjad Rahaman, Masud H. Chowdhury	Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems.	Microelectron. J.	2010	DBLP DOI BibTeX RDF
16	Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini	3D NoCs - Unifying inter & intra chip communication.	ISCAS	2010	DBLP DOI BibTeX RDF
16	Ankit More, Baris Taskin	Leakage current analysis for intra-chip wireless interconnects.	ISQED	2010	DBLP DOI BibTeX RDF
16	Yo Ohtake, Naoya Onizawa, Takahiro Hanyu	High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme.	ISCAS	2009	DBLP DOI BibTeX RDF
16	Stas Polonsky, M. Bhushan, A. Gattiker, Alan J. Weger, Peilin Song	Photon emission microscopy of inter/intra chip device performance variations.	Microelectron. Reliab.	2005	DBLP DOI BibTeX RDF
16	Y. P. Zhang	Bit-error-rate performance of intra-chip wireless interconnect systems.	IEEE Commun. Lett.	2004	DBLP DOI BibTeX RDF
16	Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu	Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding.	ISMVL	2004	DBLP DOI BibTeX RDF
16	Anand Pappu, Alyssa B. Apsel	Electrical isolation and fanout in intra-chip optical interconnects.	ISCAS (2)	2004	DBLP BibTeX RDF
16	Brian A. Floyd, Chih-Ming Hung, Kenneth K. O	Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters.	IEEE J. Solid State Circuits	2002	DBLP DOI BibTeX RDF
16	Mau-Chung Frank Chang, Vwani P. Roychowdhury, Liyang Zhang, Hyunchol Shin, Yongxi Qian	RF/wireless interconnect for inter- and intra-chip communications.	Proc. IEEE	2001	DBLP DOI BibTeX RDF
16	Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Y. Tatsumi, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Terufumi Yamaguchi, Kyoji Yamashita, Noriaki Nakayama	Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability.	CICC	2001	DBLP DOI BibTeX RDF
16	Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu	Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits.	ICCAD	2000	DBLP DOI BibTeX RDF
16	Nobuyasu Kanekawa, Makoto Nohmi, Yoshimichi Satoh, Hiroshi Satoh	Self-Checking and Fail-Safe LSIs by Intra-Chip Redundancy.	FTCS	1996	DBLP DOI BibTeX RDF
14	Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran	Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Hongliang Chang, Sachin S. Sapatnekar	Full-chip analysis of leakage power under process variations, including spatial correlations.	DAC	2005	DBLP DOI BibTeX RDF
14	Calin Cascaval, José G. Castaños, Luis Ceze, Monty Denneau, Manish Gupta 0002, Derek Lieber, José E. Moreira, Karin Strauss, Henry S. Warren Jr.	Evaluation of a Multithreaded Architecture for Cellular Computing.	HPCA	2002	DBLP DOI BibTeX RDF
14	Stuart K. Tewksbury, Lawrence A. Hornak	Optical Clock Distribution in Electronic Systems.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
11	Cheng Wang 0013, Ho-Seop Kim, Youfeng Wu, Victor Ying	Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection.	CGO	2007	DBLP DOI BibTeX RDF
11	J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne	Analysis and modeling of power grid transmission lines.	DATE	2006	DBLP DOI BibTeX RDF
11	Min-An Song, Ting-Chun Huang, Sy-Yen Kuo	A Functional Verification Environment for Advanced Switching Architecture.	DELTA	2006	DBLP DOI BibTeX RDF
11	Salem Abdennadher, Saghir A. Shaikh	Challenges in High Speed Interface Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
11	Aline Mello 0001, Leandro Möller, Ney Calazans, Fernando Gehm Moraes	MultiNoC: A Multiprocessing System Enabled by a Network on Chip.	DATE	2004	DBLP DOI BibTeX RDF
11	Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm	An Adaptive Low-Power Transmission Scheme for On-Chip Networks.	ISSS	2002	DBLP DOI BibTeX RDF	low-power, systems-on-chip, networks-on-chip
11	Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto	CMOS Circuit Technology for Precise GHz Timing Generator.	ITC	2002	DBLP DOI BibTeX RDF
8	Hikmet Dursun, Ken-ichi Nomura, Liu Peng, Richard Seymour, Weiqiang Wang, Rajiv K. Kalia, Aiichiro Nakano, Priya Vashishta	A Multilevel Parallelization Framework for High-Order Stencil Computations.	Euro-Par	2009	DBLP DOI BibTeX RDF	single instruction multiple data parallelism, spatial decomposition, message passing, multithreading, Stencil computation
8	David E. Shaw	Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins.	MICRO	2008	DBLP DOI BibTeX RDF
8	Richard H. Larson, John K. Salmon, Ron O. Dror, Martin M. Deneroff, Cliff Young, J. P. Grossman, Yibing Shan, John L. Klepeis, David E. Shaw	High-throughput pairwise point interactions in Anton, a specialized machine for molecular dynamics simulation.	HPCA	2008	DBLP DOI BibTeX RDF
8	Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran	Fundamental Data Retention Limits in SRAM Standby Experimental Results.	ISQED	2008	DBLP DOI BibTeX RDF	standby, data retention, low power, SRAM, error control code
8	Steve Pawlowski	Petascale Computing Research Challenges - A Manycore Perspective.	HPCA	2007	DBLP DOI BibTeX RDF
8	Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim	Profile-guided microarchitectural floorplanning for deep submicron processor design.	DAC	2004	DBLP DOI BibTeX RDF	microarchitectural planning, computer architecture, floorplanning
8	Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu	Analytical Bound for Unwanted Clock Skew due to Wire Width Variation.	ICCAD	2003	DBLP DOI BibTeX RDF
8	Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi 0001	Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI.	ISMVL	2002	DBLP DOI BibTeX RDF	new paradigm computing, high-speed signaling, code-division multiple access, equalization, VLSI systems
8	Gregorio Cappuccino, Giuseppe Cocorullo	A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines.	EUROMICRO	1999	DBLP DOI BibTeX RDF