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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 27 occurrences of 24 keywords
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Results
Found 89 publication records. Showing 89 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
47 | Md. Sajjad Rahaman, Masud H. Chowdhury |
Improved ber performance in intra-chip rf/wireless interconnect systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 303-308, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
RF interconnect, intra-chip channel, wireless interconnect, interleaver, error control coding, channel coding |
39 | Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu 0016, Michael C. Huang 0001, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore |
An intra-chip free-space optical interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 94-105, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
free-space optical interconnect, intra-chip, 3d |
36 | Eli Yablonovitch |
Can nano-photonic silicon circuits become an INTRA-chip interconnect technology? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 309, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Claudio Favi, Edoardo Charbon |
Techniques for fully integrated intra-/inter-chip optical communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 343-344, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
intra-chip & inter-chip communication, low power optical communication, miniaturized optical channel and detector |
32 | Louis Scheffer |
An overview of on-chip interconnect variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 27-28, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
causes of variability, on-chip variation, design rules |
29 | Walker J. Turner, John W. Poulton, John M. Wilson 0002, Xi Chen 0033, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray |
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, CA, USA, April 8-11, 2018, pp. 1-8, 2018, IEEE, 978-1-5386-2483-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
26 | Pranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy |
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 117-128, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
interconnection networks, nanophotonics |
25 | Ian O'Connor |
Optical solutions for system-level interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 79-88, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect technology, optical network on chip, optical interconnect |
25 | Louis Scheffer |
Explicit computation of performance as a function of process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 1-8, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
static timing, process variation, yield, statistical timing |
24 | Md. Sajjad Rahaman, Masud H. Chowdhury |
Time diversity approach for intra-chip RF/wireless interconnect systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2434-2437, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama |
Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 18-21 May 2005, Calgary, Canada, pp. 114-119, 2005, IEEE Computer Society, 0-7695-2336-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Shirish Bahirat, Sudeep Pasricha |
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 129-136, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
photonic interconnect, network-on-chip, chip multiprocessor |
23 | Assaf Shacham, Keren Bergman, Luca P. Carloni |
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(9), pp. 1246-1260, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Michele Petracca, Keren Bergman, Luca P. Carloni |
Photonic networks-on-chip: Opportunities and challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2789-2792, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | D. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama |
Correlation method of circuit-performance and technology fluctuations for improved design reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 39-44, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu |
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Inf. Syst. ![In: IEICE Trans. Inf. Syst. 97-D(9), pp. 2304-2311, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
22 | Everton Alceu Carara |
Serviços de comunicação diferenciados em sistemas multiprocessados em chip baseados em redes intra-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2011 |
RDF |
|
22 | Xiaowen Wu, Yaoyao Ye, Wei Zhang 0012, Weichen Liu, Mahdi Nikdast, Xuan Wang 0001, Jiang Xu 0001 |
UNION: A unified inter/intra-chip optical network for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, USA, June 17-18, 2010, pp. 35-40, 2010, IEEE Computer Society, 978-1-4244-8020-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
22 | Phi-Hung Pham, Phuong Mau, Chulwoo Kim |
A 64-PE folded-torus intra-chip communication fabric for guaranteed throughput in Network-on-Chip based applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: IEEE Custom Integrated Circuits Conference, CICC 2009, San Jose, California, USA, 13-16 September, 2009, Proceedings, pp. 645-648, 2009, IEEE, 978-1-4244-4071-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Kenichi Okada, Hidetoshi Onodera |
Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(4), pp. 746-751, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
22 | Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera |
A statistical gate delay model for intra-chip and inter-chip variabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 31-36, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera |
Statistical modeling of gate-delay variation with consideration of intra-gate variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 513-516, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi |
VLSI architecture based on packet data transfer scheme and its application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1786-1789, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Dan Zhao 0001, Yi Wang 0007 |
MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(8), pp. 1046-1057, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Chun-Lung Hsu, Chang-Hsin Cheng, Yu-Sheng Huang, Chih-Jung Chen |
An Adaptive Low-Power Control Scheme for On-Chip Network Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 113-118, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Dan Zhao 0001, Shambhu J. Upadhyaya, Martin Margala |
Control Constrained Resource Partitioning for Complex SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 425-432, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | George Almási 0001, Eduard Ayguadé, Calin Cascaval, José G. Castaños, Jesús Labarta, Francisco Martínez, Xavier Martorell, José E. Moreira |
Evaluation of OpenMP for the Cyclops Multithreaded Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WOMPAT ![In: OpenMP Shared Memory Parallel Programming, International Workshop on OpenMP Applications and Tools, WOMPAT 2003, Toronto, Canada, June 26-27, 2003, Proceedings, pp. 69-83, 2003, Springer, 3-540-40435-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Fan Jiang, Min Lin 0002, Xiao Chen, Lei Zhang, Xuyang Sheng |
A Novel Low Power High Speed Gbps UWB Transmitter Design Using Fractional DTC and High Spectrum Efficiency Intra-Chip PPM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 71(1), pp. 111-115, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Marco Eppenberger, Mattia Bonomi, David Moor, Marco Mueller, Bertold Ian Bitachon, Thomas Burger, Luca Alloatti |
10Gb/s Intra-Chip Compact Electro-Optical Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OFC ![In: Optical Fiber Communications Conference and Exhibition, OFC 2021, San Francisco, CA, USA, June 6-10, 2021, pp. 1-3, 2021, IEEE, 978-1-943580-86-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
16 | Xavier Timoneda, Sergi Abadal, Antonio Franques, Dionysios Manessis, Jin Zhou 0001, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio |
Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 68(5), pp. 3247-3258, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Mohammadreza F. Imani, Sergi Abadal, Philipp del Hougne |
Toward Dynamically Adapting Wireless Intra-Chip Channels to Traffic Needs with a Programmable Metasurface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoCoCoA@SenSys ![In: NanoCoCoA@SenSys '20: Proceedings of the 1st ACM International Workshop on Nanoscale Computing, Communication, and Application, Virtual Event, Japan, November, 2020, pp. 20-25, 2020, ACM, 978-1-4503-8116-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Qian Chen 0027, Chirn Chye Boon, Xueyong Zhang, Chenyang Li, Yuan Liang, Zhe Liu 0038, Ting Guo |
Multi-Channel FSK Inter/Intra-Chip Communication by Exploiting Field-Confined Slow-Wave Transmission Line. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Luan H. K. Duong, Peng Yang 0003, Zhifei Wang, Yi-Shing Chang, Jiang Xu 0001, Zhehui Wang, Xuanqi Chen |
Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1), pp. 43-56, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Xavier Timoneda, Sergi Abadal, Antonio Franques, Dionysios Manessis, Jin Zhou 0001, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio |
Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1901.04291, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
16 | Peng Yang 0003, Zhengbin Pang, Zhifei Wang, Zhehui Wang, Min Xie, Xuanqi Chen, Luan H. K. Duong, Jiang Xu 0001 |
RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 1369-1374, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Tanmay Shinde, Suryanarayanan Subramaniam, Padmanabh Deshmukh, M. Meraj Ahmed, Mark A. Indovina, Amlan Ganguly |
A 0.24pJ/bit, 16Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018, pp. 69-74, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Vitaly Petrov, Dmitri Moltchanov, Maria Komar, Alexander Antonov, Pavel Kustarev, Shaloo Rakheja, Yevgeni Koucheryavy |
Terahertz Band Intra-Chip Communications: Can Wireless Links Scale Modern x86 CPUs? ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 5, pp. 6095-6109, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Md Shahriar Shamim, Naseef Mansoor, Rounak Singh Narde, Vignesh Kothandapani, Amlan Ganguly, Jayanti Venkataraman |
A Wireless Interconnection Framework for Seamless Inter and Intra-Chip Communication in Multichip Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(3), pp. 389-402, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Muhammad Sana Ullah, Abdullah G. Alharbi, Masud H. Chowdhury |
BPSK modulation based exact BER computation for network intra-chip RF interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 29th International Conference on Microelectronics, ICM 2017, Beirut, Lebanon, December 10-13, 2017, pp. 1-4, 2017, IEEE, 978-1-5386-4049-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Amlan Ganguly, Naseef Mansoor, Md Shahriar Shamim, M. Meraj Ahmed, Rounak Singh Narde, Abhishek Vashist, Jayanti Venkataraman |
Intra-chip Wireless Interconnect: The Road Ahead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NoCArc@MICRO ![In: Proceedings of the 10th International Workshop on Network on Chip Architectures, NoCArc@MICRO 2017, Cambridge, MA, USA, October 14-18, 2017, pp. 3:1-3:6, 2017, ACM, 978-1-4503-5542-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Sagar Saxena, Deekshith Shenoy Manur, M. Meraj Ahmed, Amlan Ganguly |
Energy-efficiency in interconnection fabrics for inter and intra-chip communication using Graphene-based THz-band antennas. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IGSC ![In: Eighth International Green and Sustainable Computing Conference, IGSC 2017, Orlando, FL, USA, October 23-25, 2017, pp. 1-6, 2017, IEEE Computer Society, 978-1-5386-3470-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Suryanarayanan Subramaniam, Tanmay Shinde, Padmanabh Deshmukh, Md Shahriar Shamim, Mark A. Indovina, Amlan Ganguly |
A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017, pp. 132-137, 2017, IEEE, 978-1-5386-4034-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Zhehui Wang, Zhengbin Pang, Peng Yang 0003, Jiang Xu 0001, Xuanqi Chen, Rafael K. V. Maeda, Zhifei Wang, Luan H. K. Duong, Haoran Li 0002, Zhe Wang 0003 |
MOCA: an Inter/Intra-Chip Optical Network for Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017, pp. 86:1-86:6, 2017, ACM, 978-1-4503-4927-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Zhehui Wang, Jiang Xu 0001, Peng Yang 0003, Luan Huu Kinh Duong, Zhifei Wang, Xuan Wang 0001, Zhe Wang 0003, Haoran Li 0002, Rafael Kioji Vivas Maeda |
A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(7), pp. 2462-2474, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Hesam Shabani, Arman Roohi, Akram Reza, Midia Reshadi, Nader Bagherzadeh, Ronald F. DeMara |
Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 65(6), pp. 1789-1801, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Peng Yang 0003, Shigeru Nakamura, Kenichiro Yashiki, Zhehui Wang, Luan H. K. Duong, Zhifei Wang, Xuanqi Chen, Yuichi Nakamura 0002, Jiang Xu 0001 |
Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Tenth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016, Nara, Japan, August 31 - September 2, 2016, pp. 1-8, 2016, IEEE, 978-1-4673-9030-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Naoto Sugaya, Masanori Natsui, Takahiro Hanyu |
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 46th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2016, Sapporo, Japan, May 18-20, 2016, pp. 72-77, 2016, IEEE Computer Society, 978-1-4673-9489-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Jose Eduardo Chiarelli Bueno Filho, Jorge Luis Gonzalez Reano, Jiang Chau Wang |
Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016, pp. 41-46, 2016, IEEE, 978-1-5090-1367-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Xiaowen Wu, Jiang Xu 0001, Yaoyao Ye, Xuan Wang 0001, Mahdi Nikdast, Zhehui Wang, Zhe Wang 0003 |
An Inter/Intra-Chip Optical Network for Manycore Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(4), pp. 678-691, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Md Shahriar Shamim, Jagan Muralidharan, Amlan Ganguly |
An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015, pp. 2:1-2:8, 2015, ACM, 978-1-4503-3396-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Erman Timurdogan, Zhan Su 0001, Krishna T. Settaluri, Sen Lin, Sajjad Moazeni, Chen Sun 0003, Gerald Leake, Douglas D. Coolbaugh, Benjamin R. Moss, Michele Moresco, Vladimir Stojanovic, Michael R. Watts |
An ultra low power 3D integrated intra-chip silicon electronic-photonic link. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OFC ![In: Optical Fiber Communications Conference and Exhibition, OFC 2015, Los Angeles, CA, USA, March 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-5575-2937-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Mohamad Hamieh, Myriam Ariaudo, Sébastien Quintanel, Yves Louët |
Sizing of the physical layer of a RF intra-chip communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, pp. 163-166, 2014, IEEE, 978-1-4799-4242-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Yassir Madhour, Michael Zervas, Gerd Schlottig, Thomas Brunschwiler, Yusuf Leblebici, John Richard Thome, Bruno Michel |
Integration of intra chip stack fluidic cooling using thin-layer solder bonding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
3DIC ![In: 2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA, USA, October 2-4, 2013, pp. 1-8, 2013, IEEE, 978-1-4673-6484-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Ghaith Tarawneh, Terrence S. T. Mak, Alex Yakovlev |
Intra-chip physical parameter sensor for FPGAS using flip-flop metastability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012, pp. 373-379, 2012, IEEE, 978-1-4673-2257-7. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Sergio Johann Filho |
Suporte para aplicações dinâmicas em sistemas multiprocessados intra-chip homogêneos. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2012 |
RDF |
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16 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
Wave-pipelined intra-chip signaling for on-FPGA communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 43(2), pp. 188-201, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Md. Sajjad Rahaman, Masud H. Chowdhury |
Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 41(1), pp. 33-40, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini |
3D NoCs - Unifying inter & intra chip communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 3337-3340, 2010, IEEE, 978-1-4244-5308-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Ankit More, Baris Taskin |
Leakage current analysis for intra-chip wireless interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 11th International Symposium on Quality of Electronic Design (ISQED 2010), 22-24 March 2010, San Jose, CA, USA, pp. 49-53, 2010, IEEE, 978-1-4244-6455-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
16 | Yo Ohtake, Naoya Onizawa, Takahiro Hanyu |
High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 1000-1003, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Stas Polonsky, M. Bhushan, A. Gattiker, Alan J. Weger, Peilin Song |
Photon emission microscopy of inter/intra chip device performance variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 45(9-11), pp. 1471-1475, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Y. P. Zhang |
Bit-error-rate performance of intra-chip wireless interconnect systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Commun. Lett. ![In: IEEE Commun. Lett. 8(1), pp. 39-41, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu |
Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada, pp. 192-197, 2004, IEEE Computer Society, 0-7695-2130-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Anand Pappu, Alyssa B. Apsel |
Electrical isolation and fanout in intra-chip optical interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 533-536, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
16 | Brian A. Floyd, Chih-Ming Hung, Kenneth K. O |
Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 37(5), pp. 543-552, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Mau-Chung Frank Chang, Vwani P. Roychowdhury, Liyang Zhang, Hyunchol Shin, Yongxi Qian |
RF/wireless interconnect for inter- and intra-chip communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 89(4), pp. 456-466, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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16 | Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Y. Tatsumi, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Terufumi Yamaguchi, Kyoji Yamashita, Noriaki Nakayama |
Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, CICC 2001, San Diego, CA, USA, May 6-9, 2001, pp. 357-360, 2001, IEEE, 0-7803-6591-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu |
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000, pp. 62-67, 2000, IEEE Computer Society, 0-7803-6448-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Nobuyasu Kanekawa, Makoto Nohmi, Yoshimichi Satoh, Hiroshi Satoh |
Self-Checking and Fail-Safe LSIs by Intra-Chip Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FTCS ![In: Digest of Papers: FTCS-26, The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing, Sendai, Japan, June 25-27, 1996, pp. 426-430, 1996, IEEE Computer Society, 0-8186-7261-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
14 | Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran |
Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1867-1870, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Hongliang Chang, Sachin S. Sapatnekar |
Full-chip analysis of leakage power under process variations, including spatial correlations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 523-528, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Calin Cascaval, José G. Castaños, Luis Ceze, Monty Denneau, Manish Gupta 0002, Derek Lieber, José E. Moreira, Karin Strauss, Henry S. Warren Jr. |
Evaluation of a Multithreaded Architecture for Cellular Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 311-322, 2002, IEEE Computer Society, 0-7695-1525-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Stuart K. Tewksbury, Lawrence A. Hornak |
Optical Clock Distribution in Electronic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 16(2-3), pp. 225-246, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
11 | Cheng Wang 0013, Ho-Seop Kim, Youfeng Wu, Victor Ying |
Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: Fifth International Symposium on Code Generation and Optimization (CGO 2007), 11-14 March 2007, San Jose, California, USA, pp. 244-258, 2007, IEEE Computer Society, 978-0-7695-2764-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne |
Analysis and modeling of power grid transmission lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 33-38, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Min-An Song, Ting-Chun Huang, Sy-Yen Kuo |
A Functional Verification Environment for Advanced Switching Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 201-204, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Salem Abdennadher, Saghir A. Shaikh |
Challenges in High Speed Interface Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 468, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Aline Mello 0001, Leandro Möller, Ney Calazans, Fernando Gehm Moraes |
MultiNoC: A Multiprocessing System Enabled by a Network on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 234-239, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm |
An Adaptive Low-Power Transmission Scheme for On-Chip Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 92-100, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
low-power, systems-on-chip, networks-on-chip |
11 | Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto |
CMOS Circuit Technology for Precise GHz Timing Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 894-902, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
8 | Hikmet Dursun, Ken-ichi Nomura, Liu Peng, Richard Seymour, Weiqiang Wang, Rajiv K. Kalia, Aiichiro Nakano, Priya Vashishta |
A Multilevel Parallelization Framework for High-Order Stencil Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2009 Parallel Processing, 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009. Proceedings, pp. 642-653, 2009, Springer, 978-3-642-03868-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
single instruction multiple data parallelism, spatial decomposition, message passing, multithreading, Stencil computation |
8 | David E. Shaw |
Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteins. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Richard H. Larson, John K. Salmon, Ron O. Dror, Martin M. Deneroff, Cliff Young, J. P. Grossman, Yibing Shan, John L. Klepeis, David E. Shaw |
High-throughput pairwise point interactions in Anton, a specialized machine for molecular dynamics simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 331-342, 2008, IEEE Computer Society, 978-1-4244-2070-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran |
Fundamental Data Retention Limits in SRAM Standby Experimental Results. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 92-97, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
standby, data retention, low power, SRAM, error control code |
8 | Steve Pawlowski |
Petascale Computing Research Challenges - A Manycore Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 96, 2007, IEEE Computer Society, 1-4244-0804-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim |
Profile-guided microarchitectural floorplanning for deep submicron processor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 634-639, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
microarchitectural planning, computer architecture, floorplanning |
8 | Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu |
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 401-407, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
8 | Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi 0001 |
Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, pp. 54-60, 2002, IEEE Computer Society, 0-7695-1462-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
new paradigm computing, high-speed signaling, code-division multiple access, equalization, VLSI systems |
8 | Gregorio Cappuccino, Giuseppe Cocorullo |
A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1204-1208, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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