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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 114 occurrences of 71 keywords
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Results
Found 369 publication records. Showing 369 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
178 | David T. Blaauw, Anirudh Devgan, Farid N. Najm |
Leakage power: trends, analysis and avoidance. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
111 | Nikhil Jayakumar, Sunil P. Khatri |
A Predictably Low-Leakage ASIC Design Style. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
87 | Nikhil Jayakumar, Sunil P. Khatri |
An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
standby current, leakage current, standard cells, MTCMOS |
76 | Jason Helge Anderson, Farid N. Najm |
Active leakage power optimization for FPGAs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
65 | Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen |
Cache leakage control mechanism for hard real-time systems. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
cache leakage control policy, hard real-time system |
64 | Kamal S. Khouri, Niraj K. Jha |
Leakage power analysis and reduction during behavioral synthesis. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
63 | Shengqi Yang, Wayne H. Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie 0001 |
Low-leakage robust SRAM cell design for sub-100nm technologies. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
59 | Min Ni, Seda Ogrenci Memik |
Thermal-induced leakage power optimization by redundant resource allocation. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
58 | Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001 |
Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
52 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001 |
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
Behavioral synthesis of datapaths with low leakage power. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
52 | Jun-Cheol Park, Vincent John Mooney III |
Sleepy Stack Leakage Reduction. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Micah G. O'Halloran, Rahul Sarpeshkar |
An analog storage cell with 5e-/sec leakage. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
50 | Kamal S. Khouri, Niraj K. Jha |
Leakage Power Analysis and Reduction during Behavioral Synthesis. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
50 | Kwang-Il Oh, Seunghyun Cho, Lee-Sup Kim |
A low power SoC bus with low-leakage and low-swing technique. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Arifur Rahman, Vijay Polavarapuv |
Evaluation of low-leakage design techniques for field programmable gate arrays. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
FPGA, leakage power, multiplexer |
45 | Volkan Kursun, Zhiyu Liu |
Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy 0001 |
A forward body-biased low-leakage SRAM cache: device and architecture considerations. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
forward body-biasing, super high VT, SRAM, leakage power |
45 | David Scott, Shaoping Tang, Song Zhao, Mahalingam Nandakumar |
Device Physics Impact on Low Leakage, High Speed DSP Design Techniques (invited). |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
standby, GIDL, leakage, tunneling, subthreshold, current |
44 | Jun Seomun, Jae-Hyun Kim, Youngsoo Shin |
Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Wei Zhang 0002, Bramha Allu |
Reducing branch predictor leakage energy by exploiting loops. |
ACM Trans. Embed. Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
compiler, Branch prediction, leakage energy |
44 | Wei Zhang 0002, Bramha Allu |
Loop-based leakage control for branch predictors. |
CASES |
2004 |
DBLP DOI BibTeX RDF |
compiler, branch prediction, leakage energy |
42 | Rajiv V. Joshi, Kaushik Roy 0001 |
Design of Deep Sub-Micron CMOS Circuits. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Zhiyu Liu, Volkan Kursun |
Leakage Biased Sleep Switch Domino Logic. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
gate oxide tunneling, sleep mode, Domino logic, subthreshold leakage current, dual threshold voltage |
39 | Nasir Mohyuddin, Rashed Zafar Bhatti, Michel Dubois 0001 |
Controlling leakage power with the replacement policy in slumberous caches. |
Conf. Computing Frontiers |
2005 |
DBLP DOI BibTeX RDF |
tranquility level, leakage power, replacement policy, drowsy cache |
39 | Nam Sung Kim, Krisztián Flautner, David T. Blaauw, Trevor N. Mudge |
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
38 | Shilpa Bhoj, Dinesh Bhatia |
Early stage FPGA interconnect leakage power estimation. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
38 | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Optimal sleep transistor synthesis under timing and area constraints. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
row-based, clustering, leakage power, power-gating, standard cell, sleep transistor |
38 | Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry |
Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing |
An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. |
Asia-Pacific Computer Systems Architecture Conference |
2006 |
DBLP DOI BibTeX RDF |
Periodically Drowsy Speculative Recover, Adaptive, Leakage Power, Drowsy cache |
38 | Jun-Cheol Park, Vincent John Mooney III |
Pareto Points in SRAM Design Using the Sleepy Stack Approach. |
VLSI-SoC |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger |
Sleepy Stack Reduction of Leakage Power. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Mohan G. Kabadi, Ranjani Parthasarathi |
Live-Cache: Exploiting Data Redundancy to Reduce Leakage Energy in a Cache Subsystem. |
Asia-Pacific Computer Systems Architecture Conference |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman |
Managing static leakage energy in microprocessor functional units. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Zhiyu Liu, Volkan Kursun |
PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
Tabu Search Based Behavioral Synthesis of Low Leakage Datapaths. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Vikas Kaushal, Quentin Diduck, Martin Margala |
Study of leakage current mechanisms in ballistic deflection transistors. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
ballistic transport, current leakage mechanism, deflection transistors, silvaco simulation, geometry, monte carlo simulation |
33 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum |
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors. |
CASES |
2008 |
DBLP DOI BibTeX RDF |
multiple sleep mode, peripheral circuits, cache, embedded processor, leakage power |
33 | Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001 |
Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
process variation, yield, leakage, dual-Vt, metal gate |
33 | A. S. Seyedi, S. H. Rasouli, Amir Amirabadi, Ali Afzali-Kusha |
Low power low leakage clock gated static pulsed flip-flop. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Tadayoshi Enomoto, Yuki Higuchi |
A low-leakage current power 180-nm CMOS SRAM. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Behnam Amelifard, Massoud Pedram, Farzan Fallah |
Low-leakage SRAM Design with Dual V_t Transistors. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Lei Cheng 0001, Deming Chen, Martin D. F. Wong |
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Input vector control, gate replacement, leakage reduction |
32 | Yousra Alkabani, Tammara Massey, Farinaz Koushanfar, Miodrag Potkonjak |
Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
input vector control, low power, manufacturing variability |
32 | Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos |
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Lei Cheng 0001, Liang Deng, Deming Chen, Martin D. F. Wong |
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
gate replacement, input vector control, leakage reduction |
32 | Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy 0001 |
Leakage control with efficient use of transistor stacks in single threshold CMOS. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Andrea Lodi 0002, Luca Ciccarelli, Roberto Giansante |
Combining low-leakage techniques for FPGA routing design. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
low leakage, FPGA, power |
32 | Navid Azizi, Andreas Moshovos, Farid N. Najm |
Low-leakage asymmetric-cell SRAM. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
low-leakage, low-power, SRAM, dual-Vt |
31 | Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri |
A Single-supply True Voltage Level Shifter. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Ehsan Pakbaznia, Massoud Pedram |
Design and application of multimodal power gating structures. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou |
SRAM Cell Current in Low Leakage Design. |
MTDT |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan M. Rabaey |
SRAM Leakage Suppression by Minimizing Standby Supply Voltage. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Chandra S. Nagarajan, Lin Yuan, Gang Qu 0001, Barbara G. Stamps |
Leakage optimization using transistor-level dual threshold voltage cell library. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue |
Improved Policies for Drowsy Caches in Embedded Processors. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
Low Power Cache Design, Leakage Energy, Drowsy Cache |
27 | Olga Golubeva, Mirko Loghi, Massimo Poncino, Enrico Macii |
Architectural leakage-aware management of partitioned scratchpad memories. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang |
Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
FD/SOI, low-power, stability, SRAM |
27 | Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril |
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Mahmut T. Kandemir, Mary Jane Irwin, Guangyu Chen, Ibrahim Kolcu |
Compiler-guided leakage optimization for banked scratch-pad memories. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin |
Reducing instruction cache energy consumption using a compiler-based strategy. |
ACM Trans. Archit. Code Optim. |
2004 |
DBLP DOI BibTeX RDF |
compiler optimizations, Leakage power, cache design |
27 | Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin |
Compiler-directed instruction cache leakage optimization. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Rahul M. Rao, Frank Liu 0001, Jeffrey L. Burns, Richard B. Brown |
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Anish Muttreja, Niket Agarwal, Niraj K. Jha |
CMOS logic design with independent-gate FinFETs. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu |
Leakage-Aware Design of Nanometer SoC. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Frank Sill, Frank Grassert, Dirk Timmermann |
Low power gate-level design with mixed-Vth (MVT) techniques. |
SBCCI |
2004 |
DBLP DOI BibTeX RDF |
MVT, leakage currents, threshold voltage |
24 | Yan Lin 0001, Fei Li 0003, Lei He 0001 |
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang |
Nanoscale CMOS circuit leakage power reduction by double-gate device. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
double-gate device, short-channel effect, leakage power |
22 | Liqiong Wei, Kaushik Roy 0001, Vivek De |
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
low voltage low power, multiple threshold voltages, multiple supply voltages and leakage control |
22 | Deepak Mittal |
SRAM Cell Leakage Reduction Methodologies for Low Leakage Cache Memories. |
ICCCNT |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Corentin Pochet, Haowei Jiang, Drew A. Hall |
Ultra-Low Leakage ESD Protection Achieving 10.5 fA Leakage. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Behnam Samadpoor Rikan, Hamed Abbasizadeh, Thi Kim Nga Truong, Sung Jin Kim, Kang-Yoon Lee |
A low leakage retention LDO and leakage-based BGR with 120nA quiescent current. |
ISOCC |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Weiqiang Zhang, Li Su, Yu Zhang, Linfeng Li, Jianping Hu |
Low-Leakage Flip-Flops Based on Dual-Threshold and Multiple Leakage Reduction Techniques. |
J. Circuits Syst. Comput. |
2011 |
DBLP DOI BibTeX RDF |
|
22 | Kawori Takakubo, Toru Eto, Hajime Takakubo |
Analysis and Modeling of Leakage Current for Four-Terminal MOSFET in Off-State and Low Leakage Switches. |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada |
A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. |
IEEE J. Solid State Circuits |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Amit Agarwal 0001, Kaushik Roy 0001, Ram K. Krishnamurthy |
A leakage-tolerant low-leakage register file with conditional sleep transistor. |
SoCC |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny |
Low-leakage repeaters for NoC interconnects. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark |
LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, Ibrahim Kolcu |
Banked scratch-pad memory management for reducing leakage energy consumption. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Krisztián Flautner, Nam Sung Kim, Steven M. Martin, David T. Blaauw, Trevor N. Mudge |
Drowsy Caches: Simple Techniques for Reducing Leakage Power. |
ISCA |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Marco Bucci, Raimondo Luzzi, Santos Torres Vargas |
A Low Leakage Non-Volatile Memory Voltage Pulse Generator for RFID Applications. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry |
A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Juan M. Cebrian, Juan L. Aragón, José M. García 0001 |
Leakage Energy Reduction in Value Predictors through Static Decay. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta |
Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
Leakage energy reduction techniques in deep submicron cache memories: a comparative study. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino |
STV-Cache: a leakage energy-efficient architecture for data caches. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
architecture, caches, leakage power |
20 | Karthik Sankaranarayanan, Kevin Skadron |
Profile-based adaptation for cache decay. |
ACM Trans. Archit. Code Optim. |
2004 |
DBLP DOI BibTeX RDF |
Adaptation, leakage power, interval, cache decay |
20 | Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger |
Static energy reduction techniques for microprocessor caches. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Qi Wang, Sarma B. K. Vrudhula |
An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
low power, CMOS circuits, dual Vt |
20 | Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin |
A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. |
SoCC |
2018 |
DBLP DOI BibTeX RDF |
|
19 | Amit Agarwal 0001, Kaushik Roy 0001 |
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
diode, low leakage cache, SRAM, gate leakage |
19 | Amit Agarwal 0001, Hai Li, Kaushik Roy 0001 |
DRG-cache: a data retention gated-ground cache for low power. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
gated-ground, low leakage cache, SRAM |
16 | Andrea Calimera, Enrico Macii, Massimo Poncino |
NBTI-aware power gating for concurrent leakage and aging optimization. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
aging, leakage, power-gating, nbti |
16 | David Fitrio, Aleksandar Stojcevski, Jugdutt Singh |
Ultra Low Power Weak Inversion Current Steered Digital to Analog Converter. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | A. Madan, S. C. Bose, P. J. George, Chandra Shekhar 0001 |
Evaluation of Device Parameters of HfO2/SiO2/Si Gate Dielectric Stack for MOSFETs. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
Direct Tunneling, gate leakage current, high-K gate stack, MOSFETs |
16 | M. Elangovan, Kulbhushan Sharma, Ashish Sachdeva, Lipika Gupta |
Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications. |
Circuits Syst. Signal Process. |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Ang Yuan, Huidong Zhao, Xiao Wang, Zhi Li, Shushan Qiao |
An Ultra-Low Leakage and Wide-Range Voltage Level Shifter for Low-Power Digital CMOS VLSIs. |
IEEE Trans. Circuits Syst. II Express Briefs |
2024 |
DBLP DOI BibTeX RDF |
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