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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1754 occurrences of 998 keywords
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Results
Found 2330 publication records. Showing 2330 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
59 | Bernard J. Carey, George F. MacLachlan |
Automated design based upon Microprogrammable Bit Slice Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 20-24, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
55 | Masatoshi Shima 0001 |
The Birth, Evolution and Future of the Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Fifth International Conference on Computer and Information Technology (CIT 2005), 21-23 September 2005, Shanghai, China, pp. 2, 2005, IEEE Computer Society, 0-7695-2432-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Anthony C. J. Fox, Neal A. Harman |
Algebraic Models of Correctness for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Aspects Comput. ![In: Formal Aspects Comput. 12(4), pp. 298-312, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Formal Verification, Microprocessors, Algebraic Models |
49 | Corinna G. Lee, Derek J. DeVries |
Initial Results on the Performance and Cost of Vector Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 171-182, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
47 | Uwe Brinkschulte, Mathias Pacher |
A Control Theory Approach to Improve the Real-Time Capability of Multi-Threaded Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISORC ![In: 11th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2008), 5-7 May 2008, Orlando, Florida, USA, pp. 399-404, 2008, IEEE Computer Society, 978-0-7695-3132-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Control theory in high-end microprocessors, real-time microprocessors, IPC rate |
45 | Yedidya Hilewitz, Ruby B. Lee |
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 53(1-2), pp. 145-169, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Bit scatter, Bit gather, Parallel deposit, Unpack, Algorithm acceleration, Bioinformatics, Compression, Pattern matching, Steganography, Microprocessors, Permutations, Pack, Instruction set architecture, Cryptology, ISA, Parallel extract, Bit manipulations |
44 | William M. van Cleemput, John C. Foster, Donald C. S. Allison (eds.) |
Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![IEEE Press / ACM Digital Library The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Robert I. Gardner |
State of the implementation of SARA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 60-62, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | John Grason |
Design aids and hardware testing of microprocessor system circuit packs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 95-99, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | W. Werner, W. Minnick |
User requirements for digital design verification simulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 36-43, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | William T. Overman, Gerald Estrin |
Developing a SARA building block - the 8080. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 77-86, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Will Sherwood |
Simulation hierarchy for microprocessor design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 44-49, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Charles W. Rose |
N.mPc: An adaptable software system to support the development of microprocessor-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 1, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Lawrence A. O'Neill |
Computer aids for the design of manufacturable microcomputer-based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 108, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Todd J. Wagner |
Verification of hardware designs thru symbolic manipulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 50-53, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | B. A. Prasad |
Modelling techniques for dynamic logic and test pattern generation of a microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 100-107, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Robert I. Gardner |
Multi-level modeling in SARA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 63-66, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | John Teets, Charles W. Rose, Edward J. McCluskey |
Panel Discussions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 110, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Will Sherwood |
PLATO - PLA Translator/Optimizer - "a ROM is a PLA in no uncertain terms.". ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 28-35, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Rami R. Razouk, Gerald Estrin |
The graph model of behavior simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 67-76, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | R. J. Smith II, M. N. Matelan |
Practical considerations in implementing a real-time controller design automation system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 25-27, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Ivan M. Campos, Gerald Estrin |
Specialization of SARA for software synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 87-94, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Gerald Estrin |
Modeling for synthesis - the gap between intent and behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 54-59, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Will Sherwood |
Some applications of the Stanford University Drawing System for LSI microprocessor - "a picture is worth a thousand bytes.". ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 15-19, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Hoo-Min D. Toong |
Automatic design of multiprocessor microprocessor systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 6-14, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Paul J. Drongowski |
Capability requirements in a multimicro processor, hardware/software simulation environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Design Automation and Microprocessors ![In: Proceedings of the Symposium on Design Automation and Microprocessors, Palo Alto, California, February 24-25, 1977., pp. 2-5, 1977, IEEE Press / ACM Digital Library. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP BibTeX RDF |
|
44 | Neal A. Harman |
Algebraic Models of Simultaneous Multithreaded and Multi-core Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CALCO ![In: Algebra and Coalgebra in Computer Science, Second International Conference, CALCO 2007, Bergen, Norway, August 20-24, 2007, Proceedings, pp. 294-311, 2007, Springer, 978-3-540-73857-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
many-sorted algebra, verification, microprocessors, correctness, threaded |
42 | Antonio González 0001 |
Key Microarchitectural Innovations for Future Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings, pp. 2, 2009, Springer, 978-3-642-00453-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
42 | Todd J. Foster, Dennis L. Lastor, Padmaraj Singh |
First Silicon Functional Validation and Debug of Multicore Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(5), pp. 495-504, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Jianfeng An, Xiaoya Fan, Shengbing Zhang, Danghui Wang, Yi Wang 0016 |
VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Third International Conference on Information Technology: New Generations (ITNG 2006), 10-12 April 2006, Las Vegas, Nevada, USA, pp. 245-249, 2006, IEEE Computer Society, 0-7695-2497-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Norman P. Jouppi |
The Future Evolution of High-Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 155, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
42 | Miroslav N. Velev |
Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for the Construction and Analysis of Systems, 7th International Conference, TACAS 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 252-267, 2001, Springer, 3-540-41865-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
42 | Rajesh Kannah, C. P. Ravikumar |
Functional Testing of Microprocessors with Graded Fault Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 204-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
42 | S. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, Arindam Karmakar, Chandra Shekhar 0001, Sudhir Kumar, Amit K. Agarwal |
Evolution of Architectural Concepts and Design Methods of Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 312-317, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Microprocessor Evolution, Synthesis, VHDL, Microprocessor Design |
41 | Philip Heidelberger, M. Seetha Lakshmi |
A Performance Comparison of Multi-Micro and Mainframe Database Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1987 ACM SIGMETRICS conference on Measurement and modeling of computer systems, Banff, Alberta, Canada, May 11-14, 1987, pp. 5-6, 1987, ACM, 0-89791-225-X. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
40 | Seongbae Park, SangMin Shim, Soo-Mook Moon |
Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 104-113, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques |
38 | Yiu-Hing Chan, Prabhakar Kudva, Lisa B. Lacey, Gregory A. Northrop, Thomas E. Rosser |
Physical synthesis methodology for high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 696-701, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
synthesis, microprocessors, high-performance |
38 | John D. Bunda, Donald S. Fussell, William C. Athas |
Energy-efficient instruction set architecture for CMOS microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 298-305, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density |
35 | DiaaEldin Khalil, Yehea I. Ismail |
A global interconnect link design for many-core microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFMT ![In: Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, IFMT 2008, Cairo, Egypt, November 24-25, 2008, pp. 14, 2008, ACM, 978-1-60558-407-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
interconnect, link, bus, repeater insertion |
35 | Jason D. Lee, Praveen Bhojwani, Rabi N. Mahapatra |
A Safety Analysis Framework for COTS Microprocessors in Safety-Critical Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: Tenth IEEE International Symposium on High Assurance Systems Engineering (HASE 2007), November 14-16, 2007, Dallas, Texas, USA, pp. 407-408, 2007, IEEE Computer Society, 0-7695-3043-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Norman P. Jouppi |
The Future Evolution of High-Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2004, 11th International Conference, Bangalore, India, December 19-22, 2004, Proceedings, pp. 5, 2004, Springer, 3-540-24129-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Jianfeng An, Xiaoya Fan, Shengbing Zhang, Danghui Wang |
An Efficient Verification Method for Microprocessors Based on the Virtual Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, First International Conference, ICESS 2004, Hangzhou, China, December 9-10, 2004, Revised Selected Papers, pp. 514-521, 2004, Springer, 3-540-28128-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Carlo Brandolese, Fabio Salice, William Fornaciari, Donatella Sciuto |
Static power modeling of 32-bit microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11), pp. 1306-1316, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Yi-Ping You, Chingren Lee, Jenq Kuen Lee |
Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 15th Workshop, LCPC 2002, College Park, MD, USA, July 25-27, 2002, Revised Papers, pp. 45-60, 2002, Springer, 3-540-30781-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Al Crouch, Jeff Freeman |
Designing and Verifying Embedded Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 14(4), pp. 87-94, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
35 | Chen-Shang Lin, Hong-Fa Ho |
Automatic Functional Test Program Generation for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 605-608, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
31 | Skyler Schneider, Daniel Y. Deng, Daniel Lo, Greg Malysa, G. Edward Suh |
Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 285, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dynamic inspection, reconfigurable microprocessors, fpga |
31 | Adam Waksman, Simha Sethumadhavan |
Tamper Evident Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Security and Privacy ![In: 31st IEEE Symposium on Security and Privacy, SP 2010, 16-19 May 2010, Berleley/Oakland, California, USA, pp. 173-188, 2010, IEEE Computer Society, 978-0-7695-4035-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
microprocessors, hardware security, backdoors |
31 | Nikolaos Kavvadias, Spiridon Nikolaidis 0001 |
Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(2), pp. 200-214, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Optimization, Microprocessors, Hardware description languages, Real-time and embedded systems, Pipeline processors, Control design |
31 | Giovanni Squillero |
Ea-based test and verification of microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO (Companion) ![In: Genetic and Evolutionary Computation Conference, GECCO 2008, Proceedings, Atlanta, GA, USA, July 12-16, 2008, Companion Material, pp. 2665-2688, 2008, ACM, 978-1-60558-131-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
post-sysnthesis verification, pre-sysnthesis verification, test, evolutionary algorithm, microprocessors |
31 | David Van Campenhout, Trevor N. Mudge, John P. Hayes |
High-Level Test Generation for Design Verification of Pipelined Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 185-188, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
high-level test generation, pipelined microprocessors, sequential test generation, design verification |
31 | Li Shen, Stephen Y. H. Su |
A Functional Testing Method for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(10), pp. 1288-1293, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
functional testing method, control fault model, register transfer language, k-out-of-m codes, test generation time, microprocessors, microprocessor chips, computer testing, testing requirements |
31 | Thirumalai Sridhar, John P. Hayes |
A Functional Approach to Testing Bit-Sliced Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(8), pp. 563-571, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
Bit-sliced processors, test generation, fault modeling, microprocessors, testability, iterative logic arrays |
31 | Victor S. Foster |
MIDAS: A MID-level language for microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Annual Conference (2) ![In: Proceedings 1978 ACM Annual Conference, Washington, DC, USA, December 4-6, 1978, Volume II, pp. 526-529, 1978, ACM, 978-0-89791-000-2. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
Microprocessor languages, Mid-level languages, Languages, Microprocessors, MIDAS |
30 | Csaba Andras Moritz, Donald Yeung, Anant Agarwal |
SimpleFit: A Framework for Analyzing Design Trade-Offs in Raw Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 12(7), pp. 730-742, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
modeling, architecture, Multiprocessors, microprocessors |
30 | Marco Ferretti |
Multi-Media Extensions in Super-Pipelined Micro-Architectures. A New Case for SIMD Processing? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 249-, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
super-pipelined microarchitectures, general purpose microprocessors, Von-Neumann paradigm, image processing, parallel architectures, associated memory, instruction set architectures, massively parallel processors, multimedia extensions, SIMD processing |
29 | Laurent Fournier, Yaron Arbetman, Moshe Levinger |
Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 434-441, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Rui Gong, Kui Dai, Zhiying Wang 0003 |
A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 184-192, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Kamran Zarrineh |
Design for Test Challenges of High Performance/Low Power Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 503-503, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Dimitris Gizopoulos, Robert C. Aitken, Sandip Kundu |
Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(5), pp. 493-494, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Srinivas Vadlamani, Stephen F. Jenks |
Architectural Considerations for Efficient Software Execution on Parallel Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), Proceedings, 26-30 March 2007, Long Beach, California, USA, pp. 1-10, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Dietmar Fey, Marcus Komann, Frank Schurz, Andreas Loos |
An Organic Computing architecture for visual microprocessors based on Marching Pixels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2686-2689, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel |
Implicitly Parallel Programming Models for Thousand-Core Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 754-759, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Jason A. Blome, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke |
Cost-efficient soft error protection for embedded microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 421-431, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
reliability, embedded processors, soft errors |
28 | Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova |
Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 111-118, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Andre L. R. Pouponnot |
Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessors: Past, Present and Future. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 319-323, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Eyal Bin, Laurent Fournier |
Micro-Architecture Verification for Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA, pp. 112-113, 2004, IEEE Computer Society, 0-7695-2320-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal |
Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACS ![In: Power-Aware Computer Systems, 4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers, pp. 30-45, 2004, Springer, 3-540-29790-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Lieven Eeckhout |
Efficient architectural design of high performance microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2004 IEEE International Symposium on Performance Analysis of Systems and Software, March 10-12, 2004, Austin, Texas, USA, Proceedings, pp. 170, 2004, IEEE Computer Society, 0-7803-8385-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Nobuyuki Ohba, Kohji Takano |
An SoC design methodology using FPGAs and embedded microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 747-752, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
mixed-level verification, SoC, ASIC, FPGA prototyping |
28 | Shuvendu K. Lahiri, Randal E. Bryant |
Deductive Verification of Advanced Out-of-Order Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 15th International Conference, CAV 2003, Boulder, CO, USA, July 8-12, 2003, Proceedings, pp. 341-353, 2003, Springer, 3-540-40524-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Chris R. Jesshope |
Multi-threaded Microprocessors - Evolution or Revolution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 21-45, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Shuvendu K. Lahiri, Sanjit A. Seshia, Randal E. Bryant |
Modeling and Verification of Out-of-Order Microprocessors in UCLID. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings, pp. 142-159, 2002, Springer, 3-540-00116-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Toshinori Sato, Itsujiro Arita |
Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 17-19 December 2001, Seoul, Korea, pp. 225-232, 2001, IEEE Computer Society, 0-7695-1414-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | Wen Ching Wu, Chung-Len Lee 0001, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir |
Oscillation Ring Delay Test for High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 147-155, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault |
28 | Yutao He, Algirdas Avizienis |
Assessment of the Applicability of COTS Microprocessors in High-Confidence Computing Systems: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2000 International Conference on Dependable Systems and Networks (DSN 2000) (formerly FTCS-30 and DCCA-8), 25-28 June 2000, New York, NY, USA, pp. 81-86, 2000, IEEE Computer Society, 0-7695-0707-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Kanad Ghose |
Reducing energy requirements for instruction issue and dispatch in superscalar microprocessors (poster session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 231-233, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
instruction dispatching, instruction issue, window buffer, superscalar processor, power minimization |
28 | Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto |
An instruction-level functionally-based energy estimation model for 32-bits microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 346-351, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
28 | Takashi Takenaka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi |
Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 177-180, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Shantanu Ganguly, Daksh Lehther, Satyamurthy Pullela |
Clock Distribution Methodology for PowerPCTM Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 16(2-3), pp. 181-189, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
28 | Hélène Collavizza |
Functional semantics of microprocessors at the microprogram level and correspondence with the machine instruction level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 52-56, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
28 | Michael J. Flynn, Robert I. Winner |
ASIC microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989, Dublin, Ireland, August 14-16, 1989, pp. 237-243, 1989, ACM/IEEE, 0-89791-324-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
28 | Paul M. Russo |
Microprocessors at work: session overview. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS National Computer Conference ![In: American Federation of Information Processing Societies: 1975 National Computer Conference, 19-22 May 1975, Anaheim, CA, USA, pp. 21-22, 1975, AFIPS Press, 978-1-4503-7919-9. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
|
28 | Erika Gunadi, Mikko H. Lipasti |
Power-aware operand delivery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 375-378, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power, microarchitecture, renaming |
28 | Toshinori Sato |
Exploiting Instruction Redundancy for Transient Fault Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 547-554, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | James Laudon, Anoop Gupta, Mark Horowitz |
Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VI Proceedings - Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 4-7, 1994., pp. 308-318, 1994, ACM Press, 0-89791-660-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
23 | Mondira (Mandy) Deb Pant |
Microprocessor power delivery challenges in the Nano-Era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 375-376, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
power delivery, power, microprocessors |
23 | Deniz Balkan, Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose |
Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(1), pp. 82-95, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
General, Microprocessors, Pipeline processors, Performance attributes |
23 | Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel |
Examining ACE analysis reliability estimates using fault-injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 460-469, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fault tolerance, microprocessors, soft errors, measurement techniques |
23 | Patricio Bulic, Veselko Gustin |
An efficient way to filter out data dependences with a sufficiently large distance between memory references. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGPLAN Notices ![In: ACM SIGPLAN Notices 40(4), pp. 51-60, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SIMD microprocessors, vectorizing compilers, data dependence analysis |
23 | Michael B. Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal |
Scalar Operand Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(2), pp. 145-162, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
microprocessors, distributed architectures, Interconnection architectures |
23 | Fred A. Bower, Sule Ozev, Daniel J. Sorin |
Autonomic Microprocessor Execution via Self-Repairing Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Dependable Secur. Comput. ![In: IEEE Trans. Dependable Secur. Comput. 2(4), pp. 297-310, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Logic design reliability and testing, microprocessors and microcomputers |
23 | William Lloyd Bircher, M. Valluri, J. Law, Lizy K. John |
Runtime identification of microprocessor energy saving opportunities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 275-280, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
speculative microprocessors, modeling, energy efficiency, power |
23 | Xiuli Sun, Jinzhao Wu, Xiaoyu Song, Mila E. Majster-Cederbaum |
Formal Specification of an Asynchronous Processor via Action Refinement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA, pp. 36-41, 2004, IEEE Computer Society, 0-7695-2320-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
pipelines, microprocessors, asynchronous circuits, Action refinement |
23 | Johnson Kin, Munish Gupta, William H. Mangione-Smith |
The Filter Cache: An Energy Efficient Memory Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 184-193, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
direct mapped 256-byte filter cache, energy efficient memory structure, on-chip caches, static RAM, microprocessors, microprocessor chips, power reduction, embedded applications, L2 cache, filter cache, L1 cache |
23 | Juha Plosila, Kaisa Sere |
Action Systems in Pipelined Processor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands, pp. 156-166, 1997, IEEE Computer Society, 0-8186-7922-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
pipelined processor design, asynchronous pipelined microprocessors, hazard situations, verifying refinement steps, circuit implementation, speed-independent techniques, refinement calculus, refinement calculus, action systems |
23 | Shoji Suzuki, Kang G. Shin |
On memory protection in real-time OS for small embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 4th International Workshop on Real-Time Computing Systems and Applications (RTCSA '97), 27-29 October 1997, Taipei, Taiwan, pp. 51-, 1997, IEEE Computer Society, 0-8186-8073-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
real-time OS, small embedded systems, region enlargement, memory consumption, processing overhead, intermediate-level skip multi-size paging, multi-level paging, short-circuit segment tree, real-time systems, reliability, safety, microprocessors, paged segmentation, hardware support, memory protection |
23 | Georg Färber, Franz Fischer, Thomas Kolloch, Annette Muth |
Improving processor utilization with a task classification model based application specific hard real-time architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 4th International Workshop on Real-Time Computing Systems and Applications (RTCSA '97), 27-29 October 1997, Taipei, Taiwan, pp. 276-, 1997, IEEE Computer Society, 0-8186-8073-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
task classification model, application specific hard real-time architecture, real-time architecture, target architecture framework, tightly coupled heterogeneous multiprocessor system, rapid prototyping platform, caches, pipelines, microprocessors, templates, schedulability analysis, execution times, software prototyping, hard real time systems, processor utilization |
23 | P. Bosch, A. Carloganu, Daniel Etiemble |
Complete x86 instruction trace generation from hardware bus collect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 402-408, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
complete x86 instruction trace generation, hardware bus collect, architectural improvements, benchmark traces, hardware/software approach, x86 execution traces, commercial analyzer, computer architecture, microprocessors, memory hierarchies, trace driven simulation, performance data |
23 | Wolfgang K. Giloi, Ulrich Brüning 0001, Wolfgang Schröder-Preikschat |
MANNA: Prototype of a Distributed Memory Architecture with Maximized Sustained Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), January 24-26, 1996, Portugal, pp. 297-304, 1996, IEEE Computer Society, 0-8186-7376-1. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
maximized sustained performance, compiler problem, innovative architectural solutions, overlapping communication, MANNA computer, benchmark performance, performance evaluation, parallel computers, operating system, parallel machines, distributed memory systems, parallelizing compilers, operating systems (computers), programmability, virtual storage, parallelising compilers, latency hiding, distributed memory parallel computer, distributed memory architecture, virtual shared memory, global address space, superscalar microprocessors |
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