Search results for "nanometer"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
85	Samuel Rodríguez, Bruce L. Jacob	Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm).	ISLPED	2006	DBLP DOI BibTeX RDF	nanometer design, pipelined caches, cache design
63	Janusz Rajski, Kan Thapar	Nanometer Design: What are the Requirements for Manufacturing Test?	DATE	2004	DBLP DOI BibTeX RDF
54	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh	Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
54	Jeong-Taek Kong	CAD for nanometer silicon design challenges and success.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
54	Thomas W. Williams	Testing in Nanometer Technologies.	DATE	1999	DBLP DOI BibTeX RDF
50	Georgios Karakonstantis, Kaushik Roy 0001	Low-Power and Variation-Tolerant Application-Specific System Design.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
50	Sachin S. Sapatnekar	Statistical Design of Integrated Circuits.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
50	Shreyas Sen, Vishwanath Natarajan, Abhijit Chatterjee	Low-Power Adaptive Mixed Signal/RF Circuits and Systems and Self-Healing Solutions.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
50	Swaroop Ghosh	Effect of Variations and Variation Tolerance in Logic Circuits.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
50	Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon	Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
50	Wei Zhang 0012, James Williamson, Li Shang	Power Dissipation.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
50	Aditya Bansal, Rahul M. Rao	Variations: Sources and Characterization.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
50	Nikil Mehta, André DeHon	Low-Power Techniques for FPGAs.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
50	Bipul C. Paul, Arijit Raychowdhury	Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
50	Nikil Mehta, André DeHon	Variation and Aging Tolerance in FPGAs.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
50	Hamid Mahmoodi	Low-Power and Variation-Tolerant Memory Design.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
50	Meeta Sharma Gupta, Pradip Bose	Variation-Tolerant Microprocessor Architecture at Low Power.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
48	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm
48	Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind	Architecting ASIC libraries and flows in nanometer era.	DAC	2003	DBLP DOI BibTeX RDF	nanometer design, libraries, standard cell
44	Joseph Sawicki	Forging Tighter Connections Between Design and Manufacturing in the Nanometer Age.	ISQED	2007	DBLP DOI BibTeX RDF
39	Mehrdad Nourani, Arun Radhakrishnan	Testing On-Die Process Variation in Nanometer VLSI.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	nanometer VLSI, ultra deep-submicron, fast Fourier transform, process variation, frequency domain, ring oscillator
39	Kaushik Roy 0001, T. M. Mak, Kwang-Ting (Tim) Cheng	Test Consideration for Nanometer-Scale CMOS Circuits.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	deep-submicron test, delay test, statistical timing, nanometer technologies
35	Georges G. E. Gielen	Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS.	DDECS	2009	DBLP DOI BibTeX RDF
35	Dan Zhao 0001, Yi Wang 0007	MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
35	Josep Carmona 0001, Jordi Cortadella, Yousuke Takada, Ferdinand Peper	Formal methods for the analysis and synthesis of nanometer-scale cellular arrays.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	model checking, cellular array, Nanocomputing, symbolic techniques
35	Massimo Alioto, Gaetano Palumbo, Melita Pennisi	Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic.	PATMOS	2008	DBLP DOI BibTeX RDF
35	David Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo García Del Valle, Michael DeBole, Vijaykrishnan Narayanan	Reliability-aware design for nanometer-scale devices.	ASP-DAC	2008	DBLP DOI BibTeX RDF
35	Chong Zhao, Xiaoliang Bai, Sujit Dey	Evaluating Transient Error Effects in Digital Nanometer Circuits.	IEEE Trans. Reliab.	2007	DBLP DOI BibTeX RDF
35	N. Verghese, P. Hurat	DFM reality in sub-nanometer IC design.	ASP-DAC	2007	DBLP DOI BibTeX RDF	EDA solutions, subnanometer IC design, catastrophic failures, systematic manufacturing variations, subnanometer manufacturing variations, DFM, design for manufacturing, parametric failures
35	Georges G. E. Gielen	Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies.	ASP-DAC	2007	DBLP DOI BibTeX RDF
35	Georges G. E. Gielen	Future trends for wireless communication frontends in nanometer CMOS.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	RF frontends, wireless sensor networks, wireless communication, integrated circuits, reconfigurable hardware
35	Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal	Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	measurement, process variations, extraction, VLSI interconnects
35	Chuen M. Tan, Masud H. Chowdhury	Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
35	Gadi Singer, Philippe Magarshack, Dennis Buss, Fu-Chieh Hsu, Ho-Kyu Kang	"The IC nanometer race -- what will it take to win?".	DAC	2006	DBLP DOI BibTeX RDF	hardware
35	Krishnan Sundaresan, Nihar R. Mahapatra	Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses.	HPCA	2005	DBLP DOI BibTeX RDF
35	Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman	Practical Aspects of Delay Testing for Nanometer Chips.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
35	Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi	Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
35	Khalil Arshak, Stephen F. Gilmartin, Damian Collins, Olga Korostynska, Arous Arshak	Patterning Nanometer Resist Features on Planar and Topography Substrates Using The 2-Step NERIME FIB Top Surface Imaging Process.	ICMENS	2005	DBLP DOI BibTeX RDF
35	Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee	A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs.	ICCD	2005	DBLP DOI BibTeX RDF
35	Jay Jahangiri, David Abercrombie	Meeting Nanometer DPM Requirements Through DFT.	ISQED	2005	DBLP DOI BibTeX RDF
35	E. Y. Chou, J. C. Huang, M. S. Huang, M. C. Hsieh, A. Y. Hsu	Baud-rate channel equalization in nanometer technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
35	Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas	Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
35	Cunkui Huang, Kumar Nandakumar, Daniel Y. Kwok	Non-Equilibrium Injection Flow in a Nanometer Capillary Channel.	ICMENS	2004	DBLP DOI BibTeX RDF
35	Brian Marshall	Beyond P-Cell and Gate-Level: Accuracy Requirements for Simulation of Nanometer SoC Designs.	IWSOC	2004	DBLP DOI BibTeX RDF
35	Robert W. Brodersen, Anthony M. Hill, John Kibarian, Desmond Kirkpatrick, Mark A. Lavin, Mitsumasa Koyanagi	Nanometer design: what hurts next...?	DAC	2002	DBLP DOI BibTeX RDF
31	Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park	Leakage Minimization Technique for Nanoscale CMOS VLSI.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current
31	Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Chien-Mo Li	Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies.	ASP-DAC	2007	DBLP DOI BibTeX RDF	systematic defects, cyclic-column parity row selection technique, built-in self tested circuits, cyclic scan chains, masking circuitry, transient errors, circuit under test, nanometer technologies
31	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
31	Sachin S. Sapatnekar	Book Reviews: Plumbing the Depths of Leakage.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	nanometer CMOS technology, leakage
31	Steve Leibson, James Kim	Configurable Processors: A New Era in Chip Design.	Computer	2005	DBLP DOI BibTeX RDF	nanometer silicon lithography, microprocessors, multiprocessor systems, MPSoCs, configurable processors
31	Robert Madge	New test paradigms for yield and manufacturability.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	nanometer-era semiconductor, test paradigm, yield and manufacturability
31	Chong Zhao, Yi Zhao, Sujit Dey	Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits.	DAC	2005	DBLP DOI BibTeX RDF	circuit hardening, nanometer circuits, robustness calibration, robustness insertion
31	Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen	Multilevel routing with antenna avoidance.	ISPD	2004	DBLP DOI BibTeX RDF	nanometer, process antenna effect, routing, physical design, design for manufacturability (DFM), multilevel optimization
31	Kyu-won Choi, Abhijit Chatterjee	UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI.	ISLPED	2003	DBLP DOI BibTeX RDF	device and interconnect co-optimization, nanometer design, time slack distribution, low-power design
31	Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi	Noise tolerant low voltage XOR-XNOR for fast arithmetic.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	XOR-XNOR circuits, multipliers, noise tolerant, deep submicron, nanometer technology
27	Khawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar	Complementary nano-electromechanical switches for ultra-low power embedded processors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	nems, cmos, switch, device, ultra-low power
27	Sheng-Chih Lin, Kaustav Banerjee	A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
27	Mini Nanua, David T. Blaauw	Crosstalk Waveform Modeling Using Wave Fitting.	PATMOS	2007	DBLP DOI BibTeX RDF
26	Feng Ge, Pranjal Jain, Ken Choi	Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology.	EIT	2009	DBLP DOI BibTeX RDF
26	David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat	Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic.	ISLPED	2009	DBLP DOI BibTeX RDF	short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage
26	Basab Datta, Wayne P. Burleson	On temperature planarization effect of copper dummy fills in deep nanometer technology.	ISQED	2009	DBLP DOI BibTeX RDF
26	Shaoxi Wang, Rui He, Lihong Zhang	MOSFET model assessment for submicron and nanometer bulk-driven applications.	CCECE	2009	DBLP DOI BibTeX RDF
26	Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen	Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
26	Ja Chun Ku, Yehea I. Ismail	Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
26	Georges G. E. Gielen, Pieter De Wit, Elie Maricau, Johan Loeckx, Javier Martín-Martínez, Ben Kaczer, Guido Groeseneken, Rosana Rodríguez, Montserrat Nafría	Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies.	DATE	2008	DBLP DOI BibTeX RDF
26	David Z. Pan	Synergistic modeling and optimization for nanometer IC design/manufacturing integration.	SBCCI	2008	DBLP DOI BibTeX RDF	design for manufacturing
26	Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
26	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.	SoCC	2008	DBLP DOI BibTeX RDF
26	Adit D. Singh	Scan Delay Testing of Nanometer SoCs.	VLSI Design	2008	DBLP DOI BibTeX RDF
26	Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi	Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
26	Davide Pandini	Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies.	PATMOS	2007	DBLP DOI BibTeX RDF
26	Hengliang Zhu, Xuan Zeng 0001, Wei Cai 0003, Jintao Xue, Dian Zhou	A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology.	DATE	2007	DBLP DOI BibTeX RDF
26	José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura 0001	Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs.	DATE	2007	DBLP DOI BibTeX RDF
26	Zhangcai Huang, Hong Yu 0013, Atsushi Kurokawa, Yasuaki Inoue	Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies.	ASP-DAC	2007	DBLP DOI BibTeX RDF
26	Jarrod A. Roy, Igor L. Markov	High-performance routing at the nanometer scale.	ICCAD	2007	DBLP DOI BibTeX RDF
26	Ja Chun Ku, Yehea I. Ismail	Attaining Thermal Integrity in Nanometer Chips.	ISCAS	2007	DBLP DOI BibTeX RDF
26	Davide Pandini	Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies.	IOLTS	2007	DBLP DOI BibTeX RDF
26	Ja Chun Ku, Yehea I. Ismail	Area optimization for leakage reduction and thermal stability in nanometer scale technologies.	ASP-DAC	2006	DBLP DOI BibTeX RDF
26	Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava	Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems.	ASP-DAC	2006	DBLP DOI BibTeX RDF
26	Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen	Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs.	ISPD	2006	DBLP DOI BibTeX RDF	fault-tolerant, reliability, low power, coupling capacitance
26	Massimo Alioto, Gaetano Palumbo	Nanometer MCML gates: models and design considerations.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura 0001	Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?.	VTS	2006	DBLP DOI BibTeX RDF
26	Fumio Sasaki, Satoshi Haraichi, Shunsuke Kobayashi	Highly oriented molecular aggregates in 1-D photonic crystal slabs: toward the control of molecular arrangement from submicron to nanometer region.	IEEE J. Sel. Areas Commun.	2005	DBLP DOI BibTeX RDF
26	Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici	A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
26	Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee	Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits.	DATE	2005	DBLP DOI BibTeX RDF
26	Tetyana Segin, Jacob Masliyah, Subir Bhattacharjee	Molecular Dynamics Simulation of the Rupture of Nanometer-Sized Oil/Water Interface.	ICMENS	2005	DBLP DOI BibTeX RDF
26	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De	A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.	ICCD	2005	DBLP DOI BibTeX RDF
26	Navin Srivastava, Xiaoning Qi, Kaustav Banerjee	Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
26	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance.	VTS	2005	DBLP DOI BibTeX RDF
26	Alexandre Schmid, Yusuf Leblebici	Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
26	Hongliang Chang, Haifeng Qian, Sachin S. Sapatnekar	The Certainty of Uncertainty: Randomness in Nanometer Design.	PATMOS	2004	DBLP DOI BibTeX RDF
26	Alexandre Schmid, Yusuf Leblebici	A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies.	DFT	2004	DBLP DOI BibTeX RDF
26	Sanjay Sengupta	Test Strategies for Nanometer Technologies.	ITC	2004	DBLP DOI BibTeX RDF
26	Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane	An Economic Analysis and ROI Model for Nanometer Test.	ITC	2004	DBLP DOI BibTeX RDF
26	Greg Aldrich	100 DPPM in Nanometer Technology - Is it achievable?	ITC	2004	DBLP DOI BibTeX RDF
26	Aman Kokrady, C. P. Ravikumar	Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures.	VLSI Design	2004	DBLP DOI BibTeX RDF	Timing Failure, Test Validation, Crosstalk, At Speed Testing, IR Drop
26	Shekhar Borkar, Tanay Karnik, Vivek De	Design and reliability challenges in nanometer technologies.	DAC	2004	DBLP DOI BibTeX RDF	leakage tolerance, reliability, low-power, variability, soft errors, circuits, SEU, SER, variation tolerance
26	Kaushik Roy 0001, T. M. Mak, Kwang-Ting Cheng	Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits.	VTS	2003	DBLP DOI BibTeX RDF
26	Philippe Magarshack, Pierre G. Paulin	System-on-chip beyond the nanometer wall.	DAC	2003	DBLP DOI BibTeX RDF	design automation tools, embedded software technologies, system-on-chip, network-on-chip, reconfigurable systems, multi-processor systems
26	Dennis Sylvester, Himanshu Kaul	Power-Driven Challenges in Nanometer Design.	IEEE Des. Test Comput.	2001	DBLP DOI BibTeX RDF