Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
85 | Samuel Rodríguez, Bruce L. Jacob |
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 25-30, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
nanometer design, pipelined caches, cache design |
63 | Janusz Rajski, Kan Thapar |
Nanometer Design: What are the Requirements for Manufacturing Test? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 930-937, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh |
Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(5), pp. 514-524, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
54 | Jeong-Taek Kong |
CAD for nanometer silicon design challenges and success. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(11), pp. 1132-1147, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Thomas W. Williams |
Testing in Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 5-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
50 | Georgios Karakonstantis, Kaushik Roy 0001 |
Low-Power and Variation-Tolerant Application-Specific System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 249-292, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
50 | Sachin S. Sapatnekar |
Statistical Design of Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 109-149, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
50 | Shreyas Sen, Vishwanath Natarajan, Abhijit Chatterjee |
Low-Power Adaptive Mixed Signal/RF Circuits and Systems and Self-Healing Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 293-333, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
50 | Swaroop Ghosh |
Effect of Variations and Variation Tolerance in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 83-108, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
50 | Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon |
Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 381-432, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
50 | Wei Zhang 0012, James Williamson, Li Shang |
Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 41-80, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
50 | Aditya Bansal, Rahul M. Rao |
Variations: Sources and Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 3-39, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
50 | Nikil Mehta, André DeHon |
Low-Power Techniques for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 337-363, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
50 | Bipul C. Paul, Arijit Raychowdhury |
Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 185-207, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
50 | Nikil Mehta, André DeHon |
Variation and Aging Tolerance in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 365-380, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
50 | Hamid Mahmoodi |
Low-Power and Variation-Tolerant Memory Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 151-183, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
50 | Meeta Sharma Gupta, Pradip Bose |
Variation-Tolerant Microprocessor Architecture at Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 211-247, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
48 | Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi |
Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 654-659, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
gate leakage current, nanometer-scale CMOS circuits, supply switching, ground collapse, standard-cell elements, 45 nm, 65 nm, power gating, subthreshold leakage current, 90 nm |
48 | Clive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind |
Architecting ASIC libraries and flows in nanometer era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 776-781, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
nanometer design, libraries, standard cell |
44 | Joseph Sawicki |
Forging Tighter Connections Between Design and Manufacturing in the Nanometer Age. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 560-566, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Mehrdad Nourani, Arun Radhakrishnan |
Testing On-Die Process Variation in Nanometer VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(6), pp. 438-451, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
nanometer VLSI, ultra deep-submicron, fast Fourier transform, process variation, frequency domain, ring oscillator |
39 | Kaushik Roy 0001, T. M. Mak, Kwang-Ting (Tim) Cheng |
Test Consideration for Nanometer-Scale CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(2), pp. 128-136, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
deep-submicron test, delay test, statistical timing, nanometer technologies |
35 | Georges G. E. Gielen |
Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 1, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
35 | Dan Zhao 0001, Yi Wang 0007 |
MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(8), pp. 1046-1057, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Josep Carmona 0001, Jordi Cortadella, Yousuke Takada, Ferdinand Peper |
Formal methods for the analysis and synthesis of nanometer-scale cellular arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(2), pp. 8:1-8:27, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
model checking, cellular array, Nanocomputing, symbolic techniques |
35 | Massimo Alioto, Gaetano Palumbo, Melita Pennisi |
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 136-145, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | David Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo García Del Valle, Michael DeBole, Vijaykrishnan Narayanan |
Reliability-aware design for nanometer-scale devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 549-554, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Chong Zhao, Xiaoliang Bai, Sujit Dey |
Evaluating Transient Error Effects in Digital Nanometer Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 56(3), pp. 381-391, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | N. Verghese, P. Hurat |
DFM reality in sub-nanometer IC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 226-231, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
EDA solutions, subnanometer IC design, catastrophic failures, systematic manufacturing variations, subnanometer manufacturing variations, DFM, design for manufacturing, parametric failures |
35 | Georges G. E. Gielen |
Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 432-437, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Georges G. E. Gielen |
Future trends for wireless communication frontends in nanometer CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 600-605, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
RF frontends, wireless sensor networks, wireless communication, integrated circuits, reconfigurable hardware |
35 | Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal |
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 14-18, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
measurement, process variations, extraction, VLSI interconnects |
35 | Chuen M. Tan, Masud H. Chowdhury |
Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 2004-2007, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
35 | Gadi Singer, Philippe Magarshack, Dennis Buss, Fu-Chieh Hsu, Ho-Kyu Kang |
"The IC nanometer race -- what will it take to win?". ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 77-78, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
hardware |
35 | Krishnan Sundaresan, Nihar R. Mahapatra |
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 51-60, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman |
Practical Aspects of Delay Testing for Nanometer Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 470, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi |
Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 156-161, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Khalil Arshak, Stephen F. Gilmartin, Damian Collins, Olga Korostynska, Arous Arshak |
Patterning Nanometer Resist Features on Planar and Topography Substrates Using The 2-Step NERIME FIB Top Surface Imaging Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMENS ![In: 2005 International Conference on MEMS, NANO, and Smart Systems (ICMENS 2005), 24-27 July 2005, Banff, Alberta, Canada, pp. 159-166, 2005, IEEE Computer Society, 0-7695-2398-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee |
A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 411-416, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Jay Jahangiri, David Abercrombie |
Meeting Nanometer DPM Requirements Through DFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 276-282, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | E. Y. Chou, J. C. Huang, M. S. Huang, M. C. Hsieh, A. Y. Hsu |
Baud-rate channel equalization in nanometer technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(11), pp. 1174-1181, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas |
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8), pp. 1256-1263, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Cunkui Huang, Kumar Nandakumar, Daniel Y. Kwok |
Non-Equilibrium Injection Flow in a Nanometer Capillary Channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMENS ![In: 2004 International Conference on MEMS, NANO, and Smart Systems (ICMENS 2004), 25-27 August 2004, Banff, Alberta, Canada, pp. 374-378, 2004, IEEE Computer Society, 0-7695-2189-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Brian Marshall |
Beyond P-Cell and Gate-Level: Accuracy Requirements for Simulation of Nanometer SoC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 19-21 July 2004, Banff, Alberta, Canada, pp. 23-26, 2004, IEEE Computer Society, 0-7695-2182-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Robert W. Brodersen, Anthony M. Hill, John Kibarian, Desmond Kirkpatrick, Mark A. Lavin, Mitsumasa Koyanagi |
Nanometer design: what hurts next...? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 242, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park |
Leakage Minimization Technique for Nanoscale CMOS VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(4), pp. 322-330, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current |
31 | Chun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Chien-Mo Li |
Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 835-840, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
systematic defects, cyclic-column parity row selection technique, built-in self tested circuits, cyclic scan chains, masking circuitry, transient errors, circuit under test, nanometer technologies |
31 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 678-683, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process |
31 | Sachin S. Sapatnekar |
Book Reviews: Plumbing the Depths of Leakage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(4), pp. 318-319, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
nanometer CMOS technology, leakage |
31 | Steve Leibson, James Kim |
Configurable Processors: A New Era in Chip Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 38(7), pp. 51-59, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
nanometer silicon lithography, microprocessors, multiprocessor systems, MPSoCs, configurable processors |
31 | Robert Madge |
New test paradigms for yield and manufacturability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(3), pp. 240-246, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
nanometer-era semiconductor, test paradigm, yield and manufacturability |
31 | Chong Zhao, Yi Zhao, Sujit Dey |
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 190-195, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
circuit hardening, nanometer circuits, robustness calibration, robustness insertion |
31 | Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen |
Multilevel routing with antenna avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 34-40, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
nanometer, process antenna effect, routing, physical design, design for manufacturability (DFM), multilevel optimization |
31 | Kyu-won Choi, Abhijit Chatterjee |
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 72-77, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
device and interconnect co-optimization, nanometer design, time slack distribution, low-power design |
31 | Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi |
Noise tolerant low voltage XOR-XNOR for fast arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 285-288, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
XOR-XNOR circuits, multipliers, noise tolerant, deep submicron, nanometer technology |
27 | Khawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar |
Complementary nano-electromechanical switches for ultra-low power embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 309-314, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
nems, cmos, switch, device, ultra-low power |
27 | Sheng-Chih Lin, Kaustav Banerjee |
A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(11), pp. 1488-1498, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Mini Nanua, David T. Blaauw |
Crosstalk Waveform Modeling Using Wave Fitting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 211-221, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Feng Ge, Pranjal Jain, Ken Choi |
Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 405-410, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | David Bol, Dina Kamel, Denis Flandre, Jean-Didier Legat |
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 3-8, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
short-channel effects, subthreshold logic, variability, cmos digital integrated circuits, ultra-low power, gate leakage |
26 | Basab Datta, Wayne P. Burleson |
On temperature planarization effect of copper dummy fills in deep nanometer technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 494-499, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Shaoxi Wang, Rui He, Lihong Zhang |
MOSFET model assessment for submicron and nanometer bulk-driven applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, CCECE 2009, 3-6 May 2009, Delta St. John's Hotel and Conference Centre, St. John's, Newfoundland, Canada, pp. 1091-1094, 2009, IEEE, 978-1-4244-3508-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
26 | Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen |
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(5), pp. 589-593, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Ja Chun Ku, Yehea I. Ismail |
Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 241-248, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Georges G. E. Gielen, Pieter De Wit, Elie Maricau, Johan Loeckx, Javier Martín-Martínez, Ben Kaczer, Guido Groeseneken, Rosana Rodríguez, Montserrat Nafría |
Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1322-1327, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | David Z. Pan |
Synergistic modeling and optimization for nanometer IC design/manufacturing integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 2, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
design for manufacturing |
26 | Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2761-2764, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty |
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 21st Annual IEEE International SoC Conference, SoCC 2008, September 17-20, 2008, Radisson Hotel, Newport Beach, CA, USA, Proceedings, pp. 243-246, 2008, IEEE, 978-1-4244-2596-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Adit D. Singh |
Scan Delay Testing of Nanometer SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 13, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi |
Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(7), pp. 758-766, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Davide Pandini |
Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 577, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Hengliang Zhu, Xuan Zeng 0001, Wei Cai 0003, Jintao Xue, Dian Zhou |
A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1514-1519, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura 0001 |
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1271-1276, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Zhangcai Huang, Hong Yu 0013, Atsushi Kurokawa, Yasuaki Inoue |
Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 565-570, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Jarrod A. Roy, Igor L. Markov |
High-performance routing at the nanometer scale. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 496-502, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Ja Chun Ku, Yehea I. Ismail |
Attaining Thermal Integrity in Nanometer Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3223-3226, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Davide Pandini |
Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 254, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Ja Chun Ku, Yehea I. Ismail |
Area optimization for leakage reduction and thermal stability in nanometer scale technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 231-236, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Kaustav Banerjee, Sheng-Chih Lin, Navin Srivastava |
Electrothermal engineering in the nanometer era: from devices and interconnects to circuits and systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 223-230, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Shanq-Jang Ruan, Edwin Naroska, Chun-Chih Chen |
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 114-119, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fault-tolerant, reliability, low power, coupling capacitance |
26 | Massimo Alioto, Gaetano Palumbo |
Nanometer MCML gates: models and design considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura 0001 |
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 358-363, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
26 | Fumio Sasaki, Satoshi Haraichi, Shunsuke Kobayashi |
Highly oriented molecular aggregates in 1-D photonic crystal slabs: toward the control of molecular arrangement from submicron to nanometer region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 23(7), pp. 1385-1389, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici |
A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 111-125, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee |
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 288-293, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Tetyana Segin, Jacob Masliyah, Subir Bhattacharjee |
Molecular Dynamics Simulation of the Rupture of Nanometer-Sized Oil/Water Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMENS ![In: 2005 International Conference on MEMS, NANO, and Smart Systems (ICMENS 2005), 24-27 July 2005, Banff, Alberta, Canada, pp. 295, 2005, IEEE Computer Society, 0-7695-2398-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De |
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 567-573, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Navin Srivastava, Xiaoning Qi, Kaustav Banerjee |
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 346-351, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh |
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 298-303, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Alexandre Schmid, Yusuf Leblebici |
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(11), pp. 1156-1166, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Hongliang Chang, Haifeng Qian, Sachin S. Sapatnekar |
The Certainty of Uncertainty: Randomness in Nanometer Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 36-47, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Alexandre Schmid, Yusuf Leblebici |
A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 39-47, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Sanjay Sengupta |
Test Strategies for Nanometer Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1421, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane |
An Economic Analysis and ROI Model for Nanometer Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 518-524, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Greg Aldrich |
100 DPPM in Nanometer Technology - Is it achievable? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1417, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Aman Kokrady, C. P. Ravikumar |
Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 597-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Timing Failure, Test Validation, Crosstalk, At Speed Testing, IR Drop |
26 | Shekhar Borkar, Tanay Karnik, Vivek De |
Design and reliability challenges in nanometer technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 75, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
leakage tolerance, reliability, low-power, variability, soft errors, circuits, SEU, SER, variation tolerance |
26 | Kaushik Roy 0001, T. M. Mak, Kwang-Ting Cheng |
Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 313-318, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Philippe Magarshack, Pierre G. Paulin |
System-on-chip beyond the nanometer wall. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 419-424, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
design automation tools, embedded software technologies, system-on-chip, network-on-chip, reconfigurable systems, multi-processor systems |
26 | Dennis Sylvester, Himanshu Kaul |
Power-Driven Challenges in Nanometer Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 18(6), pp. 12-22, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|