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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 401 occurrences of 236 keywords
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Results
Found 435 publication records. Showing 435 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
63 | Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, George Xenoulis |
Software-Based Self-Testing of Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(4), pp. 461-475, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
processor self-testing, Embedded processors, software-based self-testing, low-cost testing |
50 | Matthew K. Franklin, Juan A. Garay, Moti Yung |
Self-Testing/Correcting Protocols (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 13th International Symposium, Bratislava, Slovak Republic, September 27-29, 1999, Proceedings, pp. 269-283, 1999, Springer, 3-540-66531-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
43 | Stanislaw J. Piestrak |
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(2), pp. 229-234, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
embedded circuit, inverter-free circuit, totally self-testing circuit, concurrent error detection, Berger code, self-testing checker, two-rail code |
36 | Dimitris Nikolos |
Self-Testing Embedded Two-Rail Checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 69-79, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
parity tree, embedded self-testing, self testing, two-rail checker, parity checker |
35 | Li Chen, Sujit Dey |
Software-based self-testing methodology for processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3), pp. 369-380, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
35 | Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng |
Embedded hardware and software self-testing methodologies for processor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 625-630, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
34 | Tom Chen 0001, Glen Sunada |
Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(2), pp. 88-97, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
33 | Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey |
Embedded software-based self-testing for SoC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 355-360, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
functional test, SoC test, VLSI test, microprocessor test |
32 | Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi |
Instruction-level test methodology for CPU core self-testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(4), pp. 673-689, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing |
31 | Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar |
Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 14th IEEE European Test Symposium, ETS 2009, Sevilla, Spain, May 25-29, 2009, pp. 33-38, 2009, IEEE Computer Society, 978-0-7695-3703-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Chip multithreading, micro-processor testing, functional self-testing, test time optimization, multiprocessors, software-based self-testing |
31 | Dimitris Nikolos |
Optimal Self-Testing Embedded Parity Checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(3), pp. 313-321, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Parity tree, embedded self-testing circuits, self-testing, two-rail checker, parity checker |
31 | Krishnendu Chakrabarty, John P. Hayes |
Balance testing and balance-testable design of logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(1), pp. 71-86, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
built-in self testing, design for testability, fault detection, fault coverage, testing methods |
31 | Xrysovalantis Kavousianos, Dimitris Nikolos |
Self-exercising self testing k-order comparators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 216-221, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
self testing k-order comparators, self-exercising comparators, equality comparator, fault tolerant cache memory, built-in self test, error correction codes, combinational circuit, error detection codes, broadcast networks |
31 | Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian |
Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 431-440, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Ronald Stevens, Brittany Parsons, Tariq M. King |
A self-testing autonomic container. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 45th Annual Southeast Regional Conference, 2007, Winston-Salem, North Carolina, USA, March 23-24, 2007, pp. 1-6, 2007, ACM, 978-1-59593-629-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
testing, validation, autonomic computing |
30 | Steffen Tarnick |
Design of Embedded Self-Testing Checkers for t-UED and BUED Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(5), pp. 465-477, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
t-unidirectional error detecting (t-UED) codes, burst unidirectional error detecting (BUED) codes, averaging circuits, embedded checkers, self-testing checkers |
28 | Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis |
Functional Self-Testing for Bus-Based Symmetric Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1304-1309, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis |
Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Dependable Secur. Comput. ![In: IEEE Trans. Dependable Secur. Comput. 6(2), pp. 124-134, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005 |
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(4-6), pp. 449-462, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array |
27 | Cecilia Metra, Michele Favalli, Bruno Riccò |
Compact and low power on-line self-testing voting scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 137-147, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
on-line self-testing voting scheme, fault-tolerant techniques, reliability, power consumption, majority voting, triple modular redundancy, area overhead, majority logic, TMR systems |
27 | Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Constantin Halatsis |
A concurrent built-in self-test architecture based on a self-testing RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 54(1), pp. 69-78, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Xiaoliang Bai, Sujit Dey, Janusz Rajski |
Self-test methodology for at-speed test of crosstalk in chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 619-624, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian |
Instruction-Based Self-Testing of Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(2), pp. 103-112, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
processor cores, built-in self-test, instruction set, at-speed testing, software-based self test |
26 | Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian |
Instruction-Based Self-Testing of Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 223-228, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Eiji Fujiwara, Nobuo Mutoh, Kohji Matsuoka |
A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(6), pp. 578-583, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
self-verification, error-detection ability, group-parity prediction checker, self-testing, Built-in testing, duplication, self-checking checker, fault-detection ability |
25 | Steffen Tarnick |
Self-Testing Embedded Borden t -UED Code Checkers for t = 2 k q - 1 with q = 2 m - 1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(6), pp. 509-527, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Borden codes, Embedded checkers, Code translators, AN codes, Self-testing checkers |
25 | Stanislaw J. Piestrak |
Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 12(1-2), pp. 63-68, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
counters of 1s, m-out-of-n (m/n) codes, concurrent error detection, on-line testing, self-checking circuit, unidirectional errors, parallel counters, unordered codes, self-testing checker |
25 | Stanislaw J. Piestrak |
Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 119-127, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
systematic unidirectional error detecting code, t-UED Bose-Lin code, burst UED code, multi-output threshold circuit, encoder, automatic testing, logic function, Berger code, hardware complexity, self-testing checker |
25 | Kazuo Kawakubo, Koji Tanaka, Hiromi Hiraishi |
Formal Verification Of Self-Testing Properties Of Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 119-122, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
self-testing properties, logic function manipulation, decision function, output code words, self-checking logic, mutiple-input multiple-output circuit, fault tolerance, formal verification, combinational circuits, combinational circuits, binary decision diagrams, stuck-at faults, satisfiability problem, characteristic functions, Berger code |
25 | Hussam Y. Abujbara, Sami A. Al-Arian |
Self-testing and self-reconfiguration architecture for 2-D WSI arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPDP ![In: Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, SPDP 1990, Dallas, Texas, USA, December 9-13, 1990., pp. 527-530, 1990, IEEE Computer Society, 0-8186-2087-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
24 | Ravi Kumar 0001, D. Sivakumar 0001 |
Efficient Self-Testing/Self-Correction of Linear Recurrences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 37th Annual Symposium on Foundations of Computer Science, FOCS '96, Burlington, Vermont, USA, 14-16 October, 1996, pp. 602-611, 1996, IEEE Computer Society, 0-8186-7594-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
efficient self-testing, efficient self-correction, self-tester design, self-corrector design, result-checkers, linear function testing, counting arguments, matrix twist, convolution identities, VLSI chip testing, randomness-efficient self-tester, rational domains, signal processing, finite fields, program testing, polynomials, reduction, functions, spectral analysis, matrix groups, linear recurrences, control engineering |
24 | Nur A. Touba, Edward J. McCluskey |
Applying two-pattern tests using scan-mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 393-399, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests |
24 | Adam Kristof |
Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 630, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
23 | Y. You, John P. Hayes |
Implementation of VLSI self-testing by regularization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12), pp. 1261-1271, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
23 | Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
Low-Cost Software-Based Self-Testing of RISC Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10714-10719, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
23 | Andrzej Krasniewski, Alexander Albicki |
Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 808-811, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
23 | Frédéric Magniez |
Multi-Linearity Self-Testing with Relative Error. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theory Comput. Syst. ![In: Theory Comput. Syst. 38(5), pp. 573-591, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Timothy J. Dysart, Peter M. Kogge |
Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 478-486, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Steven S. Gorshe, Bella Bose |
A self-checking ALU design with efficient codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 157-161, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
self-checking ALU design, self-testing ALU, VLSI, logic testing, built-in self test, integrated circuit testing, logic design, error detection codes, error detecting codes, integrated logic circuits, unidirectional errors |
21 | Peter Böhlau |
Zero Aliasing Compression Based on Groups of Weakly Independent Outputs in Circuits with High Complexity for Two Fault Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDCC ![In: Dependable Computing - EDCC-1, First European Dependable Computing Conference, Berlin, Germany, October 4-6, 1994, Proceedings, pp. 289-306, 1994, Springer, 3-540-58426-9. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
zero aliasing, self-testing circuits, functional properties, groupability, weakly independent outputs, built-in self-test |
21 | Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
Built-in sequential fault self-testing of array multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3), pp. 449-460, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Jaeki Yoo, Edward Lee, Earl E. Swartzlander Jr. |
A self-testing method for the pipelined A/D converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 109-112, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Ravi Kumar 0001, D. Sivakumar 0001 |
On Self-Testing without the Generator Bottleneck. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSTTCS ![In: Foundations of Software Technology and Theoretical Computer Science, 15th Conference, Bangalore, India, December 18-20, 1995, Proceedings, pp. 248-262, 1995, Springer, 3-540-60692-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
20 | Alain E. Ramirez, Barbara Quinones-Morales, Tariq M. King |
A self-testing autonomic job scheduler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Southeast Regional Conference ![In: Proceedings of the 46th Annual Southeast Regional Conference, 2008, Auburn, Alabama, USA, March 28-29, 2008, pp. 304-309, 2008, ACM, 978-1-60558-105-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
autonomic computing, job scheduling, self-testing |
20 | Stanislaw J. Piestrak |
Design of Self-Testing Checkers for Borden Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(4), pp. 461-469, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Borden code, easily-testable circuit, multioutput threshold circuit, optimal t-unidirectional error detecting code, concurrent error detection, unidirectional errors, self-testing checker, unidirectional error detecting code |
20 | Egor S. Sogomonyan, Michael Gössel |
Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 138-144, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
circuit feedback, concurrently self-testing embedded checker, ultra-reliable fault-tolerant system, parity codes, design, monitoring, built-in self test, integrated circuit testing, linear feedback shift register, error detection codes, error detection code, shift registers, arithmetic codes, Berger codes, duplication codes, integrated circuit reliability, corrector |
20 | Seyed H. Hosseini, Nizar Jamal |
Efficient Distributed Algorithms for Self Testing of Multiple Processor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(11), pp. 1397-1409, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
interprocessor links, testing overhead, performance evaluation, performance, reliability, distributed algorithms, fault tolerant computing, multiprocessing systems, automatic testing, simulation results, self testing, multiple processor systems, dynamic testing |
20 | Stanislaw J. Piestrak |
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(3), pp. 360-374, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
complexity, logic testing, logic design, automatic testing, digital arithmetic, logic circuits, error-detecting codes, error detection codes, arithmetic codes, gate levels, self-testing checkers |
20 | Yuval Tamir, Carlo H. Séquin |
Design and Application of Self-Testing Comparators Implemented with MOS PLA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 33(6), pp. 493-506, 1984. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP DOI BibTeX RDF |
two-rail code checker, duplication and matching, faults in VLSI circuits, MOS PLA fault model, self-testing comparator, programmable logic array, Concurrent error detection |
20 | Zeev Barzilai, Don Coppersmith, Arnold L. Rosenberg |
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(2), pp. 190-194, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
VLSI self-testing, Linear feedback shift registers (LFSR), primitive polynomials |
19 | Sami Beydeda |
Self-Metamorphic-Testing Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC (2) ![In: 30th Annual International Computer Software and Applications Conference, COMPSAC 2006, Chicago, Illinois, USA, September 17-21, 2006. Volume 2, pp. 265-272, 2006, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Marcos A. Kiwi, Frédéric Magniez, Miklos Santha |
Exact and Approximate Testing/Correcting of Algebraic Functions: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Theoretical Aspects of Computer Science ![In: Theoretical Aspects of Computer Science, Advanced Lectures (First Summer School on Theoretical Aspects of Computer Science, Tehran, Iran, July 2000), pp. 30-83, 2000, Springer, 3-540-43328-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Manuel Blum 0001, Bruno Codenotti, Peter Gemmell, Troy Shahoumian |
Self-Correcting for Function Fields Transcendental Degree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 22nd International Colloquium, ICALP95, Szeged, Hungary, July 10-14, 1995, Proceedings, pp. 547-557, 1995, Springer, 3-540-60084-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Dimitris Gizopoulos |
Online Periodic Self-Test Scheduling for Real-Time Processor-Based Systems Dependability Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Dependable Secur. Comput. ![In: IEEE Trans. Dependable Secur. Comput. 6(2), pp. 152-158, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Laurie Murphy, Josh Tenenberg |
Do computer science students know what they know?: a calibration study of data structure knowledge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITiCSE ![In: Proceedings of the 10th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, ITiCSE 2005, Caparica, Portugal, June 27-29, 2005, pp. 148-152, 2005, ACM, 1-59593-024-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
calibration of knowledge, data structures, self-assessment, metacognition |
19 | Yizheng Zhou, Vijay Lakamraju, Israel Koren, C. M. Krishna 0001 |
Software-Based Failure Detection and Recovery in Programmable Network Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 18(11), pp. 1539-1550, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Programmable Network Interface Card (NIC), Single Event Upset (SEU), radiation induced faults, failure detection, self-testing |
19 | Stanislaw J. Piestrak |
Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(6), pp. 735-736, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
TSC Berger code checker, Berger code, totally self-checking circuit, self-testing checker, two-rail code |
19 | Amit Laknaur, Haibo Wang 0005 |
Built-In-Self-Testing Techniques for Programmable Capacitor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 434-439, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi |
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 158-163, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Kwanghyun Kim, Dong Sam Ha, Joseph G. Tront |
On using signature registers as pseudorandom pattern generators in built-in self-testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8), pp. 919-928, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
18 | Sandeep K. Venishetti, Ali Akoglu, Rahul Kalra |
Hierarchical Built-in Self-testing and FPGA Based Healing Methodology for System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 717-724, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Yizheng Zhou, Vijay Lakamraju, Israel Koren, C. Mani Krishna 0001 |
Software-Based Adaptive and Concurrent Self-Testing in Programmable Network Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS (1) ![In: 12th International Conference on Parallel and Distributed Systems, ICPADS 2006, Minneapolis, Minnesota, USA, July 12-15, 2006, pp. 525-532, 2006, IEEE Computer Society, 0-7695-2612-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Steffen Tarnick, Albrecht P. Stroele |
Embedded self-testing checkers for low-cost arithmetic codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 514-523, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos |
On the Design of Self-Testing Checkers for Modified Berger Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy, pp. 153-157, 2001, IEEE Computer Society, 0-7695-1290-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Sami Beydeda |
STECC: Selbsttestende Software-Komponenten. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inform. Forsch. Entwickl. ![In: Inform. Forsch. Entwickl. 21(3-4), pp. 243-253, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Self-testability, Control flow graph generation, Path-oriented testing, Component-based development |
17 | Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian |
Effective Software Self-Test Methodology for Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 592-597, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Andrzej Krasniewski |
Application-Dependent Testing of FPGA Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1260-1267, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Krishnendu Chakrabarty, John P. Hayes |
Cumulative balance testing of logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(1), pp. 72-83, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Hsiu-Ming Chang 0001, Kuan-Yu Lin, Chin-Hsuan Chen, Kwang-Ting Cheng |
A Built-in self-calibration scheme for pipelined ADCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 266-271, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey |
Embedded Software-Based Self-Test for Programmable Core-Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(4), pp. 18-27, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Christian Galke, Marcus Grabow, Heinrich Theodor Vierhaus |
Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 183-, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Andrzej Krasniewski, Slawomir Pilarski |
Circular Self-Test Path: A Low-Cost BIST Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 407-415, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
16 | Cecilia Metra, Michele Favalli, Bruno Riccò |
Embedded two-rail checkers with on-line testing ability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 145-150, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
embedded two-rail checkers, online testing ability, self-testing ability, compact structure, VLSI, logic testing, integrated circuit testing, design for testability, error detection, automatic testing, integrated logic circuits, two-rail code |
16 | Imtiaz P. Shaik, Michael L. Bushnell |
Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming . ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 393-399, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions |
16 | Imtiaz P. Shaik, Michael L. Bushnell |
A graph approach to DFT hardware placement for robust delay fault BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 177-182, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI |
16 | Leonardo Mariani, Mauro Pezzè, David Willmor |
Generation of Integration Tests for Self-Testing Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORTE Workshops ![In: Applying Formal Methods: Testing, Performance and M/ECommerce, FORTE 2004 Workshops The FormEMC, EPEW, ITM, Toledo, Spain, October 1-2, 2004, pp. 337-350, 2004, Springer, 3-540-23169-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
Instruction-Based Delay Fault Self-Testing of Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 933-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Andrzej Krasniewski |
Self-Testing of FPGA Delay Faults in the System Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 40-, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, BIST, random testing, delay faults |
16 | Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya |
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 205-, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Built-in self-test, TPG, delay faults, robust testing, two-pattern tests |
16 | Rupsa Chakraborty, Dipanwita Roy Chowdhury |
coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACRI ![In: Cellular Automata, 8th International Conference on Cellular Aotomata for Reseach and Industry, ACRI 2008, Yokohama, Japan, September 23-26, 2008. Proceedings, pp. 506-511, 2008, Springer, 978-3-540-79991-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Response-Analyzer, Built-in self-test, System-on-Chip, Cellular Automata, Test-Pattern-Generator |
16 | Anzhela Yu. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. Nikitin |
Designing FPGA based Self-Testing Checkers for m-out-of-n Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 49-53, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Ronitt Rubinfeld, Madhu Sudan 0001 |
Self-Testing Polynomial Functions Efficiently and Over Rational Domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Third Annual ACM/SIGACT-SIAM Symposium on Discrete Algorithms, 27-29 January 1992, Orlando, Florida, USA., pp. 23-32, 1992, ACM/SIAM, 0-89791-466-X. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP BibTeX RDF |
|
15 | Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(8), pp. 971-975, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis |
A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 271-276, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Marco Balboni, Davide Bertozzi |
Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AISTECS@HiPEAC ![In: Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2017, Stockholm, Sweden, January 25, 2017, pp. 12-17, 2017, ACM, 978-1-4503-5226-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
14 | Ching-Wen Lin, Chung-Ho Chen |
Unambiguous I-cache testing using software-based self-testing methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 1756-1759, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Diana Bodean, Ghenadie Bodean, Wajeb Gharibi |
Pseudo-Ring Testing Schemes and Algorithms of RAM Built-In and Embedded Self-Testing ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1106.3677, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
14 | Satoshi Mizutani, Toshio Nakagawa, Kodo Ito, Hiroaki Sandoh |
Optimal periodic testing policy for circuit with self-testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Math. Appl. ![In: Comput. Math. Appl. 51(2), pp. 363-370, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Sami Beydeda, Volker Gruhn |
Merging components and testing tools: The Self-Testing COTS Components (STECC) Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 29th EUROMICRO Conference 2003, New Waves in System Architecture, 3-5 September 2003, Belek-Antalya, Turkey, pp. 107-115, 2003, IEEE Computer Society, 0-7695-1996-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Kim T. Le, Kewal K. Saluja |
A Novel Approach for Testing Memories Using a Built-In Self Testing Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1986, Washington, D.C., USA, September 1986, pp. 830-839, 1986, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP BibTeX RDF |
|
14 | Tom W. Williams |
Sufficient Testing In A Self-Testing Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1984, Philadelphia, PA, USA, October 1984, pp. 167-173, 1984, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1984 |
DBLP BibTeX RDF |
|
14 | Jianxun Liu, Wen-Ben Jone |
An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 360-367, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Steffen Tarnick |
Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11162-11163, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Steffen Tarnick |
A Design Method for Embedded Self-Testing t-UED and BUED Code Checkers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 43-48, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Albrecht P. Stroele, Steffen Tarnick |
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 361-369, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Stanislaw J. Piestrak |
Design of minimal-level PLA self-testing checkers for m-out-of-n codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(2), pp. 264-272, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
14 | Ram Chillarege |
Self-testing software probe system for failure detection and diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASCON ![In: Proceedings of the 1994 Conference of the Centre for Advanced Studies on Collaborative Research, October 31 - November 3, 1994, Toronto, Ontario, Canada, pp. 10, 1994, IBM. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
diagnosis, detection, failure, isolation, software errors |
14 | Shambhu J. Upadhyaya, Kewal K. Saluja |
A new approach to the design of built-in self-testing PLAs for high fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 60-67, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
14 | S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter |
A Fast Signature Simulation Tool for Built-In Self-Testing Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 17-25, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
12 | Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich, Francisco Triviño |
A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs" [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 14(1), pp. 2:1-2:9, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
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