Search results for "self-testing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
63	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, George Xenoulis	Software-Based Self-Testing of Embedded Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	processor self-testing, Embedded processors, software-based self-testing, low-cost testing
50	Matthew K. Franklin, Juan A. Garay, Moti Yung	Self-Testing/Correcting Protocols (Extended Abstract).	DISC	1999	DBLP DOI BibTeX RDF
43	Stanislaw J. Piestrak	Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	embedded circuit, inverter-free circuit, totally self-testing circuit, concurrent error detection, Berger code, self-testing checker, two-rail code
36	Dimitris Nikolos	Self-Testing Embedded Two-Rail Checkers.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	parity tree, embedded self-testing, self testing, two-rail checker, parity checker
35	Li Chen, Sujit Dey	Software-based self-testing methodology for processor cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
35	Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng	Embedded hardware and software self-testing methodologies for processor cores.	DAC	2000	DBLP DOI BibTeX RDF
34	Tom Chen 0001, Glen Sunada	Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
33	Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey	Embedded software-based self-testing for SoC design.	DAC	2002	DBLP DOI BibTeX RDF	functional test, SoC test, VLSI test, microprocessor test
32	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Instruction-level test methodology for CPU core self-testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing
31	Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar	Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors.	ETS	2009	DBLP DOI BibTeX RDF	Chip multithreading, micro-processor testing, functional self-testing, test time optimization, multiprocessors, software-based self-testing
31	Dimitris Nikolos	Optimal Self-Testing Embedded Parity Checkers.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	Parity tree, embedded self-testing circuits, self-testing, two-rail checker, parity checker
31	Krishnendu Chakrabarty, John P. Hayes	Balance testing and balance-testable design of logic circuits.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	built-in self testing, design for testability, fault detection, fault coverage, testing methods
31	Xrysovalantis Kavousianos, Dimitris Nikolos	Self-exercising self testing k-order comparators.	VTS	1997	DBLP DOI BibTeX RDF	self testing k-order comparators, self-exercising comparators, equality comparator, fault tolerant cache memory, built-in self test, error correction codes, combinational circuit, error detection codes, broadcast networks
31	Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores.	ITC	2003	DBLP DOI BibTeX RDF
30	Ronald Stevens, Brittany Parsons, Tariq M. King	A self-testing autonomic container.	ACM Southeast Regional Conference	2007	DBLP DOI BibTeX RDF	testing, validation, autonomic computing
30	Steffen Tarnick	Design of Embedded Self-Testing Checkers for t-UED and BUED Codes.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	t-unidirectional error detecting (t-UED) codes, burst unidirectional error detecting (BUED) codes, averaging circuits, embedded checkers, self-testing checkers
28	Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Functional Self-Testing for Bus-Based Symmetric Multiprocessors.	DATE	2008	DBLP DOI BibTeX RDF
28	George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units.	IEEE Trans. Dependable Secur. Comput.	2009	DBLP DOI BibTeX RDF
27	Amit Laknaur, Sai Raghuram Durbha, Haibo Wang 0005	Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	programmable capacitor array, built-in-self-testing, analog testing, field programmable analog array
27	Cecilia Metra, Michele Favalli, Bruno Riccò	Compact and low power on-line self-testing voting scheme.	DFT	1997	DBLP DOI BibTeX RDF	on-line self-testing voting scheme, fault-tolerant techniques, reliability, power consumption, majority voting, triple modular redundancy, area overhead, majority logic, TMR systems
27	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Constantin Halatsis	A concurrent built-in self-test architecture based on a self-testing RAM.	IEEE Trans. Reliab.	2005	DBLP DOI BibTeX RDF
27	Xiaoliang Bai, Sujit Dey, Janusz Rajski	Self-test methodology for at-speed test of crosstalk in chip interconnects.	DAC	2000	DBLP DOI BibTeX RDF
26	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Instruction-Based Self-Testing of Processor Cores.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	processor cores, built-in self-test, instruction set, at-speed testing, software-based self test
26	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Instruction-Based Self-Testing of Processor Cores.	VTS	2002	DBLP DOI BibTeX RDF
25	Eiji Fujiwara, Nobuo Mutoh, Kohji Matsuoka	A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	self-verification, error-detection ability, group-parity prediction checker, self-testing, Built-in testing, duplication, self-checking checker, fault-detection ability
25	Steffen Tarnick	Self-Testing Embedded Borden t -UED Code Checkers for t = 2 k q - 1 with q = 2 m - 1.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Borden codes, Embedded checkers, Code translators, AN codes, Self-testing checkers
25	Stanislaw J. Piestrak	Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	counters of 1s, m-out-of-n (m/n) codes, concurrent error detection, on-line testing, self-checking circuit, unidirectional errors, parallel counters, unordered codes, self-testing checker
25	Stanislaw J. Piestrak	Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes.	DFT	1997	DBLP DOI BibTeX RDF	systematic unidirectional error detecting code, t-UED Bose-Lin code, burst UED code, multi-output threshold circuit, encoder, automatic testing, logic function, Berger code, hardware complexity, self-testing checker
25	Kazuo Kawakubo, Koji Tanaka, Hiromi Hiraishi	Formal Verification Of Self-Testing Properties Of Combinational Circuits.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	self-testing properties, logic function manipulation, decision function, output code words, self-checking logic, mutiple-input multiple-output circuit, fault tolerance, formal verification, combinational circuits, combinational circuits, binary decision diagrams, stuck-at faults, satisfiability problem, characteristic functions, Berger code
25	Hussam Y. Abujbara, Sami A. Al-Arian	Self-testing and self-reconfiguration architecture for 2-D WSI arrays.	SPDP	1990	DBLP DOI BibTeX RDF
24	Ravi Kumar 0001, D. Sivakumar 0001	Efficient Self-Testing/Self-Correction of Linear Recurrences.	FOCS	1996	DBLP DOI BibTeX RDF	efficient self-testing, efficient self-correction, self-tester design, self-corrector design, result-checkers, linear function testing, counting arguments, matrix twist, convolution identities, VLSI chip testing, randomness-efficient self-tester, rational domains, signal processing, finite fields, program testing, polynomials, reduction, functions, spectral analysis, matrix groups, linear recurrences, control engineering
24	Nur A. Touba, Edward J. McCluskey	Applying two-pattern tests using scan-mapping.	VTS	1996	DBLP DOI BibTeX RDF	scan-mapping, combinational mapping logic, logic testing, built-in self test, built-in self-testing, fault coverage, delay faults, pseudo-random testing, deterministic testing, two-pattern tests
24	Adam Kristof	Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections.	ED&TC	1997	DBLP DOI BibTeX RDF
23	Y. You, John P. Hayes	Implementation of VLSI self-testing by regularization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
23	Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Low-Cost Software-Based Self-Testing of RISC Processor Cores.	DATE	2003	DBLP DOI BibTeX RDF
23	Andrzej Krasniewski, Alexander Albicki	Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications.	DAC	1985	DBLP DOI BibTeX RDF
23	Frédéric Magniez	Multi-Linearity Self-Testing with Relative Error.	Theory Comput. Syst.	2005	DBLP DOI BibTeX RDF
22	Timothy J. Dysart, Peter M. Kogge	Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder.	DFT	2007	DBLP DOI BibTeX RDF
21	Steven S. Gorshe, Bella Bose	A self-checking ALU design with efficient codes.	VTS	1996	DBLP DOI BibTeX RDF	self-checking ALU design, self-testing ALU, VLSI, logic testing, built-in self test, integrated circuit testing, logic design, error detection codes, error detecting codes, integrated logic circuits, unidirectional errors
21	Peter Böhlau	Zero Aliasing Compression Based on Groups of Weakly Independent Outputs in Circuits with High Complexity for Two Fault Models.	EDCC	1994	DBLP DOI BibTeX RDF	zero aliasing, self-testing circuits, functional properties, groupability, weakly independent outputs, built-in self-test
21	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Built-in sequential fault self-testing of array multipliers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
21	Jaeki Yoo, Edward Lee, Earl E. Swartzlander Jr.	A self-testing method for the pipelined A/D converter.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
21	Ravi Kumar 0001, D. Sivakumar 0001	On Self-Testing without the Generator Bottleneck.	FSTTCS	1995	DBLP DOI BibTeX RDF
20	Alain E. Ramirez, Barbara Quinones-Morales, Tariq M. King	A self-testing autonomic job scheduler.	ACM Southeast Regional Conference	2008	DBLP DOI BibTeX RDF	autonomic computing, job scheduling, self-testing
20	Stanislaw J. Piestrak	Design of Self-Testing Checkers for Borden Codes.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Borden code, easily-testable circuit, multioutput threshold circuit, optimal t-unidirectional error detecting code, concurrent error detection, unidirectional errors, self-testing checker, unidirectional error detecting code
20	Egor S. Sogomonyan, Michael Gössel	Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems.	VTS	1996	DBLP DOI BibTeX RDF	circuit feedback, concurrently self-testing embedded checker, ultra-reliable fault-tolerant system, parity codes, design, monitoring, built-in self test, integrated circuit testing, linear feedback shift register, error detection codes, error detection code, shift registers, arithmetic codes, Berger codes, duplication codes, integrated circuit reliability, corrector
20	Seyed H. Hosseini, Nizar Jamal	Efficient Distributed Algorithms for Self Testing of Multiple Processor Systems.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	interprocessor links, testing overhead, performance evaluation, performance, reliability, distributed algorithms, fault tolerant computing, multiprocessing systems, automatic testing, simulation results, self testing, multiple processor systems, dynamic testing
20	Stanislaw J. Piestrak	Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	complexity, logic testing, logic design, automatic testing, digital arithmetic, logic circuits, error-detecting codes, error detection codes, arithmetic codes, gate levels, self-testing checkers
20	Yuval Tamir, Carlo H. Séquin	Design and Application of Self-Testing Comparators Implemented with MOS PLA's.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	two-rail code checker, duplication and matching, faults in VLSI circuits, MOS PLA fault model, self-testing comparator, programmable logic array, Concurrent error detection
20	Zeev Barzilai, Don Coppersmith, Arnold L. Rosenberg	Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	VLSI self-testing, Linear feedback shift registers (LFSR), primitive polynomials
19	Sami Beydeda	Self-Metamorphic-Testing Components.	COMPSAC (2)	2006	DBLP DOI BibTeX RDF
19	Marcos A. Kiwi, Frédéric Magniez, Miklos Santha	Exact and Approximate Testing/Correcting of Algebraic Functions: A Survey.	Theoretical Aspects of Computer Science	2000	DBLP DOI BibTeX RDF
19	Manuel Blum 0001, Bruno Codenotti, Peter Gemmell, Troy Shahoumian	Self-Correcting for Function Fields Transcendental Degree.	ICALP	1995	DBLP DOI BibTeX RDF
19	Dimitris Gizopoulos	Online Periodic Self-Test Scheduling for Real-Time Processor-Based Systems Dependability Enhancement.	IEEE Trans. Dependable Secur. Comput.	2009	DBLP DOI BibTeX RDF
19	Laurie Murphy, Josh Tenenberg	Do computer science students know what they know?: a calibration study of data structure knowledge.	ITiCSE	2005	DBLP DOI BibTeX RDF	calibration of knowledge, data structures, self-assessment, metacognition
19	Yizheng Zhou, Vijay Lakamraju, Israel Koren, C. M. Krishna 0001	Software-Based Failure Detection and Recovery in Programmable Network Interfaces.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	Programmable Network Interface Card (NIC), Single Event Upset (SEU), radiation induced faults, failure detection, self-testing
19	Stanislaw J. Piestrak	Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	TSC Berger code checker, Berger code, totally self-checking circuit, self-testing checker, two-rail code
19	Amit Laknaur, Haibo Wang 0005	Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.	ISQED	2005	DBLP DOI BibTeX RDF
19	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
19	Kwanghyun Kim, Dong Sam Ha, Joseph G. Tront	On using signature registers as pseudorandom pattern generators in built-in self-testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
18	Sandeep K. Venishetti, Ali Akoglu, Rahul Kalra	Hierarchical Built-in Self-testing and FPGA Based Healing Methodology for System-on-a-Chip.	AHS	2007	DBLP DOI BibTeX RDF
18	Yizheng Zhou, Vijay Lakamraju, Israel Koren, C. Mani Krishna 0001	Software-Based Adaptive and Concurrent Self-Testing in Programmable Network Interfaces.	ICPADS (1)	2006	DBLP DOI BibTeX RDF
18	Steffen Tarnick, Albrecht P. Stroele	Embedded self-testing checkers for low-cost arithmetic codes.	ITC	1998	DBLP DOI BibTeX RDF
18	Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos	On the Design of Self-Testing Checkers for Modified Berger Codes.	IOLTW	2001	DBLP DOI BibTeX RDF
17	Sami Beydeda	STECC: Selbsttestende Software-Komponenten.	Inform. Forsch. Entwickl.	2007	DBLP DOI BibTeX RDF	Self-testability, Control flow graph generation, Path-oriented testing, Component-based development
17	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Effective Software Self-Test Methodology for Processor Cores.	DATE	2002	DBLP DOI BibTeX RDF
17	Andrzej Krasniewski	Application-Dependent Testing of FPGA Delay Faults.	EUROMICRO	1999	DBLP DOI BibTeX RDF
17	Krishnendu Chakrabarty, John P. Hayes	Cumulative balance testing of logic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
17	Hsiu-Ming Chang 0001, Kuan-Yu Lin, Chin-Hsuan Chen, Kwang-Ting Cheng	A Built-in self-calibration scheme for pipelined ADCs.	ISQED	2009	DBLP DOI BibTeX RDF
17	Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey	Embedded Software-Based Self-Test for Programmable Core-Based Designs.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
17	Christian Galke, Marcus Grabow, Heinrich Theodor Vierhaus	Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip.	IOLTS	2003	DBLP DOI BibTeX RDF
17	Andrzej Krasniewski, Slawomir Pilarski	Circular Self-Test Path: A Low-Cost BIST Technique.	DAC	1987	DBLP DOI BibTeX RDF
16	Cecilia Metra, Michele Favalli, Bruno Riccò	Embedded two-rail checkers with on-line testing ability.	VTS	1996	DBLP DOI BibTeX RDF	embedded two-rail checkers, online testing ability, self-testing ability, compact structure, VLSI, logic testing, integrated circuit testing, design for testability, error detection, automatic testing, integrated logic circuits, two-rail code
16	Imtiaz P. Shaik, Michael L. Bushnell	Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming .	VTS	1995	DBLP DOI BibTeX RDF	low overhead delay-fault BIST, constrained quadratic 0-1 programming, built-in self testing model, weighted signed graph balancing problem, VLSI, logic testing, delays, built-in self test, integrated circuit testing, logic design, automatic testing, integrated circuit design, quadratic programming, circuit design, digital integrated circuits, hazards and race conditions
16	Imtiaz P. Shaik, Michael L. Bushnell	A graph approach to DFT hardware placement for robust delay fault BIST.	VLSI Design	1995	DBLP DOI BibTeX RDF	graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI
16	Leonardo Mariani, Mauro Pezzè, David Willmor	Generation of Integration Tests for Self-Testing Components.	FORTE Workshops	2004	DBLP DOI BibTeX RDF
16	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-Based Delay Fault Self-Testing of Processor Cores.	VLSI Design	2004	DBLP DOI BibTeX RDF
16	Andrzej Krasniewski	Self-Testing of FPGA Delay Faults in the System Environment.	IOLTW	2000	DBLP DOI BibTeX RDF	FPGA, BIST, random testing, delay faults
16	Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya	Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults.	VLSI Design	1998	DBLP DOI BibTeX RDF	Built-in self-test, TPG, delay faults, robust testing, two-pattern tests
16	Rupsa Chakraborty, Dipanwita Roy Chowdhury	coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips.	ACRI	2008	DBLP DOI BibTeX RDF	Response-Analyzer, Built-in self-test, System-on-Chip, Cellular Automata, Test-Pattern-Generator
16	Anzhela Yu. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. Nikitin	Designing FPGA based Self-Testing Checkers for m-out-of-n Codes.	IOLTS	2003	DBLP DOI BibTeX RDF
16	Ronitt Rubinfeld, Madhu Sudan 0001	Self-Testing Polynomial Functions Efficiently and Over Rational Domains.	SODA	1992	DBLP BibTeX RDF
15	Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
15	Andreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs.	IOLTS	2007	DBLP DOI BibTeX RDF
14	Marco Balboni, Davide Bertozzi	Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
14	Ching-Wen Lin, Chung-Ho Chen	Unambiguous I-cache testing using software-based self-testing methodology.	ISCAS	2014	DBLP DOI BibTeX RDF
14	Diana Bodean, Ghenadie Bodean, Wajeb Gharibi	Pseudo-Ring Testing Schemes and Algorithms of RAM Built-In and Embedded Self-Testing	CoRR	2011	DBLP BibTeX RDF
14	Satoshi Mizutani, Toshio Nakagawa, Kodo Ito, Hiroaki Sandoh	Optimal periodic testing policy for circuit with self-testing.	Comput. Math. Appl.	2006	DBLP DOI BibTeX RDF
14	Sami Beydeda, Volker Gruhn	Merging components and testing tools: The Self-Testing COTS Components (STECC) Strategy.	EUROMICRO	2003	DBLP DOI BibTeX RDF
14	Kim T. Le, Kewal K. Saluja	A Novel Approach for Testing Memories Using a Built-In Self Testing Technique.	ITC	1986	DBLP BibTeX RDF
14	Tom W. Williams	Sufficient Testing In A Self-Testing Environment.	ITC	1984	DBLP BibTeX RDF
14	Jianxun Liu, Wen-Ben Jone	An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects.	ICCD	2007	DBLP DOI BibTeX RDF
14	Steffen Tarnick	Self-Testing Embedded Checkers for Bose-Lin, Bose, and a Class of Borden Codes.	DATE	2003	DBLP DOI BibTeX RDF
14	Steffen Tarnick	A Design Method for Embedded Self-Testing t-UED and BUED Code Checkers.	IOLTS	2003	DBLP DOI BibTeX RDF
14	Albrecht P. Stroele, Steffen Tarnick	Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code.	VTS	1999	DBLP DOI BibTeX RDF
14	Stanislaw J. Piestrak	Design of minimal-level PLA self-testing checkers for m-out-of-n codes.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
14	Ram Chillarege	Self-testing software probe system for failure detection and diagnosis.	CASCON	1994	DBLP BibTeX RDF	diagnosis, detection, failure, isolation, software errors
14	Shambhu J. Upadhyaya, Kewal K. Saluja	A new approach to the design of built-in self-testing PLAs for high fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
14	S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter	A Fast Signature Simulation Tool for Built-In Self-Testing Circuits.	DAC	1987	DBLP DOI BibTeX RDF
12	Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich, Francisco Triviño	A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs" [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106].	ACM Trans. Embed. Comput. Syst.	2015	DBLP DOI BibTeX RDF