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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2164 occurrences of 1285 keywords
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Results
Found 9468 publication records. Showing 9468 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
78 | Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor |
Bridging pre-silicon verification and post-silicon validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 94-95, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
post-silicon, pre-silicon, verification, validation |
59 | Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici |
Post-silicon validation opportunities, challenges and recent advances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 12-17, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
post-silicon validation |
57 | Sung-Boem Park, Anne Bracy, Hong Wang 0003, Subhasish Mitra |
BLoG: post-silicon bug localization in processors using bug localization graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 368-373, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
IFRA, BLoG, silicon debug, post-silicon validation |
57 | Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang |
Visibility enhancement for silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 13-18, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
silicon validation, functional verification, silicon debug |
56 | Jagannath Keshava, Nagib Hakim, Chinna Prudvi |
Post-silicon validation challenges: how EDA and academia can help. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 3-7, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
design, verification, test, validation, emulation |
54 | Lin Xie, Azadeh Davoodi, Kewal K. Saluja |
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 274-279, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
post-silicon diagnosis, process variations |
54 | Yu Huang 0005, Wu-Tung Cheng |
Using embedded infrastructure IP for SOC post-silicon verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 674-677, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA core, infrastructure IP (I-IP), post-silicon verification, transaction-based verification |
53 | Sandip Ray, Warren A. Hunt Jr. |
Connecting pre-silicon and post-silicon verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 160-163, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
53 | A. Richard Newton |
Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 501, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
50 | Rajani Kuchipudi, Hamid Mahmoodi |
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 27-32, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
50 | Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak |
On Silicon-Based Speed Path Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 35-41, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
50 | Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng |
A path-based methodology for post-silicon timing validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 713-720, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
48 | Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu |
Diagnosing Silicon Failures Based on Functional Test Patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA, pp. 94-98, 2006, IEEE Computer Society, 978-0-7695-2839-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fault diagnosis, Silicon debug, design for debug |
48 | Chirag S. Patel |
Silicon carrier for computer systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 857-862, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
chip-package co-design, electrical modeling, micro-bumps, silicon carrier, computer system, CMOS scaling, system on package |
45 | Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst |
Silicon VLSI processing architectures incorporating integrated optoelectronic devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 17-27, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
silicon, integrated optoelectronics, integrated optoelectronic interconnects, I/O communication, inter-chip communication, silicon VLSI processing architectures, digital SIMD processors, frame processing, three dimensional stacked chips, thin film detector array, image processing, image processing, VLSI, optical interconnections, integrated circuit interconnections, Si |
44 | Miron Abramovici |
In-System Silicon Validation and Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(3), pp. 216-223, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Ilya Wagner, Valeria Bertacco |
Reversi: Post-silicon validation system for modern microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 307-314, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Seiji Kameda, Tetsuya Yagi |
An analog silicon retina with multichip configuration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Neural Networks ![In: IEEE Trans. Neural Networks 17(1), pp. 197-210, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Christophe Lécuyer, David C. Brock |
Biographies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Ann. Hist. Comput. ![In: IEEE Ann. Hist. Comput. 28(3), pp. 89-95, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Gordon Moore, semiconductor industry, silicon technology, silicon device manufacture, Fairchild Semiconductor, Shockley Semiconductor, microprocessor, integrated circuit, DRAM, personal computer, chemistry, Moore's law, Intel |
42 | Georgios Karakonstantis, Kaushik Roy 0001 |
Low-Power and Variation-Tolerant Application-Specific System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 249-292, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Sachin S. Sapatnekar |
Statistical Design of Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 109-149, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Shreyas Sen, Vishwanath Natarajan, Abhijit Chatterjee |
Low-Power Adaptive Mixed Signal/RF Circuits and Systems and Self-Healing Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 293-333, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Swaroop Ghosh |
Effect of Variations and Variation Tolerance in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 83-108, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon |
Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 381-432, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Wei Zhang 0012, James Williamson, Li Shang |
Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 41-80, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Aditya Bansal, Rahul M. Rao |
Variations: Sources and Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 3-39, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Nikil Mehta, André DeHon |
Low-Power Techniques for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 337-363, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Bipul C. Paul, Arijit Raychowdhury |
Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 185-207, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Nikil Mehta, André DeHon |
Variation and Aging Tolerance in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 365-380, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Hamid Mahmoodi |
Low-Power and Variation-Tolerant Memory Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 151-183, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Meeta Sharma Gupta, Pradip Bose |
Variation-Tolerant Microprocessor Architecture at Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 211-247, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
42 | Dae Hyun Kim 0004, Saibal Mukhopadhyay, Sung Kyu Lim |
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 85-92, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
wirelength distribution, rent's rule, 3d ic, tsv, interconnect prediction, through silicon via |
42 | Dennis Sylvester, David T. Blaauw, Eric Karl |
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(6), pp. 484-490, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
unpredictable silicon, runtime self-diagnosis, adaptivity, architecture, process variations, self-healing, ElastIC, technology scaling |
40 | John P. Denton, Sang Woo Pae, Gerold W. Neudeck |
Vertical integration of submicron MOSFETs in two separate layers of SOI islands formed by silicon epitaxial lateral overgrowth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001, pp. 129-132, 2001, ACM, 1-58113-351-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
SOI MOSFET, selective epitaxial growth, silicon, silicon on insulator, thin film SOI, three dimensional circuits |
38 | Andrew DeOrio, Ilya Wagner, Valeria Bertacco |
Dacota: Post-silicon validation of the memory subsystem in multi-core designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 405-416, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Eli Yablonovitch |
Can nano-photonic silicon circuits become an INTRA-chip interconnect technology? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 309, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Ernst Rank, Ulrich Weinert |
A simulation system for diffusive oxidation of silicon: a two-dimensional finite element approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(5), pp. 543-550, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
37 | Hee-Dong Kim, Ho-Myoung An, Yujeong Seo, Yongjie Zhang, Jongsun Park 0001, Tae Geun Kim |
Hydrogen passivation effects under negative bias temperature instability stress in metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon capacitors for flash memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 50(1), pp. 21-25, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
36 | Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan |
Online cache state dumping for processor debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 358-363, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cache compression, processor debug, silicon debug, design for debug, post-silicon validation |
36 | Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu |
A General Failure Candidate Ranking Framework for Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 352-358, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Silicon Debug |
36 | Shi-Hua Luo, Jiu-sun Zeng |
BF Hot Metal Silicon Content Prediction Using Unsupervised Fuzzy Clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFIE ![In: Fuzzy Information and Engineering, Proceedings of the Second International Conference of Fuzzy Information and Engineering, ICFIE 2007, May 13-16, 2007, Guangzhou, China, pp. 411-418, 2007, Springer, 978-3-540-71440-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Silicon Content Prediction, Unsupervised Fuzzy Clustering |
36 | Xuesong Han |
Investigation of Surface Integrity in the Case of Chemical Mechanical Polishing Silicon Wafer by Molecular Dynamics Simulation Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAT ![In: Advances in Artificial Reality and Tele-Existence, 16th International Conference on Artificial Reality and Telexistence, ICAT 2006, Hangzhou, China, November 29 - December 1, 2006, Proceedings, pp. 651-659, 2006, Springer, 3-540-49776-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
silicon wafer, vacancy, dislocation, molecular dynamics, Chemical mechanical polishing |
36 | Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel |
Automatic generation of breakpoint hardware for silicon debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 514-517, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
hardware-breakpoints, design-flow, silicon-debug, design-for-debug |
36 | R. Dean Adams, Phil Shephard III |
Silicon-on-Insulator Technology Impacts on SRAM Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 43-48, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Fault modeling and simulation, Silicon On Insulator (SOI), Memory testing |
36 | Robert C. Frye, King L. Tai, Maureen Y. Lau, Thaddeus J. Gabara |
Trends in Silicon-On-Silicon Multichip Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 10(4), pp. 8-17, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
35 | Soon Fatt Yoon |
III-V/Si integration: potential and outlook for integrated low power micro and nanosystems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009, pp. 17-18, 2009, ACM. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
heterogeneous integration |
33 | Vassilios Gerousis |
Physical design implementation for 3D IC: methodology and tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 57, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
3D IC stack, micro-bump, physical design tools, silicon interposer, methodology, tsv |
33 | Jing Li 0073, Aditya Bansal, Swaroop Ghosh, Kaushik Roy 0001 |
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(3), pp. 13:1-13:19, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Low-temperature polycrystalline silicon (LTPS), grain boundary (GB), inherent variation, thin-film transistor (TFT), generic, reconfigurable, hybrid system, BIST, DFT, 3D integration |
33 | Pranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy |
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 117-128, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
interconnection networks, nanophotonics |
33 | Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir |
Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 374-379, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
data mining, learning, timing analysis, delay test |
33 | Mahesh Ketkar, Eli Chiprout |
A microarchitecture-based framework for pre- and post-silicon power delivery analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 179-188, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Jürgen Kogler, Christoph Sulzbachner, Wilfried Kubinger |
Bio-inspired Stereo Vision System with Silicon Retina Imagers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICVS ![In: Computer Vision Systems, 7th International Conference on Computer Vision Systems, ICVS 2009, Liège, Belgium, October 13-15, 2009, Proceedings, pp. 174-183, 2009, Springer, 978-3-642-04666-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Charbel J. Akl, Rafic A. Ayoubi, Magdy A. Bayoumi |
Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 794-798, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Kwang-Ting (Tim) Cheng |
Effective silicon debug is key for time to money. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(3), pp. 204, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Feng Wang 0004, Xiaoxia Wu, Yuan Xie 0001 |
Variability-driven module selection with joint design time optimization and post-silicon tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 2-9, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Andrew DeOrio, Adam Bauserman, Valeria Bertacco |
Post-silicon verification for cache coherence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 348-355, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Davide Pandini, Giuseppe Desoli, Alessandro Cremonesi |
Computing and design for software and silicon manufacturing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 122-127, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | R. Takami, Kazuhiro Shimonomura, Seiji Kameda, Tetsuya Yagi |
An image pre-processing system employing neuromorphic 100×100 pixel silicon retina [robot vision applications]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2771-2774, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Carol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger |
Silicon Symptoms to Solutions: Applying Design for Debug Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 664-672, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Ranjit Singh, Low Lee Ngo, Ho Soon Seng, Frederick Neo Chwee Mok |
A Silicon Piezoresistive Pressure Sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 181-186, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Chung-Yu Wu, Hsin-Chin Jiang |
An improved BJT-based silicon retina with tunable image smoothing capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(2), pp. 241-248, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Walter Bohmayr, Alexander Burenkov, Jürgen Lorenz, Heiner Ryssel, Siegfried Selberherr |
Monte Carlo simulation of silicon amorphization during ion implantation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(12), pp. 1236-1243, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi |
DCT/IDCT processor for HDTV developed with dsp silicon compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 5(2-3), pp. 151-158, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
33 | Abhay B. Bulsari, Henrik Saxén |
Artificial Neural Networks for Predicting Silicon Content in Raw Iron From Blast Furnaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCI ![In: Advances in Computing and Information - ICCI'91, International Conference on Computing and Information, Ottawa, Canada, May 27-29, 1991, Proceedings, pp. 642-644, 1991, Springer, 3-540-54029-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
30 | Scott Beamer, Chen Sun 0003, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic |
Re-architecting DRAM memory systems with monolithically integrated silicon photonics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 129-140, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dram architecture, energy-efficiency, silicon photonics |
30 | Lin Xie, Azadeh Davoodi |
Representative path selection for post-silicon timing prediction under variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 386-391, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
process variations, post-silicon validation |
30 | Qunzeng Liu, Sachin S. Sapatnekar |
Synthesizing a representative critical path for post-silicon delay prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 183-190, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
post-silicon optimization, representative critical path |
30 | Scott Beamer, Krste Asanovic, Christopher Batten, Ajay Joshi, Vladimir Stojanovic |
Designing multi-socket systems using silicon photonics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009, pp. 521-522, 2009, ACM, 978-1-60558-498-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multi-socket, silicon photonics |
30 | Kelageri Nagaraj, Sandip Kundu |
Process variation mitigation via post silicon clock tuning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 227-232, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
post-silicon tuning, performance, process variation |
30 | Xiao Liu 0011, Qiang Xu 0001 |
Interconnection fabric design for tracing signals in post-silicon validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 352-357, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
trace-based debug, post-silicon validation |
30 | XingLong Guo, Yan Jin, Lei Liu, WeiXia Ouyang, ZongSheng Lai |
Design and fabrication of miniature antenna based on silicon substrate for wireless communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(5), pp. 586-591, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
miniature antenna, high-resistivity silicon (HR-Si), IC process |
30 | Nathaniel J. August |
A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 423-428, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
pre-silicon, validation, mixed-signal |
30 | Joon-Sung Yang, Nur A. Touba |
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 345-351, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Trace Buffer Observation Window, Two-Dimensional (2-D) Compaction, Cycling Register, Silicon Debug, MISR |
30 | Vishal Khandelwal, Ankur Srivastava 0001 |
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 11-18, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
post-silicon tunability, variability, stochastic optimization, timing optimization, gate sizing |
30 | David Geer |
Silicon Optics Aims to Combine the Best of Both Worlds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 39(6), pp. 16-19, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
silicon optics, optical systems, computing technology |
30 | John R. Long |
Next-Generation Narrowband RF Front-Ends in Silicon IC Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 275-280, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
narrowband circuits, silicon IC technology, RF design |
30 | Bryan Preas, Massoud Pedram, Don Curry |
Automatic Layout of Silicon-on-Silicon Hybrid Packages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 394-399, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
29 | Rosemary M. Francis, Simon W. Moore |
FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 285, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
tdm wiring, fpga, routing |
29 | Wei Huang 0004, Kevin Skadron, Sudhanva Gurumurthi, Robert J. Ribando, Mircea R. Stan |
Differentiating the roles of IR measurement and simulation for power and temperature-aware design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings, pp. 1-10, 2009, IEEE Computer Society, 978-1-4244-4184-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Pouria Bastani, Kip Killpack, Li-C. Wang, Eli Chiprout |
Speedpath prediction based on learning from a small set of examples. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 217-222, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
speedpath, learning, timing analysis |
29 | Qing K. Zhu, Paige Kolze |
Metal Fix and Power Network Repair for SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 33-37, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Michel Côté, Philippe Hurat |
Standard Cell Printability Grading and Hot Spot Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 264-269, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Jean-Pierre Heliot, Florent Parmentier, Marie-Pierre Baron |
LYS: A Solution for System on Chip (SoC) Production Cost and Time to Volume Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 85-89, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Gilles-Eric Descamps, Satish Bagalkotkar, Subramaniam Ganesan, Satish Iyengar, Alain Pirson |
Design of a 17-million gate network processor using a design factory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 844-849, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Robert P. Colwell, Bob Brennan |
Intel's Formal Verification Experience on the Willamette Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Theorem Proving in Higher Order Logics, 13th International Conference, TPHOLs 2000, Portland, Oregon, USA, August 14-18, 2000, Proceedings, pp. 106-107, 2000, Springer, 3-540-67863-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Roel Baets, Ananth Z. Subramanian, Stephane Clemmen, Bart Kuyken, Peter Bienstman, Nicolas Le Thomas, Gunther Roelkens, Dries Van Thourhout, Philippe Hélin, Simone Severi |
Silicon photonics: Silicon nitride versus silicon-on-insulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OFC ![In: Optical Fiber Communications Conference and Exhibition, OFC 2016, Anaheim, CA, USA, March 20-24, 2016, pp. 1-3, 2016, IEEE, 978-1-9435-8007-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
27 | Ricky W. Chuang, Mao-Teng Hsu, Shen-Horng Chou, Yao-Jen Lee |
Silicon Mach-Zehnder Waveguide Interferometer on Silicon-on-Silicon (SOS) Substrate Incorporating the Integrated Three-Terminal Field-Effect Device as an Optical Signal Modulation Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 94-C(7), pp. 1173-1178, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
27 | John U. Knickerbocker, Chirag S. Patel, Paul S. Andry, Cornelia K. Tsang, L. Paivikki Buchwalter, Edmund J. Sprogis, Hua Gan, Raymond R. Horton, Robert J. Polastre, Steven L. Wright, John M. Cotte |
3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 41(8), pp. 1718-1725, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | C. K. Wong, Hei Wong, Mansun Chan, Chi-Wah Kok, H. P. Chan |
Minimizing hydrogen content in silicon oxynitride by thermal oxidation of silicon-rich silicon nitride. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 46(12), pp. 2056-2061, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Ingvar Åberg |
Transport in thin-body Metal oxide semiconductor field-effect transistors fabricated in strained silicon and strained silicon/silicon-germanium heterostructures on insulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
RDF |
|
27 | John U. Knickerbocker, Chirag S. Patel, Paul S. Andry, Cornelia K. Tsang, L. Paivikki Buchwalter, Edmund J. Sprogis, Hua Gan, Raymond R. Horton, Robert J. Polastre, Steven L. Wright, Christian D. Schuster, Christian W. Baks, Fuad E. Doany, Joanna Rosner, Steven Cordes |
Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, CICC 2005, DoubleTree Hotel, San Jose, California, USA, September 18-21, 2005, pp. 659-662, 2005, IEEE, 0-7803-9023-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | M. C. Poon, Y. Gao, Ted Chi-Wah Kok, A. M. Myasnikov, Hei Wong |
SIMS study of silicon oxynitride prepared by oxidation of silicon-rich silicon nitride layer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 41(12), pp. 2071-2074, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Xiang Zhang, Ahmed Louri |
A multilayer nanophotonic interconnection network for on-chip many-core communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 156-161, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
interconnection networks, CMP, 3D, silicon photonics |
27 | Yoonjung Yang, Gilsoo Cho |
Novel Stretchable Textile-Based Transmission Bands: Electrical Performance and Appearance after Abrasion/Laundering, and Wearability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCI (3) ![In: Human-Computer Interaction. Ambient, Ubiquitous and Intelligent Interaction, 13th International Conference, HCI International 2009, San Diego, CA, USA, July 19-24, 2009, Proceedings, Part III, pp. 806-813, 2009, Springer, 978-3-642-02579-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
stretchable textile-based transmission band, silicon-coated stainless steel multifilament yarn, abrasion, laundering, electrical resistance, MP3 player jacket, wear sensation, image analysis |
27 | Roto Le, Sherief Reda, R. Iris Bahar |
High-performance, cost-effective heterogeneous 3D FPGA architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 286, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fpga, heterogeneous, 3d ic, switch box, through silicon via |
27 | Weiwu Hu, Jian Wang |
Making Effective Decisions in Computer Architects' Real-World: Lessons and Experiences with Godson-2 Processor Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 23(4), pp. 620-632, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
correlation design, balanced design, Pico-architecture design, work-on-silicon, optimized design, superscalar architecture |
27 | Shiyan Hu, Jiang Hu |
Unified adaptivity optimization of clock and logic signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 125-130, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
clock signal tuning, logic signal tuning, post-silicon tuning, robustness, variation |
27 | T. M. Mak, Sani R. Nassif |
Guest Editors' Introduction: Process Variation and Stochastic Design and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(6), pp. 436-437, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
silicon manufacturing processes, adaptive circuits, process variation, process monitoring, subthreshold leakage |
27 | Jari Järvinen, Juha Haataja, Jari Hämäläinen |
Industrial Applications: Challenges in Modeling and Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARA ![In: Applied Parallel Computing, New Paradigms for HPC in Industry and Academia, 5th International Workshop, PARA 2000 Bergen, Norway, June 18-20, 2000 Proceedings, pp. 1-16, 2000, Springer, 3-540-41729-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
multi-physics, paper machines, silicon crystals, Modeling, parallel computing, computing, industry, numerical methods, multi-scale |
27 | David Parry 0001 |
Scalability in computing for today and tomorrow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA, pp. 12-31, 1997, IEEE Computer Society, 0-8186-7913-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
synergistic combination, performance growth, current multiprocessor alternatives, scalable SMP, Silicon Graphics Origin multiprocessor, S/sup 2/MP memory architecture, core technologies, scalability, system architecture, shared-memory multiprocessors, shared memory systems |
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