Search results for "subcircuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
69	Irith Pomeranz, Sudhakar M. Reddy	On the feasibility of fault simulation using partial circuit descriptions.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	partial circuit description, gate-level circuits, subcircuits, logic testing, fault simulation, fault simulation, memory requirements
57	Dhruva R. Chakrabarti, Ajai Jain	An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph
55	Itsuo Takanami, Tadayoshi Horita	Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits.	DFT	1997	DBLP DOI BibTeX RDF	self-reconstruction, digital neural circuits, Hopfield-type neural algorith, 1 1/2 -track switches, compensation paths, subcircuits, stable state, parallel state transitions, VLSI, mesh-connected processor arrays
55	Albrecht P. Stroele	Signature analysis and aliasing for sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	built-in self-test techniques, test registers, subcircuits, irreducible characteristic polynomial, limiting value, fault diagnosis, logic testing, built-in self test, integrated circuit testing, sequential circuits, sequential circuits, aliasing, signature analysis, shift registers, test lengths
54	Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna	Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints.	ICCAD	2004	DBLP DOI BibTeX RDF
54	Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi	A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition.	ASP-DAC	1999	DBLP DOI BibTeX RDF
54	Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis	Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
54	Norbert Fröhlich, Rolf Schlagenhaft, Josef Fleischmann	A New Approach for Partitioning VLSI Circuits on Transistor Level.	Workshop on Parallel and Distributed Simulation	1997	DBLP DOI BibTeX RDF
54	Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien	Spectral-based multiway FPGA partitioning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
54	Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien	Spectral-Based Multi-Way FPGA Partitioning.	FPGA	1995	DBLP DOI BibTeX RDF
44	Adam Slowik, Michal Bialko	Partitioning of VLSI Circuits on Subcircuits with Minimal Number of Connections Using Evolutionary Algorithm.	ICAISC	2006	DBLP DOI BibTeX RDF
44	Peter Feldmann, Frank Liu 0001	Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals.	ICCAD	2004	DBLP DOI BibTeX RDF
44	Andrzej Krasniewski	Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
41	Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones	Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).	FCCM	2006	DBLP DOI BibTeX RDF
41	Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai	Bipartitioning and encoding in low-power pipelined circuits.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Low-power design
41	Travis E. Doom, Jennifer L. White, Anthony S. Wojcik, Gregory H. Chisholm	Identifying High-Level Components in Combinational Circuits.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Reengineering, Design Recovery
41	Wen-Ben Jone, Christos A. Papachristou	A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
41	Jos T. J. van Eijndhoven, M. T. van Stiphout, H. W. Buurman	Multirate integration in a direct simulation method.	EURO-DAC	1990	DBLP DOI BibTeX RDF	Multirate Integration, Timing, Circuit Simulation
30	Irith Pomeranz	Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines.	ATS	2022	DBLP DOI BibTeX RDF
30	Yuxiang Huang, Leonid Belostotski	Extraction of Electrical- and Noise-Parameters of Fully-Differential-Amplifier Subcircuits.	IEEE Access	2019	DBLP DOI BibTeX RDF
30	André Lange, Fabio A. Velarde Gonzalez, Insaf Lahbib, Sonja Crocoll	Comparison of modeling approaches for transistor degradation: model card adaptations vs subcircuits.	ESSDERC	2019	DBLP DOI BibTeX RDF
30	Thiago Ferreira de Paiva Leite, Laurent Fesquet, Rodrigo Possamai Bastos	A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
30	Alexis Rodrigo Iga Jadue, Rodrigo Possamai Bastos, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Laurent Fesquet	Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems.	ISCAS	2018	DBLP DOI BibTeX RDF
30	Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf	High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits.	MBMV	2017	DBLP BibTeX RDF
30	Konrad Möller, Martin Kumm, Charles-Frederic Müller, Peter Zipf	Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits.	CoRR	2015	DBLP BibTeX RDF
30	Thomas Schmid 0003, Dorothee Günzel, Martin Bogdan	Automated Quantification of the Relation between Resistor-capacitor Subcircuits from an Impedance Spectrum.	BIOSIGNALS	2014	DBLP DOI BibTeX RDF
30	Ranjan Mehera, Arpan Chakrabarty, Piyali Datta, Rajat Kumar Pal	A 2D Guard Zone Computation Algorithm for Reassignment of Subcircuits to Minimize the Overall Chip Area.	ACSS (2)	2014	DBLP DOI BibTeX RDF
30	Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2009	DBLP DOI BibTeX RDF
30	Andrzej Krasniewski	On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
30	Jennifer L. White, Anthony S. Wojcik, Moon-Jung Chung, Travis E. Doom	Candidate subcircuits for functional module identification in logic circuits.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
30	Seiji Funaba, Akihiro Kitagawa, Toshiro Tsukada, Goichi Yokomizo	A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling.	ASP-DAC	1998	DBLP DOI BibTeX RDF
30	Peter Feldmann, Roland W. Freund	Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm.	DAC	1995	DBLP DOI BibTeX RDF
30	Miles Ohlrich, Carl Ebeling, Eka Ginting, Lisa Sather	SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm.	DAC	1993	DBLP DOI BibTeX RDF
30	Patrick Odent, Luc J. M. Claesen, Hugo De Man	Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator.	DAC	1989	DBLP DOI BibTeX RDF
30	Graziano Frosini, Giovanni B. Gerace	Synthesis of Asynchronous Sequential Circuits with Master-Slave Subcircuits	SWAT	1971	DBLP DOI BibTeX RDF
27	Duo Li, Sheldon X.-D. Tan	Hierarchical Krylov subspace reduced order modeling of large RLC circuits.	ASP-DAC	2008	DBLP DOI BibTeX RDF
27	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Postplacement rewiring by exhaustive search for functional symmetries.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	VLSI, placement, rewiring
27	Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri	Toggle Equivalence Preserving (TEP) Logic Optimization.	DSD	2007	DBLP DOI BibTeX RDF
27	Nikolay Rubanov	A High-Performance Subcircuit Recognition Method Based on the Nonlinear Graph Optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
27	Cheoljoo Jeong, Steven M. Nowick	Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks.	ASYNC	2006	DBLP DOI BibTeX RDF
27	Mukesh Ranjan, Ranga Vemuri	Exact hierarchical symbolic analysis of large analog networks using a general interconnection template.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Eugene Goldberg	On equivalence checking and logic synthesis of circuits with a common specification.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	common specification, scalable equivalence checking, scalable logic synthesis, toggle equivalence
27	B. Ali, A. E. A. Almaini, Tatiana Kalganova	Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits.	Genet. Program. Evolvable Mach.	2004	DBLP DOI BibTeX RDF	genetic algorithm, sequential circuits, evolvable hardware, state assignment
27	Lei Yang 0019, C.-J. Richard Shi	FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
27	Thomas Brandtner, Robert Weigel	Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network.	DATE	2002	DBLP DOI BibTeX RDF
27	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	BIST Design, Test, Low-power Design, Energy Consumption
27	Josef Eckmüller, Martin Groepl, Helmut E. Graeb	Hierarchical Characterization of Analog Integrated CMOS Circuits.	DATE	1998	DBLP DOI BibTeX RDF	hierarchical characterization, circuit class, topology independent, transistor pairs, circuit performances, functional constraints
27	Narayanan Vijaykrishnan, N. Ranganathan	SUBGEN: a genetic approach for subcircuit extraction.	VLSI Design	1996	DBLP DOI BibTeX RDF	SUBGEN model, subcircuit extraction, large circuit graph, genetic algorithms, genetic algorithm, graph theory, computer-aided design, integrated circuit design, circuit CAD, CMOS integrated circuits, CMOS circuit, integrated circuit modelling
27	Toshinobu Ono	Selecting partial scan flip-flops for circuit partitioning.	ICCAD	1994	DBLP DOI BibTeX RDF
27	Valentino Liberali, Victor da Fonte Dias, M. Ciapponi, Franco Maloberti	TOSCA: a simulator for switched-capacitor noise-shaping A/D converters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
27	Gih-Guang Hung, Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh	Improving the performance of parallel relaxation-based circuit simulators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
27	Mehrdad Bidjan-Irani	A Rule-Based Design-for-Testability Rule Checker.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
27	Antony P.-C. Ng, V. Visvanathan	A Framework for Scheduling Multi-Rate Circuit Simulation.	DAC	1989	DBLP DOI BibTeX RDF
27	Wen-Ben Jone, Christos A. Papachristou, M. Pereira	A Scheme for Overlaying Concurrent Testing of VLSI Circuits.	DAC	1989	DBLP DOI BibTeX RDF
27	R. D. Freeman, S. M. Kang, C. G. Lin-Hendel, M. L. Newby	Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning.	DAC	1986	DBLP DOI BibTeX RDF	SPICE
14	Yokesh Kumar, Prosenjit Gupta	External memory layout vs. schematic.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	verification of layouts, Graph, design automation, external memory algorithms, subgraph isomorphism
14	Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma	Leakage reduction, delay compensation using partition-based tunable body-biasing techniques.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	low-power design, process variations, leakage current, Body biasing
14	Bernhard K. Aichernig, Farhad Arbab, Lacramioara Astefanoaei, Frank S. de Boer, Sun Meng, Jan J. M. M. Rutten	Fault-Based Test Case Generation for Component Connectors.	TASE	2009	DBLP DOI BibTeX RDF
14	N. Pete Sedcole, Peter Y. K. Cheung	Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modeling, FPGA, Delay, reconfiguration, process variation, yield
14	Stephen Plaza, Igor L. Markov, Valeria Bertacco	Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
14	Marc Boule, Zeljko Zilic	Automata-based assertion-checker synthesis of PSL properties.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	assertion checkers, emulation, hardware, automata, PSL, Assertion-Based Verification
14	Stephen Plaza, Igor L. Markov, Valeria Bertacco	Optimizing non-monotonic interconnect using functional simulation and logic restructuring.	ISPD	2008	DBLP DOI BibTeX RDF
14	Michal Pavlik, Michal Kuban, Radimir Vrba	Switched Current Flash Analog to Digital Converter.	ICONS	2008	DBLP DOI BibTeX RDF	Switched current, AD Converter, flash converter, Sigma Delta modulator
14	Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown	FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
14	Angan Das, Ranga Vemuri	An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms.	ISVLSI	2007	DBLP DOI BibTeX RDF
14	N. Pete Sedcole, Peter Y. K. Cheung	Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis.	FPGA	2007	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield
14	Natalie Nakhla, Michel S. Nakhla, Ramachandra Achar	Sparse and passive reduction of massively coupled large multiport interconnects.	ICCAD	2007	DBLP DOI BibTeX RDF
14	Jaehyun Kim, Youngsoo Shin	Minimizing leakage power in sequential circuits by using mixed Vt flip-flops.	ICCAD	2007	DBLP DOI BibTeX RDF
14	Lihong Zhang, Ulrich Kleine, Yingtao Jiang	An automated design tool for analog layouts.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
14	Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong	Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Stelios Neophytou, Maria K. Michael, Spyros Tragoudas	Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Aditya K. Prasad, Vivek V. Shende, Igor L. Markov, John P. Hayes, Ketan N. Patel	Data structures and algorithms for simplifying reversible circuits.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Circuit simplification, circuit libraries, optimal subcircuit
14	Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic	Adaptive FPGAs: High-Level Architecture and a Synthesis Method.	FPL	2006	DBLP DOI BibTeX RDF
14	Chun-Jung Chen, Chih-Jen Lee, Jung-Lang Yu, Tai-Ning Yang	A Backward-Traversing Method for Subcircuit Scheduling of Relaxation-Based Circuit Simulation.	ICICIC (3)	2006	DBLP DOI BibTeX RDF
14	Tathagato Rai Dastidar, P. P. Chakrabarti 0001, Partha Ray	A synthesis system for analog circuits based on evolutionary search and topological reuse.	IEEE Trans. Evol. Comput.	2005	DBLP DOI BibTeX RDF
14	Fatih Kocan, Mehmet Hadi Gunes	On the ZBDD-based nonenumerative path delay fault coverage calculation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
14	Nikolay Rubanov	An efficient subcircuit recognition using the nonlinear graph matching.	SBCCI	2005	DBLP DOI BibTeX RDF	subcircuit recognition, graph matching, design verification
14	Eugene Goldberg	Equivalence Checking of Circuits with Parameterized Specifications.	SAT	2005	DBLP DOI BibTeX RDF
14	Nele V. T. D'Halleweyn, James Benson, William Redman-White, Ketan Mistry, M. Swanenberg	MOOSE: a physically based compact DC model of SOI LD MOSFETs for analogue circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
14	Sérgio Vale Aguiar Campos, Orna Grumberg, Karen Yorav, Fady Copty	Test sequence generation and model checking using dynamic transition relations.	Int. J. Softw. Tools Technol. Transf.	2004	DBLP DOI BibTeX RDF	Binary decision diagrams, Symbolic model checking, Test sequence generation
14	Yijun Liu, Stephen B. Furber	Minimizing the Power Consumption of an Asynchronous Multiplier.	PATMOS	2004	DBLP DOI BibTeX RDF
14	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi	Hierarchical extraction and verification of symmetry constraints for analog layout automation.	ASP-DAC	2004	DBLP DOI BibTeX RDF
14	Hisanao Akima, Shigeo Sato, Koji Nakajima	Design of Single Electron Circuitry for a Stochastic Logic Neural Network.	KES	2004	DBLP DOI BibTeX RDF
14	Marc A. Viredaz, Deborah A. Wallach	Power Evaluation of a Handheld Computer.	IEEE Micro	2003	DBLP DOI BibTeX RDF
14	Raimund Ubar	Design Error Diagnosis with Re-Synthesis in Combinational Circuits.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	test generation, diagnosis, fault simulation, design error
14	Raul Baños, Consolación Gil, Maria Dolores Gil Montoya, Julio Ortega Lopera	A Parallel Evolutionary Algorithm for Circuit Partitioning.	PDP	2003	DBLP DOI BibTeX RDF
14	Mehrdad Eslami Dehkordi, Stephen Dean Brown	Recursive circuit clustering for minimum delay and area.	FPGA	2003	DBLP DOI BibTeX RDF
14	Sheldon X.-D. Tan	A General S-Domain Hierarchical Network Reduction Algorithm.	ICCAD	2003	DBLP DOI BibTeX RDF
14	Feng Gao 0017, John P. Hayes	ILP-based optimization of sequential circuits for low power.	ISLPED	2003	DBLP DOI BibTeX RDF	low power, finite-state machine, decomposition, integer linear programming
14	Irith Pomeranz, Sudhakar M. Reddy	Static Test Compaction for Multiple Full-Scan Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
14	Yoshihiro Yamagami, Yoshifumi Nishio, Atsumi Hattori, Akio Ushida	A reduction technique of large scale RCG interconnects in complex frequency domain.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
14	Frederic Green	The Correlation Between Parity and Quadratic Polynomials Mod 3.	CCC	2002	DBLP DOI BibTeX RDF
14	Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai	Energy analysis of bipartition architecture for pipelined circuits.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
14	Irith Pomeranz, Sudhakar M. Reddy	Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
14	Wei-Hsin Chang, Shuenn-Der Tzeng, Chen-Yi Lee	A novel subcircuit extraction algorithm by recursive identification scheme.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
14	Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin	Extreme low-voltage floating-gate CMOS transconductance amplifier.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
14	Tobias Schüle, Albrecht P. Stroele	Scheduling tests for low power built-in self-test.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
14	Mahmoud Al-Nsour, Hoda S. Abdel-Aty-Zohdy	MOS fully analog reinforcement neural network chip.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
14	Tobias Schüle, Albrecht P. Stroele	Test Scheduling for Minimal Energy Consumption under Power Constraints.	VTS	2001	DBLP DOI BibTeX RDF
14	Pasquale Corsonello, Stefania Perri, G. Cororullo	Area-time-power tradeoff in cellular arrays VLSI implementations.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF