Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
69 | Irith Pomeranz, Sudhakar M. Reddy |
On the feasibility of fault simulation using partial circuit descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 108-113, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
partial circuit description, gate-level circuits, subcircuits, logic testing, fault simulation, fault simulation, memory requirements |
57 | Dhruva R. Chakrabarti, Ajai Jain |
An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 237-243, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
hierarchical test generation technique, repetitive subcircuits, hierarchical testing algorithm, bus fault model, high-level subcircuits, high level incompatibility, test generation time, complete fault coverage, computational complexity, fault diagnosis, logic testing, high level synthesis, design for testability, design for testability, ATPG, combinational circuits, combinational circuits, logic CAD, automatic test software, signal flow graphs, state transition graph |
55 | Itsuo Takanami, Tadayoshi Horita |
Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 218-226, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
self-reconstruction, digital neural circuits, Hopfield-type neural algorith, 1 1/2 -track switches, compensation paths, subcircuits, stable state, parallel state transitions, VLSI, mesh-connected processor arrays |
55 | Albrecht P. Stroele |
Signature analysis and aliasing for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 118-124, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
built-in self-test techniques, test registers, subcircuits, irreducible characteristic polynomial, limiting value, fault diagnosis, logic testing, built-in self test, integrated circuit testing, sequential circuits, sequential circuits, aliasing, signature analysis, shift registers, test lengths |
54 | Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna |
Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 58-65, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi |
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 291-294, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
54 | Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis |
Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3), pp. 309-315, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
54 | Norbert Fröhlich, Rolf Schlagenhaft, Josef Fleischmann |
A New Approach for Partitioning VLSI Circuits on Transistor Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Parallel and Distributed Simulation ![In: Proceedings of the Eleventh Workshop on Parallel and Distributed Simulation, PADS '97, Lockenhaus, Austria, June 10-13, 1997, pp. 64-67, 1997, IEEE Computer Society, 0-8186-7965-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
54 | Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien |
Spectral-based multiway FPGA partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5), pp. 554-560, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
54 | Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien |
Spectral-Based Multi-Way FPGA Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 133-139, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
44 | Adam Slowik, Michal Bialko |
Partitioning of VLSI Circuits on Subcircuits with Minimal Number of Connections Using Evolutionary Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAISC ![In: Artificial Intelligence and Soft Computing - ICAISC 2006, 8th International Conference, Zakopane, Poland, June 25-29, 2006, Proceedings, pp. 470-478, 2006, Springer, 3-540-35748-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
44 | Peter Feldmann, Frank Liu 0001 |
Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 88-92, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Andrzej Krasniewski |
Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 616-626, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones |
Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 299-300, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai |
Bipartitioning and encoding in low-power pipelined circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(1), pp. 24-32, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Low-power design |
41 | Travis E. Doom, Jennifer L. White, Anthony S. Wojcik, Gregory H. Chisholm |
Identifying High-Level Components in Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 313-318, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Reengineering, Design Recovery |
41 | Wen-Ben Jone, Christos A. Papachristou |
A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3), pp. 374-384, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
41 | Jos T. J. van Eijndhoven, M. T. van Stiphout, H. W. Buurman |
Multirate integration in a direct simulation method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 306-311, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
Multirate Integration, Timing, Circuit Simulation |
30 | Irith Pomeranz |
Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: IEEE 31st Asian Test Symposium, ATS 2022, Taichung City, Taiwan, November 21-24, 2022, pp. 114-119, 2022, IEEE, 978-1-6654-7227-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
30 | Yuxiang Huang, Leonid Belostotski |
Extraction of Electrical- and Noise-Parameters of Fully-Differential-Amplifier Subcircuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 42123-42132, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
30 | André Lange, Fabio A. Velarde Gonzalez, Insaf Lahbib, Sonja Crocoll |
Comparison of modeling approaches for transistor degradation: model card adaptations vs subcircuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 49th European Solid-State Device Research Conference, ESSDERC 2019, Cracow, Poland, September 23-26, 2019, pp. 186-189, 2019, IEEE, 978-1-7281-1539-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
30 | Thiago Ferreira de Paiva Leite, Laurent Fesquet, Rodrigo Possamai Bastos |
A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 88-90, pp. 122-127, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Alexis Rodrigo Iga Jadue, Rodrigo Possamai Bastos, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Laurent Fesquet |
Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Patrick Sittel, Martin Kumm, Konrad Möller, Martin Hardieck, Peter Zipf |
High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MBMV ![In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017., pp. 103-114, 2017, Shaker Verlag, 978-3-8440-4996-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
30 | Konrad Möller, Martin Kumm, Charles-Frederic Müller, Peter Zipf |
Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1508.06811, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
30 | Thomas Schmid 0003, Dorothee Günzel, Martin Bogdan |
Automated Quantification of the Relation between Resistor-capacitor Subcircuits from an Impedance Spectrum. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIOSIGNALS ![In: BIOSIGNALS 2014 - Proceedings of the International Conference on Bio-inspired Systems and Signal Processing, ESEO, Angers, Loire Valley, France, 3-6 March, 2014, pp. 141-148, 2014, SciTePress, 978-989-758-011-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Ranjan Mehera, Arpan Chakrabarty, Piyali Datta, Rajat Kumar Pal |
A 2D Guard Zone Computation Algorithm for Reassignment of Subcircuits to Minimize the Overall Chip Area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSS (2) ![In: Applied Computation and Security Systems - ACSS 2014 - 1st International Doctoral Symposium on Applied Computation and Security Systems (ACSS), April, 18-20, 2014, Kolkata, India, Proceedings, Volume Two, pp. 183-209, 2014, Springer, 978-81-322-1987-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
30 | Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa |
An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12), pp. 3136-3142, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Andrzej Krasniewski |
On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 596-606, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Jennifer L. White, Anthony S. Wojcik, Moon-Jung Chung, Travis E. Doom |
Candidate subcircuits for functional module identification in logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000, pp. 34-38, 2000, ACM, 1-58113-251-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Seiji Funaba, Akihiro Kitagawa, Toshiro Tsukada, Goichi Yokomizo |
A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '98, Asia and South Pacific Design Automation Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13, 1998, pp. 489-494, 1998, IEEE, 0-7803-4425-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Peter Feldmann, Roland W. Freund |
Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995., pp. 474-479, 1995, ACM Press, 0-89791-725-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
30 | Miles Ohlrich, Carl Ebeling, Eka Ginting, Lisa Sather |
SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 30th Design Automation Conference. Dallas, Texas, USA, June 14-18, 1993., pp. 31-37, 1993, ACM Press, 0-89791-577-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
30 | Patrick Odent, Luc J. M. Claesen, Hugo De Man |
Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 25-30, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
30 | Graziano Frosini, Giovanni B. Gerace |
Synthesis of Asynchronous Sequential Circuits with Master-Slave Subcircuits ![Search on Bibsonomy](Pics/bibsonomy.png) |
SWAT ![In: 12th Annual Symposium on Switching and Automata Theory, East Lansing, Michigan, USA, October 13-15, 1971, pp. 60-78, 1971, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1971 |
DBLP DOI BibTeX RDF |
|
27 | Duo Li, Sheldon X.-D. Tan |
Hierarchical Krylov subspace reduced order modeling of large RLC circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 170-175, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Kai-Hui Chang, Igor L. Markov, Valeria Bertacco |
Postplacement rewiring by exhaustive search for functional symmetries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(3), pp. 32:1-32:21, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
VLSI, placement, rewiring |
27 | Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri |
Toggle Equivalence Preserving (TEP) Logic Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 271-279, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Nikolay Rubanov |
A High-Performance Subcircuit Recognition Method Based on the Nonlinear Graph Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2353-2363, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Cheoljoo Jeong, Steven M. Nowick |
Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France, pp. 128-137, 2006, IEEE Computer Society, 0-7695-2498-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Mukesh Ranjan, Ranga Vemuri |
Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Eugene Goldberg |
On equivalence checking and logic synthesis of circuits with a common specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 102-107, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
common specification, scalable equivalence checking, scalable logic synthesis, toggle equivalence |
27 | B. Ali, A. E. A. Almaini, Tatiana Kalganova |
Evolutionary Algorithms and Theirs Use in the Design of Sequential Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Genet. Program. Evolvable Mach. ![In: Genet. Program. Evolvable Mach. 5(1), pp. 11-29, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
genetic algorithm, sequential circuits, evolvable hardware, state assignment |
27 | Lei Yang 0019, C.-J. Richard Shi |
FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 741-747, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Thomas Brandtner, Robert Weigel |
Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1028-1032, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch |
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 89-94, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
BIST Design, Test, Low-power Design, Energy Consumption |
27 | Josef Eckmüller, Martin Groepl, Helmut E. Graeb |
Hierarchical Characterization of Analog Integrated CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 636-643, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hierarchical characterization, circuit class, topology independent, transistor pairs, circuit performances, functional constraints |
27 | Narayanan Vijaykrishnan, N. Ranganathan |
SUBGEN: a genetic approach for subcircuit extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 343-345, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
SUBGEN model, subcircuit extraction, large circuit graph, genetic algorithms, genetic algorithm, graph theory, computer-aided design, integrated circuit design, circuit CAD, CMOS integrated circuits, CMOS circuit, integrated circuit modelling |
27 | Toshinobu Ono |
Selecting partial scan flip-flops for circuit partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 646-650, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
27 | Valentino Liberali, Victor da Fonte Dias, M. Ciapponi, Franco Maloberti |
TOSCA: a simulator for switched-capacitor noise-shaping A/D converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9), pp. 1376-1386, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
27 | Gih-Guang Hung, Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh |
Improving the performance of parallel relaxation-based circuit simulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(11), pp. 1762-1774, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
27 | Mehrdad Bidjan-Irani |
A Rule-Based Design-for-Testability Rule Checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 8(1), pp. 50-57, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
27 | Antony P.-C. Ng, V. Visvanathan |
A Framework for Scheduling Multi-Rate Circuit Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 19-24, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
27 | Wen-Ben Jone, Christos A. Papachristou, M. Pereira |
A Scheme for Overlaying Concurrent Testing of VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 531-536, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
27 | R. D. Freeman, S. M. Kang, C. G. Lin-Hendel, M. L. Newby |
Automated extraction of SPICE circuit models from symbolic gate matrix layout with pruning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 418-424, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
SPICE |
14 | Yokesh Kumar, Prosenjit Gupta |
External memory layout vs. schematic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(2), pp. 30:1-30:20, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
verification of layouts, Graph, design automation, external memory algorithms, subgraph isomorphism |
14 | Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma |
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(4), pp. 53:1-53:22, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low-power design, process variations, leakage current, Body biasing |
14 | Bernhard K. Aichernig, Farhad Arbab, Lacramioara Astefanoaei, Frank S. de Boer, Sun Meng, Jan J. M. M. Rutten |
Fault-Based Test Case Generation for Component Connectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TASE ![In: TASE 2009, Third IEEE International Symposium on Theoretical Aspects of Software Engineering, 29-31 July 2009, Tianjin, China, pp. 147-154, 2009, IEEE Computer Society, 978-0-7695-3757-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | N. Pete Sedcole, Peter Y. K. Cheung |
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(2), pp. 10:1-10:28, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
statistical theory, within-die variability, modeling, FPGA, Delay, reconfiguration, process variation, yield |
14 | Stephen Plaza, Igor L. Markov, Valeria Bertacco |
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12), pp. 2107-2119, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Marc Boule, Zeljko Zilic |
Automata-based assertion-checker synthesis of PSL properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(1), pp. 4:1-4:21, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
assertion checkers, emulation, hardware, automata, PSL, Assertion-Based Verification |
14 | Stephen Plaza, Igor L. Markov, Valeria Bertacco |
Optimizing non-monotonic interconnect using functional simulation and logic restructuring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 95-102, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Michal Pavlik, Michal Kuban, Radimir Vrba |
Switched Current Flash Analog to Digital Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONS ![In: The Third International Conference on Systems, ICONS 2008, April 13-18, 2008, Cancun, Mexico, pp. 341-344, 2008, IEEE Computer Society, 978-0-7695-3105-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Switched current, AD Converter, flash converter, Sigma Delta modulator |
14 | Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown |
FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1196-1210, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Angan Das, Ranga Vemuri |
An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 145-152, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | N. Pete Sedcole, Peter Y. K. Cheung |
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 178-187, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield |
14 | Natalie Nakhla, Michel S. Nakhla, Ramachandra Achar |
Sparse and passive reduction of massively coupled large multiport interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 622-626, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Jaehyun Kim, Youngsoo Shin |
Minimizing leakage power in sequential circuits by using mixed Vt flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 797-802, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
14 | Lihong Zhang, Ulrich Kleine, Yingtao Jiang |
An automated design tool for analog layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 881-894, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong |
Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2402-2412, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Stelios Neophytou, Maria K. Michael, Spyros Tragoudas |
Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 3026-3035, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Aditya K. Prasad, Vivek V. Shende, Igor L. Markov, John P. Hayes, Ketan N. Patel |
Data structures and algorithms for simplifying reversible circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 2(4), pp. 277-293, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Circuit simplification, circuit libraries, optimal subcircuit |
14 | Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic |
Adaptive FPGAs: High-Level Architecture and a Synthesis Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-8, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Chun-Jung Chen, Chih-Jen Lee, Jung-Lang Yu, Tai-Ning Yang |
A Backward-Traversing Method for Subcircuit Scheduling of Relaxation-Based Circuit Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICIC (3) ![In: First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August - 1 September 2006, Beijing, China, pp. 157-160, 2006, IEEE Computer Society, 0-7695-2616-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Tathagato Rai Dastidar, P. P. Chakrabarti 0001, Partha Ray |
A synthesis system for analog circuits based on evolutionary search and topological reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Evol. Comput. ![In: IEEE Trans. Evol. Comput. 9(2), pp. 211-224, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Fatih Kocan, Mehmet Hadi Gunes |
On the ZBDD-based nonenumerative path delay fault coverage calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7), pp. 1137-1143, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Nikolay Rubanov |
An efficient subcircuit recognition using the nonlinear graph matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 44-49, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
subcircuit recognition, graph matching, design verification |
14 | Eugene Goldberg |
Equivalence Checking of Circuits with Parameterized Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAT ![In: Theory and Applications of Satisfiability Testing, 8th International Conference, SAT 2005, St. Andrews, UK, June 19-23, 2005, Proceedings, pp. 107-121, 2005, Springer, 3-540-26276-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Nele V. T. D'Halleweyn, James Benson, William Redman-White, Ketan Mistry, M. Swanenberg |
MOOSE: a physically based compact DC model of SOI LD MOSFETs for analogue circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10), pp. 1399-1410, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Sérgio Vale Aguiar Campos, Orna Grumberg, Karen Yorav, Fady Copty |
Test sequence generation and model checking using dynamic transition relations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 6(2), pp. 174-182, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Binary decision diagrams, Symbolic model checking, Test sequence generation |
14 | Yijun Liu, Stephen B. Furber |
Minimizing the Power Consumption of an Asynchronous Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 289-300, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi |
Hierarchical extraction and verification of symmetry constraints for analog layout automation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 400-405, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Hisanao Akima, Shigeo Sato, Koji Nakajima |
Design of Single Electron Circuitry for a Stochastic Logic Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES ![In: Knowledge-Based Intelligent Information and Engineering Systems, 8th International Conference, KES 2004, Wellington, New Zealand, September 20-25, 2004. Proceedings. Part I, pp. 1010-1016, 2004, Springer, 3-540-23318-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Marc A. Viredaz, Deborah A. Wallach |
Power Evaluation of a Handheld Computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 23(1), pp. 66-74, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Raimund Ubar |
Design Error Diagnosis with Re-Synthesis in Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(1), pp. 73-82, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
test generation, diagnosis, fault simulation, design error |
14 | Raul Baños, Consolación Gil, Maria Dolores Gil Montoya, Julio Ortega Lopera |
A Parallel Evolutionary Algorithm for Circuit Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 11th Euromicro Workshop on Parallel, Distributed and Network-Based Processing (PDP 2003), 5-7 February 2003, Genova, Italy, pp. 365-371, 2003, IEEE Computer Society, 0-7695-1875-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Mehrdad Eslami Dehkordi, Stephen Dean Brown |
Recursive circuit clustering for minimum delay and area. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 242, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Sheldon X.-D. Tan |
A General S-Domain Hierarchical Network Reduction Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 650-657, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Feng Gao 0017, John P. Hayes |
ILP-based optimization of sequential circuits for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 140-145, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low power, finite-state machine, decomposition, integer linear programming |
14 | Irith Pomeranz, Sudhakar M. Reddy |
Static Test Compaction for Multiple Full-Scan Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 393-396, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Yoshihiro Yamagami, Yoshifumi Nishio, Atsumi Hattori, Akio Ushida |
A reduction technique of large scale RCG interconnects in complex frequency domain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 490-493, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Frederic Green |
The Correlation Between Parity and Quadratic Polynomials Mod 3. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: Proceedings of the 17th Annual IEEE Conference on Computational Complexity, Montréal, Québec, Canada, May 21-24, 2002, pp. 65-72, 2002, IEEE Computer Society, 0-7695-1468-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai |
Energy analysis of bipartition architecture for pipelined circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (2) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 7-11, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Irith Pomeranz, Sudhakar M. Reddy |
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(5), pp. 679-689, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Wei-Hsin Chang, Shuenn-Der Tzeng, Chen-Yi Lee |
A novel subcircuit extraction algorithm by recursive identification scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 491-494, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin |
Extreme low-voltage floating-gate CMOS transconductance amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 37-40, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Tobias Schüle, Albrecht P. Stroele |
Scheduling tests for low power built-in self-test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 247-250, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Mahmoud Al-Nsour, Hoda S. Abdel-Aty-Zohdy |
MOS fully analog reinforcement neural network chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 237-240, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Tobias Schüle, Albrecht P. Stroele |
Test Scheduling for Minimal Energy Consumption under Power Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 312-318, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Pasquale Corsonello, Stefania Perri, G. Cororullo |
Area-time-power tradeoff in cellular arrays VLSI implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(5), pp. 614-624, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|