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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6282 occurrences of 3514 keywords
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Results
Found 16023 publication records. Showing 16021 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
61 | Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu 0001 |
Test structures for delay variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 109, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
59 | Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang 0001, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De |
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 26-29, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Vt mismatch, Vt variation, random dopant variation, threshold voltage variation, transistor mismatch, transistor threshold voltage mismatch, process variation, CMOS, integrated circuits, variation, transistors, threshold voltage, mismatch, body bias, Vt |
55 | Jos J. Mellema, Wouter H. Mallee, Thierry G. Guitton, C. Niek van Dijk, David Ring, Job N. Doornberg, Science of Variation Group, Traumaplatform Study Collaborative |
Online Studies on Variation in Orthopedic Surgery: Computed Tomography in MPEG4 Versus DICOM Format. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Digit. Imaging ![In: J. Digit. Imaging 30(5), pp. 547-554, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
50 | Lerong Cheng, Puneet Gupta 0001, Costas J. Spanos, Kun Qian 0014, Lei He 0001 |
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 104-109, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
leakage analysis, process variaion, timing, SSTA |
49 | Georgios Karakonstantis, Kaushik Roy 0001 |
Low-Power and Variation-Tolerant Application-Specific System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 249-292, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
49 | Swaroop Ghosh |
Effect of Variations and Variation Tolerance in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 83-108, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
49 | Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon |
Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 381-432, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
49 | Nikil Mehta, André DeHon |
Variation and Aging Tolerance in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 365-380, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
49 | Hamid Mahmoodi |
Low-Power and Variation-Tolerant Memory Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 151-183, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
49 | Meeta Sharma Gupta, Pradip Bose |
Variation-Tolerant Microprocessor Architecture at Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 211-247, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
47 | Tahir Nawaz Minhas, Markus Fiedler, Patrik Arlos |
Quantification of packet delay variation through the coefficient of throughput variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWCMC ![In: Proceedings of the 6th International Wireless Communications and Mobile Computing Conference, IWCMC 2010, Caen, France, June 28 - July 2, 2010, pp. 336-340, 2010, ACM, 978-1-4503-0062-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
coefficient of throughput variation, network measurement traffice shapping, packet delay variation, traffic shaper, performance analysis, throughput |
47 | J. Brian Burns, Richard S. Weiss, Edward M. Riseman |
View Variation of Point-Set and Line-Segment Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 15(1), pp. 51-68, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
feature variation, view variation, 3D point sets, weak perspective approximation, 2D line segment features, feature extraction, image recognition, image recognition |
47 | Peng Xu, Timothy Kennell Jr., Min Gao, Human Genome Structural Variation Consortium, Robert P. Kimberly, Zechen Chong |
MRLR: unraveling high-resolution meiotic recombination by linked reads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Bioinform. ![In: Bioinform. 36(1), pp. 10-16, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
47 | Takeo Kanade, Masatoshi Okutomi |
A Stereo Matching Algorithm with an Adaptive Window: Theory and Experiment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 16(9), pp. 920-932, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
stereo matching algorithm, reliable matching, projective distortion, maximum correlation, sum of squared differences, disparity distribution, disparity variation, iterative stereo matching algorithm, uncertainty, image sequences, statistical analysis, iterative methods, statistical model, stereo image processing, correlation methods, real images, synthetic images, disparity map, adaptive window, window size, disparity estimate, intensity variation |
47 | Louis Scheffer |
Explicit computation of performance as a function of process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Timing Issues in the Specification and Synthesis of Digital Systems ![In: Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, USA, December 2-3, 2002, pp. 1-8, 2002, ACM, 1-58113-526-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
static timing, process variation, yield, statistical timing |
43 | Glenn Healey, Raghava Kondepudy |
Radiometric CCD camera calibration and noise estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 16(3), pp. 267-276, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
semiconductor device noise, radiometric CCD camera calibration, primary cue, material reflectance, digitized pixel values, sensor noise, scene variation, camera characterization, fixed pattern nonuniformity, spatial variation, dark current, computer vision, edge detection, edge detection, reflectivity, parameter estimation, calibration, shape from shading, video cameras, video cameras, scene description, visual processes, CCD image sensors, noise estimation, semiconductor device models, radiometry |
43 | Borislava I. Simidchieva, Leon J. Osterweil |
Categorizing and modeling variation in families of systems: a position paper. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECSA Companion Volume ![In: Software Architecture, 4th European Conference, ECSA 2010, Copenhagen, Denmark, August 23-26, 2010. Companion Volume, pp. 316-323, 2010, ACM, 978-1-4503-0179-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
software families, software product lines, system architectures, variability, variation |
43 | Bo Zhao 0007, Yu Du, Youtao Zhang, Jun Yang 0002 |
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 222-231, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
3D die stacking, NUCA, process variation, DRAM |
42 | Liang-Jie Zhang, Ali Arsanjani, Abdul Allam, Dingding Lu, Yi-Min Chee |
Variation-Oriented Analysis for SOA Solution Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE SCC ![In: 2007 IEEE International Conference on Services Computing (SCC 2007), 9-13 July 2007, Salt Lake City, Utah, USA, pp. 560-568, 2007, IEEE Computer Society, 0-7695-2925-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki |
Approach for physical design in sub-100 nm era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5934-5937, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Sachin S. Sapatnekar |
Statistical Design of Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 109-149, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Shreyas Sen, Vishwanath Natarajan, Abhijit Chatterjee |
Low-Power Adaptive Mixed Signal/RF Circuits and Systems and Self-Healing Solutions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 293-333, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Wei Zhang 0012, James Williamson, Li Shang |
Power Dissipation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 41-80, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Aditya Bansal, Rahul M. Rao |
Variations: Sources and Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 3-39, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Nikil Mehta, André DeHon |
Low-Power Techniques for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 337-363, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
41 | Bipul C. Paul, Arijit Raychowdhury |
Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Low-Power Variation-Tolerant Design in Nanometer Silicon ![In: Low-Power Variation-Tolerant Design in Nanometer Silicon, pp. 185-207, 2011, Springer, 978-1-4419-7417-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
39 | Maziar Goudarzi, Tohru Ishihara, Hamid Noori |
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 224-239, 2008, Springer, 978-3-540-77559-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
process variation, cache memory, Leakage power, power reduction |
39 | Rich Hilliard |
On representing variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECSA Companion Volume ![In: Software Architecture, 4th European Conference, ECSA 2010, Copenhagen, Denmark, August 23-26, 2010. Companion Volume, pp. 312-315, 2010, ACM, 978-1-4503-0179-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
features, variation, architecture description, concerns |
39 | Lin Huang 0002, Qiang Xu 0001 |
Performance yield-driven task allocation and scheduling for MPSoCs under process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 326-331, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance yield, process variation, task scheduling |
39 | Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Hanpei Koike, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa |
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 3:1-3:31, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, configuration, within-die variation, timing yield |
39 | Jae-Seok Yang, Andrew R. Neureuther |
Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 352-356, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
worst corner, noise, crosstalk, variation, signal integrity |
39 | Yun Ye, Frank Liu 0001, Sani R. Nassif, Yu Cao 0001 |
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 900-905, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
atomistic simulations, line-edge roughness, non-rectangular gate, random dopant fluctuations, threshold variation, predictive modeling, SPICE simulation |
39 | Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike |
Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 169-177, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, configuration, within-die variation, timing yield |
39 | Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu |
Re-synthesis for delay variation tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 814-819, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
tolerance, delay variation |
39 | Hyung-Soo Lee, Daijin Kim 0001 |
Tensor-Based AAM with Continuous Variation Estimation: Application to Variation-Robust Face Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 31(6), pp. 1102-1116, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
39 | Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong |
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5), pp. 845-857, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
39 | Nanjangud C. Narendra, Karthikeyan Ponnalagu |
Variation-Oriented Requirements Analysis (VORA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE SCW ![In: 2007 IEEE International Conference on Services Computing - Workshops (SCW 2007), 9-13 July 2007, Salt Lake City, Utah, USA, pp. 159-166, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001 |
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7), pp. 1253-1263, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar |
Circuit techniques for dynamic variation tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 4-7, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic variations, error-detection sequential, replica paths, resilient circuits, variation sensors, variation-tolerant circuits, error detection, error correction, error recovery, parameter variations, timing errors |
35 | Soroush Abbaspour, Hanif Fatemi, Massoud Pedram |
VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 426-430, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay |
35 | Kiyoo Itoh 0001 |
Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 273-274, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet |
35 | Jason Cong, Albert Liu, Bin Liu 0006 |
A variation-tolerant scheduler for better than worst-case behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 221-228, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
scheduling, variation, behavioral synthesis |
35 | Aarti Choudhary, Sandip Kundu |
A process variation tolerant self-compensating FinFET based sense amplifier design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 161-164, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
sense amplifier, robustness, process -variation, yield, sram, finfet |
35 | Andreas Lanitis, Christopher J. Taylor 0001 |
Towards Automatic Face Identification Robust to Ageing Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FG ![In: 4th IEEE International Conference on Automatic Face and Gesture Recognition (FG 2000), 26-30 March 2000, Grenoble, France, pp. 391-397, 2000, IEEE Computer Society, 0-7695-0580-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Ageing Variation, Face Recognition |
35 | Byungwoo Choi, D. M. H. Walker |
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 49-54, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
interconnect coupling, delay fault model, process variation, timing analysis, delay fault test |
35 | Jae-Seok Yang, David Z. Pan |
Overlay aware interconnect and timing variation modeling for double patterning technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 488-493, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Martin Hansson, Atila Alvandpour |
Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3744-3747, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Marvin Tom, David Leong, Guy G. Lemieux |
Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 680-687, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
channel width constraints, clustering, field-programmable gate arrays (FPGA), packing |
35 | Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera |
Statistical modeling of gate-delay variation with consideration of intra-gate variability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 513-516, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Jay Ramanathan |
Fractal architecture for the adaptive complex enterprise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 48(5), pp. 51-57, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Wangyang Zhang, Xin Li 0001, Rob A. Rutenbar |
Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 262-267, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
variation characterization, process variation, integrated circuit |
31 | Kanak Agarwal |
On-die sensors for measuring process and environmental variations in integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 147-150, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
environmental variation, test structure, monitors, sensors, process variation, characterization |
31 | Love Singhal, Sejong Oh, Eli Bozorgzadeh |
Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 249-254, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
configuration selection, delay budgeting, process variation, task allocation, within-die variation, timing yield |
31 | Maria Teresa Andrade, Artur Pimenta Alves |
Experiments with Dynamic Multiplexing and UPC Renegotiation for Video over ATM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NETWORKING ![In: NETWORKING 2000, Broadband Communications, High Performance Networking, and Performance of Communication Networks, IFIP-TC6 / European Commission International Conference, Paris, France, May 14-19, 2000, Proceedings, pp. 895-907, 2000, Springer, 3-540-67506-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
renegotiation Abbreviations: AAL, ATM Adaptation Layer, ACTS, Advanced Communications, Technologies & Services, CDV, Cell Delay Variation, CDVT, Cell Delay Variation Tolerance, CTD, Cell Transfer Delay, EFCI, Explicit Forward Congestion Indication, GOP, Group Of Pictures, MBS, Maximum Burst Size, Motion Picture Expert Group, Network Interface Card, Peak Cell Rate, MCR, Minimum Cell Rate, Resource and Management, Sustainable Cell Rate, UNI, User Network Interface, Usage Parameter Control, Quality of Service, QoS, Quality of Service, ATM, ATM, Asynchronous Transfer Mode, VoD, Video on Demand, CAC, MPEG, CBR, statistical multiplexing, VBR, Variable Bit Rate, Connection Admission Control, UPC, UPC, ABR, Virtual Circuit, RM, Available Bit Rate, SCR, PCR, VC, NIC, Constant Bit Rate |
31 | Gregory Lucas, Chen Dong 0003, Deming Chen |
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 177-180, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis |
31 | Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph |
Process variation characterization of chip-level multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 694-697, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
software, process variation, characterization |
31 | Seyed-Abdollah Aftabjahani, Linda S. Milor |
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 148-151, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Variation-Aware Timing Models, Standard Cells, Statistical Timing Analysis |
31 | Pi-Rong Sheu, Shan-Tai Chen |
On the Hardness of Approximating the Multicast Delay Variation Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(11), pp. 1575-1577, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
inter-destination delay variation, NP-complete, NP-hard, multicast routing, Inapproximability |
31 | Yan Lin 0001, Lei He 0001 |
Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 80-88, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA, uncertainty, process variation, stochastic, physical synthesis |
31 | Louis Scheffer |
An overview of on-chip interconnect variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 27-28, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
causes of variability, on-chip variation, design rules |
31 | Charles C. Chiang, Jamil Kawa |
Three DFM Challenges: Random Defects, Thickness Variation, and Printability Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1099-1102, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
31 | Lei He 0001, Andrew B. Kahng, King Ho Tam, Jinjun Xiong |
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 78-85, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
yield, buffering, design for manufacturing, wire sizing, chemical mechanical polishing (CMP) |
31 | Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester |
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 365-368, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ACLV, layout, manufacturability, compensation, variation, focus |
31 | Andreas Lanitis, Christopher J. Taylor 0001, Timothy F. Cootes |
Toward Automatic Simulation of Aging Effects on Face Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 24(4), pp. 442-455, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
aging variation, statistical face models, face recognition |
31 | Kanakagiri Raghavendra, Madhu Mutyam |
Process Variation Aware Issue Queue Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1438-1443, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari 0002, Josep Torrellas |
EVAL: Utilizing processors with variation-induced timing errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 423-434, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Yanming Jia, Yici Cai, Xianlong Hong |
Full-chip routing system for reducing Cu CMP & ECP variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008, pp. 10-15, 2008, ACM, 978-1-60558-231-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
electroplating, routing, chemical mechanical polishing |
31 | Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan |
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 398-403, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Zhuo Li 0001, Xiang Lu, Weiping Shi |
Process variation dimension reduction based on SVD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 672-675, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
31 | Takao Yamashita |
Dynamic Replica Control Based on Fairly Assigned Variation of Data with Weak Consistency for Loosely Coupled Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: Proceedings of the 22nd International Conference on Distributed Computing Systems (ICDCS'02), Vienna, Austria, July 2-5, 2002, pp. 280-289, 2002, IEEE Computer Society, 0-7695-1585-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Jussi Karlgren, Troy Straszheim |
Visualizing Stylistic Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (6) ![In: 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 7-10 January 1997, Maui, Hawaii, USA, pp. 78-, 1997, IEEE Computer Society, 0-8186-7734-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Yiyu Shi 0001, Jinjun Xiong, Chunchen Liu, Lei He 0001 |
Efficient decoupling capacitance budgeting considering operation and process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 803-810, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Wenjian Yu, Chao Hu, Wangyang Zhang |
Variational capacitance extraction of on-chip interconnects based on continuous surface model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 758-763, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
geometric variation modeling, hermite polynomial chaos method, quadratic variation model, variational capacitance extraction, spatial correlation |
27 | Kiyoo Itoh 0001, Masanao Yamaoka, Takayuki Kawahara |
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 529-533, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate |
27 | Edson J. R. Justino, Abdenaim El Yacoubi, Flávio Bortolozzi, Robert Sabourin |
An Off-Line Signature Verification System using Hidden Markov Model and Cross-Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIBGRAPI ![In: 13th Brazilian Symposium on Computer Graphics and Image Processing (SIBGRAPI 2000), 17-20 October 2000, Gramado (RS), Brazil, pp. 105-112, 2000, IEEE Computer Society, 0-7695-0878-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
off-line signature verification system, pre-processing process, segmentation process, feature extraction process, random falsifications, false acceptance concept, false rejection concept, intrapersonal variation, interpersonal variation, automatic decision threshold derivation, hidden Markov model, handwriting recognition, cross-validation, learning process |
27 | Wei Zhang 0032, Ki Chul Chun, Chris H. Kim |
Variation aware performance analysis of gain cell embedded DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 19-24, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
bitline delay, gain cell, process variation, monte carlo simulation, embedded DRAM |
27 | Mirko Lucchese, N. Alberto Borghese |
Denoising of Digital Radiographic Images with Automatic Regularization Based on Total Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIAP ![In: Image Analysis and Processing - ICIAP 2009, 15th International Conference Vietri sul Mare, Italy, September 8-11, 2009, Proceedings, pp. 711-720, 2009, Springer, 978-3-642-04145-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
total variation filtering, gradient descent minimization, regularization, Bayesian filtering, Digital radiography |
27 | Amlan Ghosh, Rahul M. Rao, Richard B. Brown |
A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 45-50, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fine-grain body-biasing, process variation compensation, slewrate |
27 | Alex Sawatzky, Christoph Brune, Jahn Müller, Martin Burger 0001 |
Total Variation Processing of Images with Poisson Statistics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAIP ![In: Computer Analysis of Images and Patterns, 13th International Conference, CAIP 2009, Münster, Germany, September 2-4, 2009. Proceedings, pp. 533-540, 2009, Springer, 978-3-642-03766-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Poisson noise, Regularization techniques, Segmentation, Denoising, Positron emission tomography, Total variation |
27 | Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik |
A parametric approach for handling local variation effects in timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 126-129, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on chip variation (OCV), timing, parametric analysis |
27 | David Wolpert 0001, Paul Ampadu |
Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - Third International ICST Conference, NanoNet 2008, Boston, MA, USA, September 14-16, 2008, Revised Selected Papers, pp. 14-18, 2008, Springer, 978-3-642-02426-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Reverse temperature dependence, high-k dielectric, variation-tolerant, metal gate |
27 | Michael Leuchtenburg, Pritish Narayanan, Teng Wang, Csaba Andras Moritz |
Impact of Process Variation in Fault-Resilient Streaming Nanoprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - Third International ICST Conference, NanoNet 2008, Boston, MA, USA, September 14-16, 2008, Revised Selected Papers, pp. 26-27, 2008, Springer, 978-3-642-02426-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
nanoscale processor, process variation, defect tolerance |
27 | A. K. M. Khaled Ahsan Talukder, Michael Kirley, Rajkumar Buyya |
A pareto following variation operator for fast-converging multiobjective evolutionary algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2008, Proceedings, Atlanta, GA, USA, July 12-16, 2008, pp. 721-728, 2008, ACM, 978-1-60558-130-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
variation operator, evolutionary multiobjective optimization, function evaluation, dynamic system identification |
27 | Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos |
A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 47-52, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed |
27 | Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas |
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 43-46, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bus coding, delay, process variation |
27 | Bin Zhang 0011, Michael Orshansky |
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 774-779, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
temperature variation, NBTI |
27 | Kimmo Kettunen 0001, Eija Airio, Kalervo Järvelin |
Restricted inflectional form generation in management of morphological keyword variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Retr. ![In: Inf. Retr. 10(4-5), pp. 415-444, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Best-match IR, Inflected indexes, Frequent case form generation for keywords, Generative methods in management of keyword variation |
27 | Shu Xiao 0001, Edmund Ming-Kit Lai |
VLIW instruction scheduling for minimal power variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 4(3), pp. 18, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power variation reduction, Instruction scheduling, VLIW processors |
27 | Heiko Ludwig, Kamal Bhattacharya, Thomas Setzer |
A Layered Service Process Model for Managing Variation and Change in Service Provider Operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISE ![In: Web Information Systems Engineering - WISE 2007, 8th International Conference on Web Information Systems Engineering, Nancy, France, December 3-7, 2007, Proceedings, pp. 484-492, 2007, Springer, 978-3-540-76992-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Variation Management, Service Transition, Service Workflow Management, Service Process Evolution, Change Management |
27 | Lv-an Tang, Bin Cui 0001, Hongyan Li 0002, Gaoshan Miao, Dongqing Yang, Xinbiao Zhou |
Effective variation management for pseudo periodical streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the ACM SIGMOD International Conference on Management of Data, Beijing, China, June 12-14, 2007, pp. 257-268, 2007, ACM, 978-1-59593-686-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
date stream, pattern growth, pseudo periodicity, variation management |
27 | Shankar Krishnamoorthy |
Variation and litho driven physical implementation system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007, pp. 170, 2007, ACM, 978-1-59593-613-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-variation optimization, VLSI, lithography |
27 | Alexander V. Mitev, Michael M. Marefat, Dongsheng Ma, Janet Meiling Wang |
Principle hessian direction based parameter reduction for interconnect networks with process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 41-46, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
principle Hessian directions, process variation, timing analysis |
27 | Kimmo Kettunen 0001 |
Management of keyword variation with frequency based generation of word forms in IR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGIR ![In: SIGIR 2007: Proceedings of the 30th Annual International ACM SIGIR Conference on Research and Development in Information Retrieval, Amsterdam, The Netherlands, July 23-27, 2007, pp. 691-692, 2007, ACM, 978-1-59593-597-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
management of morphological variation, monolingual information retrieval, word form generation, evaluation |
27 | Abhishek Tiwari 0002, Smruti R. Sarangi, Josep Torrellas |
ReCycle: : pipeline adaptation to tolerate process variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 323-334, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
pipeline, process variation, clock skew |
27 | Mehrdad Nourani, Arun Radhakrishnan |
Testing On-Die Process Variation in Nanometer VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(6), pp. 438-451, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
nanometer VLSI, ultra deep-submicron, fast Fourier transform, process variation, frequency domain, ring oscillator |
27 | James Donald, Margaret Martonosi |
Power efficiency for variation-tolerant multicore processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 304-309, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
power, multicore, parallel applications, variation |
27 | Ke Meng, Russ Joseph |
Process variation aware cache leakage management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 262-267, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
gated-VDD, selective cache ways, low power, process variation, leakage, cache management |
27 | Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De |
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 79-84, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant |
27 | Nandakumar P. Venugopal, Nihal Shastry, Shambhu J. Upadhyaya |
Effect of Process Variation on the Performance of Phase Frequency Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 525-534, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Phase Frequency Detector (PFD), NFET, PFET, process variation, Monte Carlo simulation, Jitter, Phase noise |
27 | Guoliang Xu, Qin Zhang 0005 |
Minimal Mean-Curvature-Variation Surfaces and Their Applications in Surface Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GMP ![In: Geometric Modeling and Processing - GMP 2006, 4th International Conference, Pittsburgh, PA, USA, July 26-28, 2006, Proceedings, pp. 357-370, 2006, Springer, 3-540-36711-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Minimal mean-curvature-variation flow, Discretization, Surface modeling, Energy functional, Euler-Lagrange equation |
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