Search results for "virtex"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
62	Ludovico de Souza, John D. Bunton, Duncan Campbell-Wilson, Roger J. Cappallo, Barton B. Kincaid	A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA.	FPL	2007	DBLP DOI BibTeX RDF
54	Jürgen Becker 0001, Michael Hübner 0001, Michael Ullmann	Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations.	SBCCI	2003	DBLP DOI BibTeX RDF	Virtex FPGA, runtime reconfiguration, power consumption
54	Anup Kumar Raghavan, Peter Sutton	JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs.	IPDPS	2002	DBLP DOI BibTeX RDF	JBits, FPGA design flow, Partial Bitstream, Xilinx Virtex, Partial Reconfiguration
54	Michael Hübner 0001, Lars Braun, Jürgen Becker 0001, Christopher Claus, Walter Stechele	Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs.	ISVLSI	2007	DBLP DOI BibTeX RDF
54	Parimal Patel	Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA.	VLSI Design	2007	DBLP DOI BibTeX RDF
54	Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo	Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
46	Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly	Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems.	FPL	2006	DBLP DOI BibTeX RDF
46	S. Sukhsawas, Khaled Benkrid	A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs.	ISVLSI	2004	DBLP DOI BibTeX RDF
46	Edson L. Horta, John W. Lockwood	Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
46	Abdsamad Benkrid, Khaled Benkrid, Danny Crookes	Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
46	Abdsamad Benkrid, Khaled Benkrid, Danny Crookes	A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs.	FCCM	2003	DBLP DOI BibTeX RDF
46	Jerzy Kasperek	Real Time Morphological Image Contrast Enhancement in Virtex FPGA.	FPL	2001	DBLP DOI BibTeX RDF
42	Muzaffar Rao, Thomas Newe, Ian Andrew Grout, Avijit Mathur	High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs.	J. Circuits Syst. Comput.	2016	DBLP DOI BibTeX RDF
42	Liuba Slasten, Alexey Dordopulo, Igor Kaliaev, Ilya I. Levin	Reconfigurable Computer Systems Based on Virtex-6 and Virtex-7 FPGAs.	PDeS	2013	DBLP DOI BibTeX RDF
42	Amir Moradi 0001, Markus Kasper, Christof Paar	Black-Box Side-Channel Attacks Highlight the Importance of Countermeasures - An Analysis of the Xilinx Virtex-4 and Virtex-5 Bitstream Encryption Mechanism.	CT-RSA	2012	DBLP DOI BibTeX RDF
42	Christian Schuck, Bastian Haetzer, Jürgen Becker 0001	Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs.	Int. J. Reconfigurable Comput.	2011	DBLP DOI BibTeX RDF
42	Amir Moradi 0001, Markus Kasper, Christof Paar	On the Portability of Side-Channel Attacks - An Analysis of the Xilinx Virtex 4 and Virtex 5 Bitstream Encryption Mechanism.	IACR Cryptol. ePrint Arch.	2011	DBLP BibTeX RDF
42	Christian Schuck, Bastian Haetzer, Jürgen Becker 0001	Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/ Virtex II-Pro FPGAs: A Case Study of Distributed Power Management.	ReCoSoC	2010	DBLP BibTeX RDF
42	Bradley F. Dutton, Charles E. Stroud	Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs.	CATA	2009	DBLP BibTeX RDF
42	Bradley F. Dutton, Charles E. Stroud	Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs.	ESA	2009	DBLP BibTeX RDF
41	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
41	Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel	Power estimation approach for SRAM-based FPGAs.	FPGA	2000	DBLP DOI BibTeX RDF
37	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
37	Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal	Architecture-specific packing for virtex-5 FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, performance, FPGAs, field-programmable gate arrays, power, placement, packing
37	Rashad S. Oreifej, Rawad N. Al-Haddad, Heng Tan, Ronald F. DeMara	Layered Approach to Instrinsic Evolvable Hardware Using Direct Bistream Manipulation of VIRTEX II Pro Devices.	FPL	2007	DBLP DOI BibTeX RDF
37	Christopher Claus, Florian Helmut Müller, Johannes Zeppenfeld, Walter Stechele	A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration.	IPDPS	2007	DBLP DOI BibTeX RDF
37	Abdsamad Benkrid, Khaled Benkrid, Danny Crookes	Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs.	ISVLSI	2004	DBLP DOI BibTeX RDF
37	Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMara	Evolutionary Fault Recovery in a Virtex FPGA Using a Representation that Incorporates Routing.	IPDPS	2003	DBLP DOI BibTeX RDF
37	Jason D. Lohn, Gregory V. Larchev, Ronald F. DeMara	A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs.	ICES	2003	DBLP DOI BibTeX RDF
37	Li Shang, Alireza Kaviani, Kusuma Bathala	Dynamic power consumption in Virtex[tm]-II FPGA family.	FPGA	2002	DBLP DOI BibTeX RDF
37	Jean-Luc Beuchat, Arnaud Tisserand	Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices.	FPL	2002	DBLP DOI BibTeX RDF
37	Gordon J. Brebner	Single-Chip Gigabit Mixed-Version IP Router on Virtex-II Pro.	FCCM	2002	DBLP DOI BibTeX RDF
37	Felix Albu, Jiri Kadlec, Christopher I. Softley, Rudolf Matousek, Antonin Hermanek, Nick Coleman, Anthony D. Fagan	Implementation of (Normalised) RLS Lattice on Virtex.	FPL	2001	DBLP DOI BibTeX RDF
37	Yoshiki Yamaguchi, Akira Miyashita, Tsutomu Maruyama, Tsutomu Hoshino	A Co-processor System with a Virtex FPGA for Evolutionary Computation.	FPL	2000	DBLP DOI BibTeX RDF
37	Cesar Ortega-Sanchez, Andrew M. Tyrrell	A Hardware Implementation of an Embryonic Architecture Using Virtex FPGAs.	ICES	2000	DBLP DOI BibTeX RDF
37	Cameron Patterson	High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm).	FCCM	2000	DBLP DOI BibTeX RDF
37	Gordon Hollingworth, Steve Smith, Andrew M. Tyrrell	Safe Intrinsic Evolution of Virtex Devices.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
33	Roman C. Kordasiewicz, Shahram Shirani	On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, Quantization, hardware implementations, MPEG4
33	Roman C. Kordasiewicz, Shahram Shirani	On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, quantization, hardware implementations, MPEG4
33	Kuan Zhou, John F. McDonald 0001	Multi-GHz SiGe design methodologies for reconfigurable computing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	CLB, virtex, FPGA, SiGe
33	Tomasz S. Czajkowski, Jonathan Rose	A synthesis oriented omniscient manual editor.	FPGA	2004	DBLP DOI BibTeX RDF	virtex-e, synthesis, manual
33	Michael Hübner 0001, Tobias Becker, Jürgen Becker 0001	Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration.	SBCCI	2004	DBLP DOI BibTeX RDF	virtex, dynamic partial reconfiguration
33	Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich	Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration.	IPDPS	2004	DBLP DOI BibTeX RDF	Virtex, Compression, Decompression
33	Jiri Novotný, Otto Fucík, David Antos	Project of IPv6 Router with FPGA Hardware Accelerator.	FPL	2003	DBLP DOI BibTeX RDF	Liberouter, Virtex II, FPGA, IPv6, router
33	Andreas Koch	A Comprehensive Prototyping-Platform for Hardware-Software Codesign.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	hybrid processor, RTEMS, Virtex, FPGA, prototyping, codesign, SPARC, Xilinx
33	Neil Steiner, Peter M. Athanas	An Alternate Wire Database for Xilinx FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
29	Michalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou	Implementation of a genetic algorithm on a virtex-ii pro FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	multiplier blocks, genetic algorithm, fpga, fitness functions
29	Radu Andrei Stefan, Sorin Dan Cotofana	Bitstream compression techniques for Virtex 4 FPGAs.	FPL	2008	DBLP DOI BibTeX RDF
29	Andreas Ehliar, Per Karlström, Dake Liu	A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA.	FPL	2008	DBLP DOI BibTeX RDF
29	Mamoun F. Al-Mistarihi	Separable implementation of the second order Volterra filter (SOVF) in Xilinx Virtex-E FPGA.	FPL	2008	DBLP DOI BibTeX RDF
29	Philippe Bulens, François-Xavier Standaert, Jean-Jacques Quisquater, Pascal Pellegrin, Gaël Rouvroy	Implementation of the AES-128 on Virtex-5 FPGAs.	AFRICACRYPT	2008	DBLP DOI BibTeX RDF
29	Stefan Raaijmakers, Stephan Wong	Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro.	FPL	2007	DBLP DOI BibTeX RDF
29	Irwin O. Kennedy	Implementation of Low Frequency Finite State Machines Using the VIRTEX SRL16 Primitive.	FPL	2007	DBLP DOI BibTeX RDF
29	Bas Breijer, Filipa Duarte, Stephan Wong	An OCM based shared Memory controller for Virtex 4.	FPL	2007	DBLP DOI BibTeX RDF
29	Antonio Plaza	Towards Real-Time Compression of Hyperspectral Images Using Virtex-II FPGAs.	Euro-Par	2007	DBLP DOI BibTeX RDF
29	Kyrre Glette, Jim Tørresen, Moritoshi Yasunaga	Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA.	AHS	2007	DBLP DOI BibTeX RDF
29	Filipa Duarte, Stephan Wong	Profiling Bluetooth and Linux on the Xilinx Virtex II Pro.	DSD	2006	DBLP DOI BibTeX RDF
29	Michael Hübner 0001, Christian Schuck, Jürgen Becker 0001	Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs.	IPDPS	2006	DBLP DOI BibTeX RDF
29	Carsten Bieser, Klaus D. Müller-Glaser	Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
29	Heiko Kalte, Mario Porrmann	REPLICA2Pro: task relocation by bitstream manipulation in virtex-II/Pro FPGAs.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	bitstream manipulation, task relocation, FPGA, reconfigurable computing
29	Melanie Po-Leen Ooi	Hardware Implementation for Face Detection on Xilinx Virtex-II FPGA using the Reversible Component Transformation Colour Space.	DELTA	2006	DBLP DOI BibTeX RDF
29	Peter J. Green, Desmond P. Taylor	Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmable Gate Array.	DELTA	2006	DBLP DOI BibTeX RDF
29	Jing Lu, John W. Lockwood	IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application.	IPDPS	2005	DBLP DOI BibTeX RDF
29	Kyrre Glette, Jim Tørresen	A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device.	ICES	2005	DBLP DOI BibTeX RDF
29	Monica Alderighi, A. Candelori, Fabio Casini, Sergio D'Angelo, Marcello Mancini, Alessandro Paccagnella, Sandro Pastore, Giacomo R. Sechi	Heavy Ion Effects on Configuration Logic of Virtex FPGAs.	IOLTS	2005	DBLP DOI BibTeX RDF
29	Georgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis	The Virtex II ProTM MOLEN Processor.	SAMOS	2004	DBLP DOI BibTeX RDF
29	David Elléouet, Nathalie Julien, Dominique Houzet, Jean-Gabriel Cousin, Eric Martin 0001	Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA.	DSD	2004	DBLP DOI BibTeX RDF
29	Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek	Post-placement C-slow retiming for the xilinx virtex FPGA.	FPGA	2003	DBLP DOI BibTeX RDF	C-slow retiming, FPGA CAD, FPGA optimization, retiming
29	Xiaojun Wang, Brent E. Nelson	Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs.	FCCM	2003	DBLP DOI BibTeX RDF
29	Monica Alderighi, Fabio Casini, Sergio D'Angelo, Marcello Mancini, A. Marmo, Sandro Pastore, Giacomo R. Sechi	A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs.	DFT	2003	DBLP DOI BibTeX RDF
29	Ian Robertson, James Irvine 0001, Patrick Lysaght, David Robinson	Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA, verification, dynamic reconfiguration, run-time reconfiguration
29	Matthias Dyer, Christian Plessl, Marco Platzner	Partially Reconfigurable Cores for Xilinx Virtex.	FPL	2002	DBLP DOI BibTeX RDF
29	Alexander Staller, Peter Dillinger, Reinhard Männer	Implementation of the JPEG 2000 Standard on a Virtex 1000 FPGA.	FPL	2002	DBLP DOI BibTeX RDF
29	Trevor W. Fox, Laurence E. Turner	Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA.	FPL	2002	DBLP DOI BibTeX RDF
29	Oswaldo Cadenas, Graham M. Megson	A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs.	FPL	2002	DBLP DOI BibTeX RDF
29	Tim Courtney, Richard H. Turner, Roger F. Woods	Multiplexer Based Reconfiguration for Virtex Multipliers.	FPL	2000	DBLP DOI BibTeX RDF
29	Gordon Hollingworth, Steve Smith, Andy M. Tyrrell	The Intrinsic Evolution of Virtex Devices Through Internet Reconfigurable Logic.	ICES	2000	DBLP DOI BibTeX RDF
24	Hao Wang, Shi Pu, Gabriel Knezek, Jyh-Charn Liu	A modular NFA architecture for regular expression matching.	FPGA	2010	DBLP DOI BibTeX RDF	character class constraint repetition, overlapped matching, FPGA, regular expression, NFA
24	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
24	Lei Chen 0010, Zhiquan Zhang, Zhiping Wen 0001	A novel BIST approach for testing input/output buffers in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	i/o buffers, built-in self-test, fpga testing
24	Pramod Kumar Meher, Jagdish Chandra Patra	Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform.	ASAP	2008	DBLP DOI BibTeX RDF
24	Patrick Lysaght, Brandon Blodget, Jeff Mason, Jay Young, Brendan Bridgford	Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
24	Roar Lien, Tim Grembowski, Kris Gaj	A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512.	CT-RSA	2004	DBLP DOI BibTeX RDF
21	Saber Krim, Mohamed Faouzi Mimouni	Design and Xilinx Virtex-field-programmable gate array for hardware in the loop of sensorless second-order sliding mode control and model reference adaptive system-sliding mode observer for direct torque control of induction motor drive.	J. Syst. Control. Eng.	2023	DBLP DOI BibTeX RDF
21	N. Sathiabama, S. Anila	A Universal BIST Approach for Virtex-Ultrascale Architecture.	Comput. Syst. Sci. Eng.	2023	DBLP DOI BibTeX RDF
21	Chang Cai, Bingxu Ning, Xue Fan, Tianqi Liu, Lingyun Ke, Gengsheng Chen, Jian Yu, Ze He, Liewei Xu, Jie Liu 0032	SEU sensitivity and large spacing TMR efficiency of Kintex-7 and Virtex-7 FPGAs.	Sci. China Inf. Sci.	2022	DBLP DOI BibTeX RDF
21	M. Vivekanandan, Subramanian Kanaga Suba Raja	Virtex-II Pro FPGA Based Smart Agricultural System.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
21	Ahmed J. Abd El-Maksoud, Amr Gamal, Aya Hesham, Gamal Saied, Mennat-Allah Ayman, Omnia Essam, Sara M. Mohamed, Eman El Mandouh, Ziad Ibrahim, Sara Mohamed, Hassan Mostafa	Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA.	ICM	2021	DBLP DOI BibTeX RDF
21	Karan Desai, Justin Johnson 0001	VirTex: Learning Visual Representations From Textual Annotations.	CVPR	2021	DBLP BibTeX RDF
21	Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa	Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7.	ISDCS	2021	DBLP DOI BibTeX RDF
21	Mahendrakumar Gunasekaran, Kumar Rahul, Santosh Yachareni	Optimizing Sub bytes and Mix Column to improve performance of AES in Virtex 7 FPGA.	ISNCC	2021	DBLP DOI BibTeX RDF
21	Baoju Chen, Simin Yu, Ping Chen, Liangshan Xiao, Jinhu Lü	Design and Virtex-7-Based Implementation of Video Chaotic Secure Communications.	Int. J. Bifurc. Chaos	2020	DBLP DOI BibTeX RDF
21	Karan Desai, Justin Johnson 0001	VirTex: Learning Visual Representations from Textual Annotations.	CoRR	2020	DBLP BibTeX RDF
21	Ali H. Gad, Seif Eldeen E. Abdalazeem, Omar A. Abdelmegid, Hassan Mostafa	Low power and area SHA-256 hardware accelerator on Virtex-7 FPGA.	NILES	2020	DBLP DOI BibTeX RDF
21	Abd El-Rahman Mohsen, Mohamed Youssef GadAlrab, Zeina elhaya Mahmoud, Gameel Alshaer, Mahmoud Asy, Hassan Mostafa	Remote FPGA Lab For ZYNQ and Virtex-7 Kits.	MWSCAS	2019	DBLP DOI BibTeX RDF
21	Abbas Yazdinejad, Ali Bohlooli, Kamal Jamshidi	Efficient design and hardware implementation of the OpenFlow v1.3 Switch on the Virtex-6 FPGA ML605.	J. Supercomput.	2018	DBLP DOI BibTeX RDF
21	Javier Olivito, Felipe Serrano, Juan Antonio Clemente, Hortensia Mecha, Javier Resano	Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array.	IET Comput. Digit. Tech.	2018	DBLP DOI BibTeX RDF
21	Lars Engeln, Rainer Groh 0001	VirtEx: Eine Ontologie-basierte Virtuelle Ausstellungen.	MuC	2018	DBLP DOI BibTeX RDF
21	Chao Wang, Shengjun Xiong	A High-precision Underwater Acoustic Communication Signal Modeling Method Based on VirTEX Algorithm.	ICSPCC	2018	DBLP DOI BibTeX RDF
21	Tingting Yu, Lei Chen 0010, Xuewu Li, Shuo Wang, Jing Zhou	Analyzing the Single Event Upset Sensitivity of Digital Clock Manager in Virtex-5 FPGA.	IEEA	2017	DBLP DOI BibTeX RDF