Search results for "zero-skew"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
95	Zhaoyun Xing, Prithviraj Banerjee	A parallel algorithm for zero skew clock tree routing.	ISPD	1998	DBLP DOI BibTeX RDF
89	Joe G. Xi, Wayne Wei-Ming Dai	Jitter-tolerant clock routing in two-phase synchronous systems.	ICCAD	1996	DBLP DOI BibTeX RDF	Deferred-Merge Embedding framework, clock jitter, clock tree cost, jitter-tolerance, jitter-tolerant clock routing, near-zero skew, nonoverlapping interval, safety margin, system operating conditions, two-phase clocking, two-phase jitter-tolerant useful-skew tree, two-phase synchronous systems, simulated annealing, manufacturing, jitter, zero skew
85	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time.	ISPD	2003	DBLP DOI BibTeX RDF	?-optimal, incremental refinement, pseudo-polynomial, clock tree, wire-sizing, zero-skew
81	Chia-Chun Tsai, Jan-Ou Wu, Chung-Chieh Kuo, Trong-Yen Lee, Wen-Ta Lee	Zero-Skew Driven for RLC Clock Tree Construction in SoC.	ICITA (1)	2005	DBLP DOI BibTeX RDF	RLC delay model, Upward propagation, SoC, Clock tree, Zero skew
76	Yu Chen 0005, Andrew B. Kahng, Gang Qu 0001, Alexander Zelikovsky	The associative-skew clock routing problem.	ICCAD	1999	DBLP DOI BibTeX RDF
72	José Luis Neves, Eby G. Friedman	Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
71	Chung-Wen Albert Tsao, Cheng-Kok Koh	UST/DME: a clock tree router for general skew constraints.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Useful Skew, feasible skew range, incremental skew scheduling, merging and embedding, merging region, clock tree
68	Joe G. Xi, Wayne Wei-Ming Dai	Useful-Skew Clock Routing with Gate Sizing for Low Power Design.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
68	Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria	Zero skew differential clock distribution network.	ISCAS	2006	DBLP DOI BibTeX RDF
66	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	A single layer zero skew clock routing in X architecture.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	single layer, X architecture, zero skew, clock routing
65	Alexander Zelikovsky, Ion I. Mandoiu	Practical approximation algorithms for zero- and bounded-skew trees.	SODA	2001	DBLP BibTeX RDF
64	Chia-Chun Tsai, Jan-Ou Wu, Yu-Ting Shieh, Chung-Chieh Kuo, Trong-Yen Lee	Tapping Point Numerical-Based Search for Exact Zero-Skew RLC Clock Tree Construction.	APCCAS	2006	DBLP DOI BibTeX RDF
64	Ren-Song Tsay	An exact zero-skew clock routing algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
60	Wei-Chung Chao, Wai-Kei Mak	Low-power gated and buffered clock network construction.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low power, buffer, clock gating, Clock tree, zero-skew
56	Uday Padmanabhan, Janet Meiling Wang, Jiang Hu	Robust Clock Tree Routing in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
56	Uday Padmanabhan, Janet Meiling Wang, Jiang Hu	Statistical clock tree routing for robustness to process variations.	ISPD	2006	DBLP DOI BibTeX RDF	routing, robustness, process variations, clock tree
55	Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili	Quadratic deferred-merge embedding algorithm for zero skew clock distribution network.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	VLSI, clock distribution network, zero skew
53	Jeng-Liang Tsai, Charlie Chung-Ping Chen	Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling.	ASP-DAC	2005	DBLP DOI BibTeX RDF
52	Chia-Ming Chang 0002, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang 0002, Yu-Sheng Lu	Type-matching clock tree for zero skew clock gating.	DAC	2008	DBLP DOI BibTeX RDF	physical design, gated clock, clock network synthesis
51	Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao	Bounded-skew clock and Steiner routing under Elmore delay.	ICCAD	1995	DBLP DOI BibTeX RDF	bounded-skew, pathlength delay, VLSI, global routing, Elmore delay, zero-skew, zero-skew, clock routing, routing trees
49	Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown	Process-induced skew reduction in nominal zero-skew clock trees.	ASP-DAC	2006	DBLP DOI BibTeX RDF
49	Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Ping Chen	Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
41	Hao Yu 0001, Yu Hu 0002, Chunchen Liu, Lei He 0001	Minimal skew clock embedding considering time variant temperature gradient.	ISPD	2007	DBLP DOI BibTeX RDF	clock tree design, compact parameterization, parameterized perturbation, thermal management
41	Anand Rajaram, Jiang Hu, Rabi N. Mahapatra	Reducing clock skew variability via cross links.	DAC	2004	DBLP DOI BibTeX RDF	VLSI, physical design, variation, clock network synthesis
41	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.	ISQED	2007	DBLP DOI BibTeX RDF
41	Andrew B. Kahng, Chung-Wen Albert Tsao	Planar-DME: a single-layer zero-skew clock tree router.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
41	Nan-Chi Chou, Chung-Kuan Cheng	On general zero-skew clock net construction.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
38	Shen Lin, C. K. Wong	Process-variation-tolerant clock skew minimization.	ICCAD	1994	DBLP DOI BibTeX RDF
35	Jean Ponce	On Computing Metric Upgrades of Projective Reconstructions Under the Rectangular Pixel Assumption.	SMILE	2000	DBLP DOI BibTeX RDF
34	Zhuo Li 0001, Nancy Ying Zhou, Weiping Shi	Wire Sizing for Non-Tree Topology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
34	Bing Lu, Jiang Hu, Gary Ellis, Haihua Su	Process variation aware clock tree routing.	ISPD	2003	DBLP DOI BibTeX RDF	VLSI, interconnect, physical design, clock tree synthesis
34	Mohamed Nekili, Yvon Savaria, Guy Bois	Minimizing process-induced skew using delay tuning.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
34	Qing Zhu, Wayne Wei-Ming Dai	High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
31	Vineet Wason, Rajeev Murgai, William W. Walker	An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis.	VLSI Design	2007	DBLP DOI BibTeX RDF
31	Rishi Chaturvedi, Jiang Hu	Buffered Clock Tree for High Quality IC Design.	ISQED	2004	DBLP DOI BibTeX RDF
31	Rishi Chaturvedi, Jiang Hu	A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing.	ICCD	2003	DBLP DOI BibTeX RDF
30	Xinjie Wei, Yici Cai, Xianlong Hong	Zero skew clock routing with tree topology construction using simulated annealing method.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
26	Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong	Legitimate Skew Clock Routing with Buffer Insertion.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	legitimate skew, buffer insertion, clock routing
26	Min-Seok Kim, Jiang Hu	Associative skew clock routing for difficult instances.	DATE	2006	DBLP DOI BibTeX RDF
26	Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen	Optimal spacing and capacitance padding for general clock structures.	ASP-DAC	2001	DBLP DOI BibTeX RDF
26	Mohamed Nekili, Yvon Savaria, Guy Bois	Design of Clock Distribution Networks in Presence of Process Variations.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	process variations, clock skew, clock distribution
26	Mitsuho Seki, Kenji Inoue, Kazuo Kato, Kouki Tsurusaki, Shin'ichi Fukasawa, Hitoshi Sasaki, Mutsuhito Aizawa	A specified delay accomplishing clock router using multiple layers.	ICCAD	1994	DBLP DOI BibTeX RDF
25	Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi 0001	A practical clock tree synthesis for semi-synchronous circuits.	ISPD	2000	DBLP DOI BibTeX RDF	clock-input timing, environmental and manufacturing conditions, semi-synchronous, various timing clock tree, zero skew clock tree, clock scheduling
25	Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao	Bounded-skew clock and Steiner routing.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	(inter)connection, boundary merging and embedding, bounded-skew, interior merging and embedding, merging region, merging segment, pathlength delay, VLSI, low power, synchronization, Steiner tree, clock tree, Elmore delay, zero-skew
23	Andrew B. Kahng, Chung-Wen Albert Tsao	Low-cost single-layer clock trees with exact zero Elmore delay skew.	ICCAD	1994	DBLP DOI BibTeX RDF
19	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
19	Amir H. Ajami, Kaustav Banerjee, Massoud Pedram	Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
19	Shahin Nazarian, Massoud Pedram, Emre Tuncer	An empirical study of crosstalk in VDSM technologies.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	automatic test pattern generation (ATPG) tool, crosstalk induced slowdown and speedup, transition time, static timing analysis (STA), skew
19	Yongqiang Lu 0001, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Liang Huang, Jiang Hu	Navigating registers in placement for clock network minimization.	DAC	2005	DBLP DOI BibTeX RDF	low power, placement, clock network, variation tolerance
19	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi	Post-processing of clock trees via wiresizing and buffering for robust design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
18	Wei Wang, Vasilis F. Pavlidis, Yuanqing Cheng	Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength.	ACM Great Lakes Symposium on VLSI	2020	DBLP DOI BibTeX RDF
18	Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang 0002, Song-Bin Pan	Low-power anti-aging zero skew clock gating.	ACM Trans. Design Autom. Electr. Syst.	2013	DBLP DOI BibTeX RDF
18	Adlane Habed, Kassem Al Ismaeil, David Fofi	A New Set of Quartic Trivariate Polynomial Equations for Stratified Camera Self-calibration under Zero-Skew and Constant Parameters Assumptions.	ECCV (6)	2012	DBLP DOI BibTeX RDF
18	Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee	Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration.	Integr.	2011	DBLP DOI BibTeX RDF
18	Shih-Hsu Huang, Chia-Ming Chang 0002, Wen-Pin Tu, Song-Bin Pan	Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating.	ASP-DAC	2010	DBLP DOI BibTeX RDF
18	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.	Integr.	2008	DBLP DOI BibTeX RDF
18	Chia-Chun Tsai, Jan-Ou Wu, Trong-Yen Lee	GDME: Grey Relational Clustering Applied to a Clock Tree Construction with Zero Skew and Minimal Delay.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2008	DBLP DOI BibTeX RDF
18	Jan-Ou Wu, Chia-Chun Tsai, Chung-Chieh Kuo, Trong-Yen Lee	Zero-Skew Driven Buffered RLC Clock Tree Construction.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2007	DBLP DOI BibTeX RDF
18	I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong 0001	Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion.	ISPD	2000	DBLP DOI BibTeX RDF
18	Y. P. Chen, D. F. Wong 0001	An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion.	ED&TC	1996	DBLP DOI BibTeX RDF
18	José Luis Neves, Eby G. Friedman	Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks.	ISCAS	1995	DBLP BibTeX RDF
18	Chung-Wen Albert Tsao, Andrew B. Kahng	Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay.	EURO-DAC	1994	DBLP DOI BibTeX RDF
18	Masato Edahiro	An Efficient Zero-Skew Routing Algorithm.	DAC	1994	DBLP DOI BibTeX RDF
18	Masato Edahiro	A Clustering-Based Optimization Algorithm in Zero-Skew Routings.	DAC	1993	DBLP DOI BibTeX RDF
18	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage	Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization.	DAC	1993	DBLP DOI BibTeX RDF
18	Wasim Khan, Moazzem Hossain, Naveed A. Sherwani	Zero skew clock routing in multiple-clock synchronous systems.	ICCAD	1992	DBLP DOI BibTeX RDF
18	Ying-Meng Li, Marwan A. Jabri	A zero-skew clock routing scheme for VLSI circuits.	ICCAD	1992	DBLP DOI BibTeX RDF
18	Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho	Zero Skew Clock Net Routing.	DAC	1992	DBLP BibTeX RDF
18	Ren-Song Tsay	Exact Zero Skew.	ICCAD	1991	DBLP DOI BibTeX RDF
16	Kevin Köser, Christian Beder, Reinhard Koch	Conjugate rotation: Parameterization and estimation from an affine feature correspondence.	CVPR	2008	DBLP DOI BibTeX RDF
12	Henrik Aanæs, Klas Josephson, Francois Anton, Jakob Andreas Bærentzen, Fredrik Kahl	Camera Resectioning from a Box.	SCIA	2009	DBLP DOI BibTeX RDF
12	Chia-Chun Tsai, Chung-Chieh Kuo, Jan-Ou Wu, Trong-Yen Lee, Rong-Shue Hsiao	X-clock routing based on pattern matching.	SoCC	2008	DBLP DOI BibTeX RDF
12	Yanfeng Wang, Qiang Zhou 0001, Xianlong Hong, Yici Cai	Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.	ISCAS	2007	DBLP DOI BibTeX RDF
12	Xiaochun Cao, Hassan Foroosh	Camera Calibration Using Symmetric Objects.	IEEE Trans. Image Process.	2006	DBLP DOI BibTeX RDF
12	Michal Perdoch, Jiri Matas, Ondrej Chum	Epipolar Geometry from Two Correspondences.	ICPR (4)	2006	DBLP DOI BibTeX RDF
12	Xianghua Ying, Hongbin Zha	Interpreting Sphere Images Using the Double-Contact Theorem.	ACCV (1)	2006	DBLP DOI BibTeX RDF
12	Xianghua Ying, Hongbin Zha	Linear Approaches to Camera Calibration from Sphere Images or Active Intrinsic Calibration Using Vanishing Points.	ICCV	2005	DBLP DOI BibTeX RDF
12	Xiaochun Cao, Hassan Foroosh	Camera calibration without metric information using 1D objects.	ICIP	2004	DBLP DOI BibTeX RDF
12	Xiaochun Cao, Hassan Foroosh	Simple Calibration Without Metric Information Using an Isoceles Trapezoid.	ICPR (1)	2004	DBLP DOI BibTeX RDF
12	Yan Li, Yeung Sam Hung	A Stratified Self-Calibration Method for a Stereo Rig in Planar Motion with Varying Intrinsic Parameters.	DAGM-Symposium	2004	DBLP DOI BibTeX RDF
12	Adlane Habed, Boubakeur Boufama	Self-Calibration of a Simplified Camera Using Kruppa Equations.	CRV	2004	DBLP DOI BibTeX RDF
12	Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura 0001, Ali Keshavarzi	Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism.	ITC	2004	DBLP DOI BibTeX RDF
12	Lior Wolf, Assaf Zomet	Sequence-to-Sequence Self Calibration.	ECCV (2)	2002	DBLP DOI BibTeX RDF	Multi-View Invariants, Self-Calibration
12	Jaewon Oh, Massoud Pedram	Gated clock routing for low-power microprocessor design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
12	Amir H. Farrahi, Chunhong Chen, Ankur Srivastava 0001, Gustavo E. Téllez, Majid Sarrafzadeh	Activity-driven clock design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
12	Yongduek Seo, Anders Heyden, Roberto Cipolla	A Linear Iterative Method for Auto-Calibration using the DAC Equation.	CVPR (1)	2001	DBLP DOI BibTeX RDF
12	Yongduek Seo, Anders Heyden	Auto-Calibration from the Orthogonality Constraints.	ICPR	2000	DBLP DOI BibTeX RDF
12	Lourdes de Agapito, Eric Hayman, Richard I. Hartley	Linear Self-Calibration of a Rotating and Zooming Camera.	CVPR	1999	DBLP DOI BibTeX RDF	varying intrinsic parameters, rotating camera, linear method, zooming camera, self-calibration
12	Jaewon Oh, Massoud Pedram	Gated Clock Routing Minimizing the Switched Capacitance.	DATE	1998	DBLP DOI BibTeX RDF	gated clock routing, low power
12	Atsushi Takahashi 0001, Kazunori Inoue, Yoji Kajitani	Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	clock-tree routing, semi-synchronous, deferred-merge-embedding (DME), synchronous, buffer insertion, buffer sizing, clock-schedule
12	Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi	Solving the net matching problem in high-performance chip design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
12	Masato Edahiro, Richard J. Lipton	Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	VLSI, CAD, Placement, Layout, Buffer, Clock