Search results for "Retiming"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
46	Otmane Aït Mohamed, Eduard Cerny, Xiaoyu Song	MDG-based Verification by Retiming and Combinational Transformations.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Circuit Transformations, Non-termination, Formal Verification, Retiming, Multiway Decision Graphs
46	Larry R. Dennison, William J. Dally, Thucydides Xanthopoulos	Low-latency plesiochronous data retiming.	ARVLSI	1995	DBLP DOI BibTeX RDF	telecommunication signalling, data retiming, plesiochronous data, support circuitry, undirectional signalling, timing, latency, communication networks, routers, telecommunication network routing, repeaters, repeaters, bridges, hubs
45	Noureddine Chabini, Wayne H. Wolf	An approach for reducing dynamic power consumption in synchronous sequential digital designs.	ASP-DAC	2004	DBLP DOI BibTeX RDF
45	Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	Timing Optimization of Nested Loops Considering Code Size for DSP Applications.	ICPP	2004	DBLP DOI BibTeX RDF
41	Dmitry Bufistov, Jordi Cortadella, Marc Galceran Oms, Jorge Júlvez, Michael Kishinevsky	Retiming and recycling for elastic systems with early evaluation.	DAC	2009	DBLP DOI BibTeX RDF	early evaluation, elastic systems, optimization
41	Khurram Waheed, Robert Bogdan Staszewski, John L. Wallberg	Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation.	ISCAS	2007	DBLP DOI BibTeX RDF
41	Mongkol Ekpanyapong, Thaisiri Watewai, Sung Kyu Lim	Statistical Bellman-Ford algorithm with an application to retiming.	ASP-DAC	2006	DBLP DOI BibTeX RDF
41	Noureddine Chabini, Wayne H. Wolf	Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
41	Robert Fischer 0002, Klaus Buchenrieder, Ulrich Nageldinger	Reducing the Power Consumption of FPGAs through Retiming.	ECBS	2005	DBLP DOI BibTeX RDF
41	Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.	Optimal joint module-selection and retiming with carry-save representation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
41	Chris C. N. Chu, Evangeline F. Y. Young, Dennis K. Y. Tong, Sampath Dechu	Retiming with Interconnect and Gate Delay.	ICCAD	2003	DBLP DOI BibTeX RDF
41	Chuan Lin 0002, Hai Zhou 0001	Retiming for Wire Pipelining in System-On-Chip.	ICCAD	2003	DBLP DOI BibTeX RDF
41	Pasin Israsena, S. Summerfield	Bit-level retiming of high-speed digital recursive filters.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
41	Gianpiero Cabodi, Stefano Quer, Fabio Somenzi	Optimizing sequential verification by retiming transformations.	DAC	2000	DBLP DOI BibTeX RDF
41	Srimat T. Chakradhar, Sujit Dey	Resynthesis and retiming for optimum partial scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
41	Priyank Kalla, Maciej J. Ciesielski	Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence.	DATE	1999	DBLP DOI BibTeX RDF
41	Prashant Saxena, Peichen Pan, C. L. Liu 0001	The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches.	VLSI Design	1999	DBLP DOI BibTeX RDF
41	Peichen Pan, Arvind K. Karandikar, C. L. Liu 0001	Optimal clock period clustering for sequential circuits with retiming.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
41	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee	Efficient equivalence checking of multi-phase designs using phase abstraction and retiming.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	binary decision, encoding density, multi-phase FSM, product machine, sequential hardware equivalence, diagram, steady states
41	Peichen Pan, Chih-Chang Lin	A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
41	Jason Cong, Chang Wu	FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits.	DAC	1997	DBLP DOI BibTeX RDF
41	Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Retiming and resynthesis: optimizing sequential networks with combinational techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
39	Duo Liu, Zili Shao, Meng Wang 0005, Minyi Guo, Jingling Xue	Optimal loop parallelization for maximizing iteration-level parallelism.	CASES	2009	DBLP DOI BibTeX RDF	iteration-level parallelism, retiming, loop transformation, loop parallelization, data dependence graph
39	François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer	Optimal design of synchronous circuits using software pipelining techniques.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	software pipelining, retiming, Resynthesis
39	Sujit Dey, Srimat T. Chakradhar	Design of testable sequential circuits by repositioning flip-flops.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	cycle-breaking, flip-flop minimization, sequential redundancy, design for testability, sequential circuits, retiming, partial scan, strongly connected components, redundant fault
37	Ken Museth	Retiming of fluid simulations for VFX: distributed non-linear fluid retiming by sparse bi-directional advection-diffusion.	SIGGRAPH Talks	2019	DBLP DOI BibTeX RDF
35	Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton	Scalable min-register retiming under timing and initializability constraints.	DAC	2008	DBLP DOI BibTeX RDF	min-area, retiming, initial state, sequential optimization
33	Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang	A 0.18µm CMOS transceiver design for high-speed backplane data communications.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
33	Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman	Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits.	DATE	1999	DBLP DOI BibTeX RDF
33	Rajeev K. Ranjan 0001, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton	Using Combinational Verification for Sequential Circuits.	DATE	1999	DBLP DOI BibTeX RDF
33	Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia	Pseudo-exhaustive built-in TPG for sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
30	Lei Wang 0011, Zhiying Wang 0003, Kui Dai	Performance Bound Analysis and Retiming of Timed Circuits.	ICYCS	2008	DBLP DOI BibTeX RDF
30	Ming Su, Lili Zhou, C.-J. Richard Shi	Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining.	ICCD	2007	DBLP DOI BibTeX RDF
30	Hai Zhou 0001	Deriving a new efficient algorithm for min-period retiming.	ASP-DAC	2005	DBLP DOI BibTeX RDF
30	Chien-Hsun Tseng, Stuart Lawson	Full parallel process for multidimensional wave digital filtering via multidimensional retiming technique.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
30	Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli	Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits.	SBCCI	2003	DBLP DOI BibTeX RDF
30	Aiman H. El-Maleh, Yahya E. Osais	A retiming-based test pattern generator design for built-in self test of data path architectures.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
30	Jason Cong, Sung Kyu Lim, Chang Wu	Performance driven multi-level and multiway partitioning with retiming.	DAC	2000	DBLP DOI BibTeX RDF
30	Jason Cong, Chang Wu	An efficient algorithm for performance-optimal FPGA technology mapping with retiming.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
30	Vinoo Srinivasan, Ranga Vemuri	A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining.	VLSI Design	1998	DBLP DOI BibTeX RDF
30	Dirk Eisenbiegler, Ramayya Kumar, Christian Blumenröhr	A constructive approach towards correctness of synthesis-application within retiming.	ED&TC	1997	DBLP DOI BibTeX RDF
30	G. N. Srinivasa Prasanna	Compilation of Parallel Multimedia Computations - Extending Retiming Theory and Amdahl's Law.	PPoPP	1997	DBLP DOI BibTeX RDF
30	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
30	Balakrishnan Iyer, Maciej J. Ciesielski	Metamorphosis: state assignment by retiming and re-encoding.	ICCAD	1996	DBLP DOI BibTeX RDF	Sequential Logic, Finite State Machine, Logic Synthesis, State Assignment, State Encoding
30	Jason Cong, Chang Wu	An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig.	ICCD	1996	DBLP DOI BibTeX RDF
30	Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
28	Hui Liu 0006, Zili Shao, Meng Wang 0005, Junzhao Du, Chun Jason Xue, Zhiping Jia	Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Periodic dependent tasks, Scheduling, Multimedia, Real-time, Dynamic voltage scaling (DVS), Multi-core, Software pipelining, Retiming
28	Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria	Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	multiphase, sequential circuit, software pipelining, clock, Retiming
28	Ying Yi, Roger F. Woods, Lok-Kee Ting, C. F. N. Cowan	High Speed FPGA-Based Implementations of Delayed-LMS Filters.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	delayed LMS filters, retiming technique, hardware sharing, FPGA, adaptive filtering
28	Hsueh-Chih Yang, Lan-Rong Dung	On multiple-voltage high-level synthesis using algorithmic transformations.	ASP-DAC	2005	DBLP DOI BibTeX RDF	loop shrinking, multiple voltage scheduling, high-level synthesis, retiming, unfolding, low power circuit
28	Qingfeng Zhuge, Bin Xiao 0001, Edwin Hsing-Mean Sha	Code size reduction technique and implementation for software-pipelined DSP applications.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	scheduling, software pipelining, Retiming, DSP processors
28	Qingfeng Zhuge, Zili Shao, Bin Xiao 0001, Edwin Hsing-Mean Sha	Design space minimization with timing and code size optimization for embedded DSP.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	retiming, unfolding, code size reduction, DSP processors
28	Jason Cong	Timing closure based on physical hierarchy.	ISPD	2002	DBLP DOI BibTeX RDF	interconnect planning, logic hierarchy, physical hierarchy, retiming and pipelining, sequential arrival time, interconnect optimization, timing closure, multilevel optimization
28	Bin Xiao 0001, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge	Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops.	ISSS	2002	DBLP DOI BibTeX RDF	rotation scheduling, software pipelining, retiming, unfolding
28	Alain Darte, Guillaume Huard	Complexity of Multi-dimensional Loop Alignment.	STACS	2002	DBLP DOI BibTeX RDF	Complexity, Program Transformation, Retiming, Automatic Parallelization, Loop Optimization
28	Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications.	ICPP	2002	DBLP DOI BibTeX RDF	Scheduling, Software pipelining, Retiming, DSP processors
28	Cagdas Akturan, Margarida F. Jacome	RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors.	CODES	2001	DBLP DOI BibTeX RDF	embedded systems, software pipelining, retiming, optimizing compilers, VLIW processors
28	Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak	Optimizing computations for effective block-processing.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	computation dataflow graphs, scheduling, embedded systems, combinatorial optimization, high-level synthesis, vectorization, integer linear programming, retiming
28	Dominik Stoffel, Wolfgang Kunz	Record & play: a structural fixed point iteration for sequential circuit verification.	ICCAD	1997	DBLP DOI BibTeX RDF	circuit resynthesis, circuit retiming, combinational verification techniques, instruction queue, iterative circuit array, local circuit transformation, sequential circuit verification, sequential logic equivalence checking, structural fixed point iteration, time frame equivalence, logic testing, finite state machine, logic design
28	Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma 0011	A strategy for determining a Jacobi specific dataflow processor.	ASAP	1997	DBLP DOI BibTeX RDF	Jacobi specific dataflow processor, Jacobi algorithms, real-lime adaptive signal processing applications, quasi regularity property, dependence graph representations, exploration iteration, processor template, mapper, hierarchical exploration method, mapping efficiency, lookahead techniques, pipelining, retiming, adaptive signal processing, application domain, array processing
28	Guy Even, Ami Litman	Overcoming chip-to-chip delays and clock skews.	ASAP	1996	DBLP DOI BibTeX RDF	chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews
28	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen	On Verifying the Correctness of Retimed Circuits.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	3-valued equivalence, delay-compensation, sequential ATPG, formal verification, retiming, equivalence-Checking
28	Miodrag Potkonjak	Discrete-relaxation-based heuristic techniques for video algorithm/architecture matching and system level transformations.	ICIP	1995	DBLP DOI BibTeX RDF	discrete-relaxation-based heuristic techniques, video algorithm, system level transformations, computational transformations, throughput performance, iterative heuristic approach, behavioral transformations, rephasing, architecture matching, computational complexity, image processing, VLSI, pipelining, iterative methods, pipeline processing, retiming, integrated circuit design, system level design, video processing, video signal processing, heuristic programming, digital signal processing chips, circuit optimisation, throughput optimization
28	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray	Concurrent timing optimization of latch-based digital systems.	ICCD	1995	DBLP DOI BibTeX RDF	concurrent timing optimization, latch-based digital systems, digital system timing, intentional clock skew, latch-based designed systems, multi-phase clocking, resynchronization, latches insertion, optimisation, timing, logic design, flip-flops, retiming, mixed integer linear program, race conditions, integrated framework, wave pipelining, hazards and race conditions, clock period
28	Carl Ebeling, Brian Lockyear	On the performance of level-clocked circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits
28	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Resynthesis for sequential circuits designed with a specified initial state.	VTS	1995	DBLP DOI BibTeX RDF	specified initial state, retiming method, redundancy removal method, resynthesized circuit, input sequences, logic optimisation, timing, redundancy, sequential circuits, logic CAD, flip-flops, flip-flops, circuit optimisation, synchronous sequential circuits
22	Miao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao	A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology.	ASP-DAC	2005	DBLP DOI BibTeX RDF
22	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Sequential delay budgeting with interconnect prediction.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
22	Ko Yoshikawa, Yasuhiko Hagihara, Keisuke Kanamaru, Yuichi Nakamura 0002, Shigeto Inui, Takeshi Yoshimura	Timing optimization by replacing flip-flops to latches.	ASP-DAC	2004	DBLP DOI BibTeX RDF
22	Aaron P. Hurst, Philip Chong, Andreas Kuehlmann	Physical placement driven by sequential timing analysis.	ICCAD	2004	DBLP DOI BibTeX RDF
22	Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer	A low-power VLSI architecture for turbo decoding.	ISLPED	2003	DBLP DOI BibTeX RDF	MAP decoder, low power architecture, turbo decoding
22	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Delay budgeting in sequential circuit with application on FPGA placement.	DAC	2003	DBLP DOI BibTeX RDF	delay budgeting, FPGA, placement, sequential circuits
22	Karam S. Chatha, Ranga Vemuri	Hardware-software partitioning and pipelined scheduling of transformative applications.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
22	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen	Verifying sequential equivalence using ATPG techniques.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF
22	Enrique San Millán, Luis Entrena, José Alberto Espejo	On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization.	DSD	2001	DBLP DOI BibTeX RDF
22	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III	Integrated parametric timing optimization of digital systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
22	Tracy C. Denk, Keshab K. Parhi	Synthesis of folded pipelined architectures for multirate DSP algorithms.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
22	Ching-Yi Wang, Keshab K. Parhi	High-level DSP synthesis using concurrent transformations, scheduling, and allocation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
22	Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly	Testability Implications of Performance-Driven Logic Synthesis.	IEEE Des. Test Comput.	1995	DBLP DOI BibTeX RDF
22	Hervé J. Touati, Robert K. Brayton	Computing the initial states of retimed circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
18	Gerry Chen, Frank Dellaert, Seth Hutchinson 0001	Generalizing Trajectory Retiming to Quadratic Objective Functions.	CoRR	2023	DBLP DOI BibTeX RDF
18	Khusnul Novianingsih	A Heuristic Approach for Solving Flight Retiming Problems.	SIET	2023	DBLP DOI BibTeX RDF
18	Huimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel	Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
18	Tessa Borgonjon, Broos Maenhout	An exact approach for the personnel task rescheduling problem with task retiming.	Eur. J. Oper. Res.	2022	DBLP DOI BibTeX RDF
18	Siyuan Gao, Shouzhen Gu, Rui Xu 0013, Edwin Hsing-Mean Sha, Qingfeng Zhuge	Performance optimization for parallel systems with shared DWM via retiming, loop scheduling, and data placement.	J. Syst. Archit.	2021	DBLP DOI BibTeX RDF
18	N. L. Venkataraman, Rajagopal Kumar 0001	An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques.	Trans. Emerg. Telecommun. Technol.	2020	DBLP DOI BibTeX RDF
18	Erika Lu, Forrester Cole, Tali Dekel, Weidi Xie, Andrew Zisserman, David Salesin, William T. Freeman, Michael Rubinstein	Layered Neural Rendering for Retiming People in Video.	CoRR	2020	DBLP BibTeX RDF
18	Erika Lu, Forrester Cole, Tali Dekel, Weidi Xie, Andrew Zisserman, David Salesin, William T. Freeman, Michael Rubinstein	Layered neural rendering for retiming people in video.	ACM Trans. Graph.	2020	DBLP DOI BibTeX RDF
18	Ting-Ru Lin, Massoud Pedram	Retiming for High-performance Superconductive Circuits with Register Energy Minimization.	ICCAD	2020	DBLP DOI BibTeX RDF
18	Pramod Patali, Shahana Thottathikkulam Kassim	High throughput FIR filter architectures using retiming and modified CSLA based adders.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
18	Salil Sharma, Jonas Lüßmann, Jaehyun So	Controller Independent Software-in-the-Loop Approach to Evaluate Rule-Based Traffic Signal Retiming Strategy by Utilizing Floating Car Data.	IEEE Trans. Intell. Transp. Syst.	2019	DBLP DOI BibTeX RDF
18	Huimei Cheng, Hsiao-Lun Wang, Minghe Zhang, Dylan Hand, Peter A. Beerel	Automatic Retiming of Two-Phase Latch-Based Resilient Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
18	Haoyun Jiang, Zherui Zhang, Zhengkun Shen, Xiucheng Hao, Zexue Liu, Heyi Li, Yi Tan, Qiang Zhou, Junhua Liu, Huailin Liao	A Calibration-Free Fractional-N ADPLL using Retiming Architecture and a 9-bit 0.3ps-INL Phase Interpolator.	ISCAS	2019	DBLP DOI BibTeX RDF
18	Ravindra Dwivedi, Jon Barry, Sean C. McDuffee	What time is it?: efficient and robust FX retiming workflow for spies in disguise.	SIGGRAPH Talks	2019	DBLP DOI BibTeX RDF
18	Zhengkun Shen, Heyi Li, Haoyun Jiang, Zherui Zhang, Junhua Liu, Huailin Liao	A 12-GHz All-Digital Calibration-Free FMCW Signal Generator Based on a Retiming Fractional Frequency Divider.	A-SSCC	2019	DBLP DOI BibTeX RDF
18	Xue-Yang Zhu	Efficient Retiming of Unfolded Synchronous Dataflow Graphs.	ICECCS	2019	DBLP DOI BibTeX RDF
18	Rolf N. van Lieshout, Judith Mulder, Dennis Huisman	The vehicle rescheduling problem with retiming.	Comput. Oper. Res.	2018	DBLP DOI BibTeX RDF
18	Naveen Kadayinti, Maryam Shojaei Baghini, Dinesh Kumar Sharma	Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
18	Tobias Strauch	Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs.	CoRR	2018	DBLP BibTeX RDF
18	Jalaja S, Vijaya Prakash A. M	Design of Low Power SAR ADC Using Clock Retiming.	ISVLSI	2018	DBLP DOI BibTeX RDF