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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1073 occurrences of 407 keywords
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Results
Found 939 publication records. Showing 939 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | Spyros Tragoudas, Maria K. Michael |
Functional ATPG for Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 16-19, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara |
An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 190-197, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
26 | Aiman H. El-Maleh, Mark Kassab, Janusz Rajski |
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 625-631, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
model checking, verification, guided search |
26 | A. Dargelas, C. Gauthron, Yves Bertrand |
MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 29-36, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda |
The Use of Model Checking in ATPG for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 2nd International Workshop, CAV '90, New Brunswick, NJ, USA, June 18-21, 1990, Proceedings, pp. 86-95, 1990, Springer, 3-540-54477-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
26 | André Ivanov, Vinod K. Agarwal |
Dynamic testability measures for ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(5), pp. 598-608, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
24 | Xiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu |
ECR: a low complexity generalized error cancellation rewiring scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 511-516, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
error cancellation, ATPG, rewire |
24 | Scott Davidson 0001 |
The commonality of vector generation techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(2), pp. 200, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
output compression, non-fault-directed test, semi-fault-directed test, ATPG, test compression, full scan, vector generation, logic BIST |
24 | Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos |
Hybrid-SBST Methodology for Efficient Testing of Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(1), pp. 64-75, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
H-SBST, RTPG, computer architecture, ATPG, functional testing, microprocessor testing, software-based self-test |
24 | Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker 0001 |
Power Droop Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(3), pp. 276-284, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
power droop, signal integrity errors, high-frequency effects, low-frequency effects, ATPG, heuristic method, D-algorithm |
24 | Seongmoon Wang, Wenlong Wei |
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 810-816, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
peak current reduction, average power dissipation, clock tree construction, special scan cells, scan chain reordering, ATPG, scan designs |
24 | Hani Rizk, Christos A. Papachristou, Francis G. Wolff |
A Self Test Program Design Technique for Embedded DSP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(1), pp. 71-87, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
self test programs, pseudorandom BIST, LSFR, DSP, ATPG |
24 | Abhishek Singh 0001, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel |
Defect Simulation Methodology for iDDT Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(3), pp. 255-272, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
iDDT, transient current testing, device testing, ATPG, fault simulation, IDDQ, defect simulation, defect-based test |
24 | Martin Stáva, Ondrej Novák |
Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 251-256, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, VLSI, ATPG, hardware, on-line learning, Backtrace |
24 | Vishnu C. Vimjam, Michael S. Hsiao |
Fast illegal state identification for improving SAT-based induction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 241-246, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
learning, ATPG, SAT, induction |
24 | Scott Davidson 0001 |
Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(6), pp. 565, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
X-tolerant, IC outlier, ATPG, BIST, yield, IDDQ, International Test Conference, test metrics |
24 | Maher N. Mneimneh, Karem A. Sakallah |
Principles of Sequential-Equivalence Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 22(3), pp. 248-257, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
conceptual and algorithmic approache, ATPG, sequential-equivalence checking, satisfiability solvers |
24 | Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara |
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(3), pp. 315-323, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
scan and non-scan, fault efficiency, ATPG |
24 | Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja |
Multiple Faults: Modeling, Simulation and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 592-597, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
ATPG Modeling, Fault Modeling, Multiple Fault |
24 | Hiroyuki Higuchi |
An implication-based method to detect multi-cycle paths in large sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 164-169, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
multi-cycle path, sequential circuits, ATPG, implication |
24 | Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker 0001 |
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(1), pp. 37-51, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
sequential circuit ATPG, single observation time test strategy, multiple observation time test strategy, genetic algorithm, symbolic simulation |
24 | Zhigang Yin, Yinghua Min, Xiaowei Li 0001 |
An Approach to RTL Fault Extraction and Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 219-224, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
ATPG (Automatic Test Pattern Generation), RTL (Register Transfer Level), Fault |
24 | Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya |
Isomorph-Redundancy in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(9), pp. 992-997, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
testing, redundancy, ATPG, DFT, stuck-at faults, sequential machines |
24 | Li-C. Wang, Magdy S. Abadir |
On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 121-130, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
custom circuits, high level circuit extraction, ATPG, DFT, time-to-market |
24 | Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer |
A new framework for static timing analysis, incremental timing refinement, and timing simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 102-107, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation |
24 | Emil Gizdarski, Hideo Fujiwara |
Spirit: satisfiability problem implementation for redundancy identification and test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 171-178, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Boolean satisfiability method, SPIRIT, ATPG system, logic testing, computability, automatic test pattern generation, combinational circuits, combinational circuits, test pattern generation, test sets |
24 | Marie-Lise Flottes, Christian Landrault, A. Petitqueux |
Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 404-, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset |
24 | Tsuyoshi Shinogi, Terumine Hayashi |
A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 164-, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
compact test generation, parallel processing, ATPG, IDDQ testing |
24 | Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen |
On Verifying the Correctness of Retimed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 277-, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
3-valued equivalence, delay-compensation, sequential ATPG, formal verification, retiming, equivalence-Checking |
24 | Antoni Ferré, Joan Figueras |
On estimating bounds of the quiescent current for IDDQ testin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 106-111, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
quiescent current bounds, sensing circuitry design, VLSI, logic testing, integrated circuit testing, ATPG, automatic testing, CMOS integrated circuits, leakage currents, I/sub DDQ/ testing, CMOS ICs, hierarchical approach |
24 | Subhrajit Bhattacharya, Sujit Dey |
H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 74-80, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology |
24 | Marcello Dalpasso, Michele Favalli, Piero Olivo |
Test pattern generation for IDDQ: increasing test quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 304-309, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
ATPG strategy, quiescent power supply current monitoring, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, CMOS logic circuits, I/sub DDQ/ testing |
18 | Pallav Gupta, Rui Zhang, Niraj K. Jha |
Automatic Test Generation for Combinational Threshold Logic Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(8), pp. 1035-1045, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir |
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(9), pp. 1289-1294, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Ho Fai Ko, Nicola Nicolici |
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 2092-2097, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Jiri Jenícek |
Efficient Test Pattern Compression Method Using Hard Fault Preferring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 703-708, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Minjin Zhang, Huawei Li 0001, Xiaowei Li 0001 |
Multiple Coupling Effects Oriented Path Delay Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 383-388, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
crosstalk, delay test, path delay fault |
18 | Shih-Ping Lin 0001, Chung-Len Lee 0001, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu |
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(7), pp. 767-776, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Kunal P. Ganeshpure, Sandip Kundu |
Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 540-545, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel |
Computation and Application of Absolute Dominators in Industrial Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007, pp. 137-144, 2007, IEEE Computer Society, 978-0-7695-2827-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Srivaths Ravi 0001, V. R. Devanathan, Rubin A. Parekhji |
Methodology for low power test pattern generation using activity threshold control logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 526-529, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Nina Amla, Kenneth L. McMillan |
Combining Abstraction Refinement and SAT-Based Model Checking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for the Construction and Analysis of Systems, 13th International Conference, TACAS 2007, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2007 Braga, Portugal, March 24 - April 1, 2007, Proceedings, pp. 405-419, 2007, Springer, 978-3-540-71208-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Jimson Mathew, Hafizur Rahaman 0001, Dhiraj K. Pradhan |
Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 207-208, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell |
Zero Cost Test Point Insertion Technique for Structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 357-363, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram |
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 533-538, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng |
Pseudofunctional testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8), pp. 1535-1546, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Seongmoon Wang, Srimat T. Chakradhar |
A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8), pp. 1555-1564, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina |
Testability Estimation Based on Controllability and Observability Parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 504-514, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito |
Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 136-144, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Yu Huang 0005 |
On N-Detect Pattern Set Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 445-450, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Shweta Chary, Michael L. Bushnell |
Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 413-418, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya |
An Efficient Scan Tree Design for Compact Test Pattern Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 175-180, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey |
Optimized reseeding by seed ordering and encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2), pp. 264-270, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Ahmad A. Al-Yamani, Edward J. McCluskey |
Test chip experimental results on high-level structural test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(4), pp. 690-701, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
test experiment, Structural test, VLSI test, complex gates |
18 | Bhushan Vaidya, Mehdi Baradaran Tahoori |
Delay Test Generation with All Reachable Output Propagation and Multiple Excitations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 380-388, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Nisar Ahmed, Mohammad Tehranipoor |
Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 187-198, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey |
Effective TARO Pattern Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 161-166, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Loganathan Lingappan, Niraj K. Jha |
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 418-423, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici |
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7), pp. 1142-1153, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Octavian Petre, Hans G. Kerkhoff |
Scan Test Strategy for Asynchronous-Synchronous Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(6), pp. 639-645, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
globally asynchronous locally synchronous (GALS), asynchronous synchronous interface, synchronizers, scan test |
18 | Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew |
Understanding Yield Losses in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 21(3), pp. 208-215, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Feng Shi 0010, Yiorgos Makris |
SPIN-TEST: automatic test pattern generation for speed-independent circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 903-908, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Pallav Gupta, Rui Zhang, Niraj K. Jha |
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 540-543, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli |
At-Speed Functional Verification of Programmable Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 386-394, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Davide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre |
Yield Analysis of Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 103-108, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | C. V. Krishna, Nur A. Touba |
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 79-86, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai |
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 916-925, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Stephen Pateras |
Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1413, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Manan Syal, Michael S. Hsiao, Sreejit Chakravarty |
Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1034-1043, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Alfred L. Crouch, John C. Potter, Jason Doege |
AC Scan Path Selection for Physical Debugging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 20(5), pp. 34-40, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger |
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 345-350, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Ahmad A. Al-Yamani, Edward J. McCluskey |
Built-In Reseeding for Serial Bist. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 63-68, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Seongmoon Wang, Srimat T. Chakradhar |
A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 574-583, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski |
Impact of Multiple-Detect Test Patterns on Product Quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1031-1040, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante |
A New Functional Fault Model for FPGA Application-Oriented Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 372-380, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | M. Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs |
Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 181-186, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich |
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 3-8, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Microprocessor, Delay Testing |
18 | Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra |
Program Slicing for Hierarchical Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 237-246, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Indradeep Ghosh, Masahiro Fujita |
Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3), pp. 402-415, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Andreas G. Veneris, Magdy S. Abadir, Ivor Ting |
Design rewiring based on diagnosis techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 479-484, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater |
A SmartBIST Variant with Guaranteed Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 325-, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri |
Timing Verification and Delay Test Generation for Hierarchical Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 157-162, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao |
Testing, Verification, and Diagnosis in the Presence of Unknowns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 263-270, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Indradeep Ghosh, Masahiro Fujita |
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 43-48, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici |
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 747-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara |
A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 5-12, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Sujit Dey, Anand Raghunathan, Kenneth D. Wagner |
Design for Testability Techniques at the Behavioral and Register-Transfer Levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(2), pp. 79-91, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability |
18 | Li-C. Wang, Magdy S. Abadir |
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(2), pp. 121-135, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
high-level test generation, assertion test generation, design validation, logic verification, symbolic trajectory evaluation |
18 | Shing-Wu Tung, Jing-Yang Jou |
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 402-407, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Michael L. Bushnell, John Giraldi |
A Functional Decomposition Method for Redundancy Identification and Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 10(3), pp. 175-195, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
redundancy identification, logic testing, automatic test generation, backtracing |
18 | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda |
New static compaction techniques of test sequences for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 37-43, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer |
High Quality Robust Tests for Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 88-93, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
test generation, fault modeling, delay test, robust test |
18 | Uwe Gläser, Heinrich Theodor Vierhaus |
Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4), pp. 410-423, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Kwang-Ting Cheng |
Gate-level test generation for sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(4), pp. 405-442, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
testing, automatic test generation, IC testing, sequential circuit test generation |
18 | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda |
Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPSN ![In: Parallel Problem Solving from Nature - PPSN IV, International Conference on Evolutionary Computation. The 4th International Conference on Parallel Problem Solving from Nature, Berlin, Germany, September 22-26, 1996, Proceedings, pp. 792-800, 1996, Springer, 3-540-61723-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin |
Redundancy Identification Using Transitive Closure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 4-9, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel |
Enhancing high-level control-flow for improved testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 322-328, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description |
18 | Kee Sup Kim, Charles R. Kime |
Partial scan flip-flop selection by use of empirical testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(1-2), pp. 47-59, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
scan flip-flop selection, serial scan, design for testability, testability, partial scan |
18 | Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal |
Toward massively parallel automatic test generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9), pp. 981-994, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
18 | Torsten Grüning, Udo Mahlstedt, Wilfried Daehn, Cengiz Özcan |
Accelerated test pattern generation by cone-oriented circuit partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 418-421, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
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