Search results for "clocks"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	Jean-Michel Hélary, Achour Mostéfaoui, Michel Raynal	Virtual Precedence in Asynchronous Systems: Cencept and Applications.	WDAG	1997	DBLP DOI BibTeX RDF	Virtual Precedence, Check-pointing, Causality, Partial Order, Logical Clocks
24	Miroslav Svéda	Embedded system design: a case study.	ECBS	1996	DBLP DOI BibTeX RDF	pumps, embedded distributed systems, dispenser control, local time concept, system-wide global clock, environment specification, system functional specification, logical structure description, petrol pumping station, explosion danger, uncontrolled petrol flow, real-time systems, formal specification, prototyping, distributed processing, controller, implementation, systems analysis, synchronisation, flow control, safety critical system, clocks, distributed control, software prototyping, safety-critical software, embedded system design, counter, control system CAD
24	Krishna B. Rajan, David E. Long, Miron Abramovici	Increasing testability by clock transformation (getting rid of those darn states).	VTS	1996	DBLP DOI BibTeX RDF	clock transformation, sequential test generation, darn states, easy-to-reach states, logic testing, partitioning, design for testability, sequential circuits, DFT, fault coverage, testability, flip-flops, flip-flops, clocks, logic partitioning
24	Ching-Farn Eric Wu, Yew-Huey Liu, Yarsun Hsu	Timestamp consistency and trace-driven analysis for distributed parallel systems.	IPPS	1995	DBLP DOI BibTeX RDF	IBM computers, timestamp consistency, trace-driven analysis, distributed parallel systems, continuous event data stream, parallel program execution progress, separate streams, logical event order, local clock discrepancy, performance analysis techniques, IBM SPn systems, system events, minimal trace overhead, trace-driven analysis tools, NAS kernel benchmarks, performance evaluation, parallel processing, message passing, message passing, timing, parallel machines, clocks, system monitoring, integrated approach, multiple processors
24	Luis F. G. Sarmenta, Gill A. Pratt, Stephen A. Ward	Rational clocking [digital systems design].	ICCD	1995	DBLP DOI BibTeX RDF	rational clocking, independently-clocked digital subsystems, finite probability, phase relationship, delays, delays, logic design, logic design, synchronisation, clocks, minimisation of switching nets, digital systems design, synchronization failure
24	Carl Ebeling, Brian Lockyear	On the performance of level-clocked circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits
24	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews	High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips.	ARVLSI	1995	DBLP DOI BibTeX RDF	counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television
24	Martin De Wulf, Laurent Doyen 0001, Nicolas Markey, Jean-François Raskin	Robust safety of timed automata.	Formal Methods Syst. Des.	2008	DBLP DOI BibTeX RDF	Robustness, Implementability, Perturbation, Timed automaton, Drift
24	Virginia Papailiopoulou, Laya Madani, Lydie du Bousquet, Ioannis Parissis	Extending Structural Test Coverage Criteria for Lustre Programs with Multi-clock Operators.	FMICS	2008	DBLP DOI BibTeX RDF
24	Zhang Fu, Marina Papatriantafilou, Philippas Tsigas	Mitigating Distributed Denial of Service Attacks in Multiparty Applications in the Presence of Clock Drifts.	SRDS	2008	DBLP DOI BibTeX RDF
24	Marcel Busse, Thilo Streichert	Time Synchronization.	Algorithms for Sensor and Ad Hoc Networks	2007	DBLP DOI BibTeX RDF
24	Adib Allahham, Hassane Alla	Monitoring of a Class of Timed Discrete Events Systems.	ICRA	2007	DBLP DOI BibTeX RDF
24	Dana Fisman	On the Characterization of Until as a Fixed Point Under Clocked Semantics.	Haifa Verification Conference	2007	DBLP DOI BibTeX RDF
24	Veerapaneni Nagbhushan, C. Y. Roger Chen	Algorithms to simplify multi-clock/edge timing constraints.	ICCD	2007	DBLP DOI BibTeX RDF
24	Emmanuelle Anceaume, Carole Delporte-Gallet, Hugues Fauconnier, Michel Hurfin, Josef Widder	Clock Synchronization in the Byzantine-Recovery Failure Model.	OPODIS	2007	DBLP DOI BibTeX RDF
24	Malolan Chetlur, Philip A. Wilsey	Causality and Proactive Cancellation.	DS-RT	2006	DBLP DOI BibTeX RDF
24	Jeanette Tsang, Konstantin Beznosov	A Security Analysis of the Precise Time Protocol (Short Paper).	ICICS	2006	DBLP DOI BibTeX RDF	IEEE 1588, Precise Time Protocol, Network Time Protocol, time synchronization, security analysis
24	Giacomo Bucci, Luigi Sassoli, Enrico Vicario	Correctness Verification and Performance Analysis of Real-Time Systems Using Stochastic Preemptive Time Petri Nets.	IEEE Trans. Software Eng.	2005	DBLP DOI BibTeX RDF	performance and dependability evaluation, maximal step semantics, well definedness, stochastic preemptive Time Petri nets, preemptive scheduling, discrete time, confusion, Real-time reactive systems, correctness verification
24	André Günther, Christian Hoene	Measuring Round Trip Times to Determine the Distance Between WLAN Nodes.	NETWORKING	2005	DBLP DOI BibTeX RDF
24	Rajeev Alur, Salvatore La Torre, P. Madhusudan	Perturbed Timed Automata.	HSCC	2005	DBLP DOI BibTeX RDF
24	Anurag Agarwal, Vijay K. Garg	Efficient dependency tracking for relevant events in shared-memory systems.	PODC	2005	DBLP DOI BibTeX RDF	shared-memory, vector clock, predicate detection
24	Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy 0001	Energy recovery clocked dynamic logic.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	logic, clock, domino, energy recovery
24	Satoshi Kawanami, Takeshi Nishimura, Tomoya Enokido, Makoto Takizawa 0001	A Scalable Group Communication Protocol with Global Clock.	AINA	2005	DBLP DOI BibTeX RDF
24	Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida	Skew measurements in clock distribution circuits using an analytic signal method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
24	Parosh Aziz Abdulla, Johann Deneux, Pritha Mahata	Multi-Clock Timed Networks.	LICS	2004	DBLP DOI BibTeX RDF
24	Jean-Michel Hélary, Michel Raynal, Giovanna Melideo, Roberto Baldoni	Efficient Causality-Tracking Timestamping.	IEEE Trans. Knowl. Data Eng.	2003	DBLP DOI BibTeX RDF	message-passing, causality, timestamp, vector clock, Asynchronous distributed computation
24	An-Swol Hu, Sergio D. Servetto	Asymptotically optimal time synchronization in dense sensor networks.	Wireless Sensor Networks and Applications	2003	DBLP DOI BibTeX RDF
24	Saurabh Ganeriwal, Ram Kumar 0001, Mani B. Srivastava	Timing-sync protocol for sensor networks.	SenSys	2003	DBLP DOI BibTeX RDF	sensor networks, medium access control, time synchronization, packet delay, clock drift
24	Kai-Steffen Hielscher, Reinhard German	A Low-Cost Infrastructure for High Precision High Volume Performance Measurements of Web Clusters.	Computer Performance Evaluation / TOOLS	2003	DBLP DOI BibTeX RDF
24	Murali Kudlugi, Russell Tessier	Static scheduling of multidomain circuits for fast functional verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
24	Maria Sorea	A Decidable Fixpoint Logic for Time-Outs.	CONCUR	2002	DBLP DOI BibTeX RDF
24	Minsoo Ryu, Jungkeun Park, Seongsoo Hong	Timing Constraint Remapping to Achieve Time Equi-Continuity in Distributed Real-Time Systems.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	timing constraint transformation, real-time scheduling, clock synchronization, Distributed real-time system
24	Dongyao Ji, Yuming Wang	Comments on "An approach to the formal verification of the two-party cryptographic protocols" by Zhang, Li and Xiao.	ACM SIGOPS Oper. Syst. Rev.	2001	DBLP DOI BibTeX RDF
24	Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida	Testing clock distribution circuits using an analytic signal method.	ITC	2001	DBLP DOI BibTeX RDF
24	Mingfu Li, Hsin-Min Peng, Chia-Shu Liao	Fast Computation of Time Deviation and Modified Allan Deviation for Telecommunications Clock Stability Characterization.	ISPAN	2000	DBLP DOI BibTeX RDF
24	Vern Paxson	On Calibrating Measurements of Packet Transit Times.	SIGMETRICS	1998	DBLP DOI BibTeX RDF
24	Johan Bengtsson, Bengt Jonsson 0001, Johan Lilius, Wang Yi 0001	Partial Order Reductions for Timed Systems.	CONCUR	1998	DBLP DOI BibTeX RDF
24	Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal	Improving Circuit Testability by Clock Control.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
24	Farn Wang, Aloysius K. Mok, E. Allen Emerson	Symbolic Model Checking for Distributed Real-Time Systems.	FME	1993	DBLP DOI BibTeX RDF
24	Hagit Attiya	Implementing FIFO Queus and Stacks (Extended Abstract).	WDAG	1991	DBLP DOI BibTeX RDF
24	T. K. Srikanth, Sam Toueg	Optimal clock synchronization.	J. ACM	1987	DBLP DOI BibTeX RDF
24	Darryl Veitch, Julien Ridoux, Satish Babu Korada	Robust synchronization of absolute and difference clocks over networks.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	TSC, software clock, synchronization, timing, GPS, network measurement, round-trip time, NTP
24	Jinkyu Koo, Rajesh Krishna Panta, Saurabh Bagchi, Luis Antonio Montestruque	A tale of two synchronizing clocks.	SenSys	2009	DBLP DOI BibTeX RDF	low duty cycle, synchronization, sensor
24	Isamu Tsuneizumi, Ailixier Aikebaier, Tomoya Enokido, Makoto Takizawa 0001	A flexible group communication protocol with hybrid clocks.	MoMM	2009	DBLP DOI BibTeX RDF
24	Taolue Chen, Jian Lu 0001	Towards the Complexity of Controls for Timed Automata with a Small Number of Clocks.	FSKD (5)	2008	DBLP DOI BibTeX RDF
24	Ales Smrcka, Vojtech Rehák, Tomás Vojnar, David Safránek, Petr Matousek, Z. Rehák	Verifying VHDL Designs with Multiple Clocks in SMV.	FMICS/PDMC	2006	DBLP DOI BibTeX RDF
24	Shengyong Chen, Chunyan Yao, Gang Xiao 0001, Y. S. Ying, Wanliang Wang	Fault Detection and Prediction of Clocks and Timers Based on Computer Audition and Probabilistic Neural Networks.	IWANN	2005	DBLP DOI BibTeX RDF
24	Roberto Gómez Cárdenas, Jorge Herrerías Guerrero, Erika Mata Sanchez	Using Lamport's Logical Clocks to Consolidate Log Files from Different Sources.	IICS	2005	DBLP DOI BibTeX RDF
24	François Laroussinie, Nicolas Markey, Philippe Schnoebelen	Model Checking Timed Automata with One or Two Clocks.	CONCUR	2004	DBLP DOI BibTeX RDF
24	Jo C. Ebergen	Circuits Without Clocks: What Makes Them Tick?	OPODIS	2003	DBLP DOI BibTeX RDF
24	Geralyn Abinader, Joey Stein, Molly Lenore	Moving clocks and bending space: a learning/interactive museum environment (LIME).	SIGGRAPH Educators Program	2003	DBLP DOI BibTeX RDF
24	Javier Miranda, Michael González Harbour	A Proposal to Integrate the POSIX Execution-Time Clocks into Ada 95.	Ada-Europe	2003	DBLP DOI BibTeX RDF	Scheduling, Execution-Time, Ada 95, Hard Real-Time, GNAT
24	Szilvia Gyapay, Reiko Heckel, Dániel Varró	Graph Transformation with Time: Causality and Logical Clocks.	ICGT	2002	DBLP DOI BibTeX RDF
24	Zhe Dang	Binary Reachability Analysis of Pushdown Timed Automata with Dense Clocks.	CAV	2001	DBLP DOI BibTeX RDF
24	Sarmistha Neogy, Anupam Sinha, Pradip Kumar Das	Checkpoint Processing in Distributed Systems Software Using Synchronized Clocks.	ITCC	2001	DBLP DOI BibTeX RDF
24	Mehrdad Nourani, Joan Carletta, Christos A. Papachristou	Synthesis-for-testability of controller-datapath pairs that use gated clocks.	DAC	2000	DBLP DOI BibTeX RDF
24	Jacob Savir	On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF
24	Rance Cleaveland, Gerald Lüttgen, Michael Mendler	An Algebraic Theory of Multiple Clocks.	CONCUR	1997	DBLP DOI BibTeX RDF
24	Glenn Jennings, Esther Jennings	A discrete syntax for level-sensitive latched circuits having n clocks and m phases.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
24	Thomas A. Henzinger, Peter W. Kopke, Howard Wong-Toi	The Expressive Power of Clocks.	ICALP	1995	DBLP DOI BibTeX RDF
24	Atul Adya, Robert Gruber, Barbara Liskov, Umesh Maheshwari	Efficient Optimistic Concurrency Control Using Loosely Synchronized Clocks.	SIGMOD Conference	1995	DBLP DOI BibTeX RDF
24	Peter B. Danzig, Stephen W. Melvin	High Resolution Timing with Low Resolution Clocks and A Microsecond Resolution Timer for Sun Workstations.	ACM SIGOPS Oper. Syst. Rev.	1990	DBLP DOI BibTeX RDF
24	Bernadette Charron-Bost	Concerning the Size of Clocks.	Semantics of Systems of Concurrent Processes	1990	DBLP DOI BibTeX RDF
24	Barbara Liskov, Liuba Shrira, John Wroclawski	Efficient At-Most-Once Messages Based on Synchronized Clocks.	SIGCOMM	1990	DBLP DOI BibTeX RDF
24	Leslie Lamport, P. M. Melliar-Smith	Synchronizing Clocks in the Presence of Faults	J. ACM	1985	DBLP DOI BibTeX RDF
16	Thomas Schmid 0002, Dustin Torres, Mani B. Srivastava	Low-power high-precision timing hardware for sensor networks.	SenSys	2009	DBLP DOI BibTeX RDF	HLTimer, clocks, time synchronization
16	Arnd Hartmanns, Holger Hermanns	A Modest Approach to Checking Probabilistic Timed Automata.	QEST	2009	DBLP DOI BibTeX RDF	Probabilistic timed automata, model checking, compositional modelling, digital clocks
16	Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay	Slew-aware clock tree design for reliable subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	slew, clocks, subthreshold
16	Piotr Zielinski	Low-latency atomic broadcast in the presence of contention.	Distributed Comput.	2008	DBLP DOI BibTeX RDF	Generic Broadcast, Synchronized clocks, Fault-tolerance, Atomic Broadcast
16	Thomas Schmid 0002, Zainul Charbiwala, Jonathan Friedman, Young H. Cho, Mani B. Srivastava	Exploiting manufacturing variations for compensating environment-induced clock drift in time synchronization.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	emulation, clocks, time synchronization, oscillator
16	Franco Cicirelli, Angelo Furfaro, Libero Nigro	Distributed simulation of modular time Petri nets: An approach and a case study exploiting temporal uncertainty.	Real Time Syst.	2007	DBLP DOI BibTeX RDF	Temporal uncertainty, Time interval based event delivery, Modelling complex real-time systems, Modularity constructs, Petri Net Markup Language, Distributed simulation, Time Petri nets, Time warp, Temporal analysis, Logical clocks
16	Vijay K. Garg, Chakarat Skawratananond, Neeraj Mittal	Timestamping messages and events in a distributed system using synchronous communication.	Distributed Comput.	2007	DBLP DOI BibTeX RDF	Timestamping messages and events, Edge decomposition, Vertex cover, Synchronous communication, Vector clocks
16	Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux	A Survey and Taxonomy of GALS Design Styles.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	globally asynchronous, locally synchronous (GALS), clock domains, pausible clocks, loosely synchronous, synchronization, asynchronous
16	Anand Rajaram, David Z. Pan	Variation tolerant buffered clock network synthesis with cross links.	ISPD	2006	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
16	Philippe Charles, Christian Grothoff, Vijay A. Saraswat, Christopher Donawa, Allan Kielstra, Kemal Ebcioglu, Christoph von Praun, Vivek Sarkar	X10: an object-oriented approach to non-uniform cluster computing.	OOPSLA	2005	DBLP DOI BibTeX RDF	atomic blocks, non-uniform cluster computing (NUCC), partitioned global address space (PGAS), Java, scalability, multithreading, productivity, clocks, data distribution, places, X10
16	Anand Rajaram, David Z. Pan, Jiang Hu	Improved algorithms for link-based non-tree clock networks for skew variability reduction.	ISPD	2005	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
16	Attila Pásztor, Darryl Veitch	PC based precision timing without GPS.	SIGMETRICS	2002	DBLP DOI BibTeX RDF	pc clocks, software clock, synchronization, timing, GPS, network measurement, NTP
16	Johann Großschädl	The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip.	ACSAC	2000	DBLP DOI BibTeX RDF	RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency
16	Kim Guldstrand Larsen, Bernhard Steffen, Carsten Weise	Continuous Modeling of Real-Time and Hybrid Systems: From Concepts to Tools.	Int. J. Softw. Tools Technol. Transf.	1997	DBLP DOI BibTeX RDF	Continuous time modeling, Timed automata-based modeling, Drifting clocks, Formal methods, Hybrid systems, Discrete time modeling
16	Allen E. Sjogren, Chris J. Myers	Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline.	ARVLSI	1997	DBLP DOI BibTeX RDF	Mixed synchronous/asynchronous interfacing, stoppable clocks, high-speed pipelines, globally synchronous locally asynchronous, metastability, synchronization failure
16	Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh	Efficient Testing of Clock Regenerator Circuits in Scan Designs.	DAC	1997	DBLP DOI BibTeX RDF	clock regenerators, fault simulation, test pattern generation, clocks, microprocessor testing
16	Nevin Heintze, J. D. Tygar	A Model for Secure Protocols and Their Compositions.	IEEE Trans. Software Eng.	1996	DBLP DOI BibTeX RDF	logic of authentication, protocols-composition of, security, model, model checking, communication, Authentication, formal methods, cryptography, protocols, composition, time, computer security, clocks, protocol analysis, protocol analysis, timed models
16	Massoud Pedram	Power minimization in IC design: principles and applications.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	adiabatic circuits, dynamic power dissipation, low power layout, low power synthesis, lower-power design, power analysis and estimation, power minimization and management, silicon-on-insulator technology, switched capacitance, synthesis, system design, power management, layout, probabilistic analysis, symbolic simulation, CMOS circuits, switching activity, statistical sampling, computer-aided design of VLSI, gated clocks, energy-delay product
16	Chuchang Liu, Mehmet A. Orgun	Executing specifications of distributed computations with Chronolog(MC).	SAC	1996	DBLP DOI BibTeX RDF	simulation, distributed computations, logic programming, temporal logic, clocks, executable specification
16	Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli	Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification.	ISSS	1996	DBLP DOI BibTeX RDF	low power, High level synthesis, finite state machines, gated clocks
16	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
16	Samit Chaudhuri, Stephen A. Blythe, Robert A. Walker 0001	An exact methodology for scheduling in a 3D design space.	ISSS	1995	DBLP DOI BibTeX RDF	2D design space, 3D design space, 3D scheduling problem, Voyager design space exploration system, candidate clock lengths, clock length, globally optimal solution, schedule length, three dimensional scheduling, three-dimensional design space, two dimensional design space, scheduling, optimisation, high level synthesis, search problems, clocks, tight bounds, network synthesis, search space pruning
16	Hong Hao, Kanti Bhabuthmal	Clock controller design in SuperSPARC II microprocessor.	ICCD	1995	DBLP DOI BibTeX RDF	SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller
16	Gill A. Pratt, John Nguyen	Distributed synchronous clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	distributed synchronous clocking, hardware clock, synchronous processor, distributed error correction algorithm, global phase alignment, mode lock, k-ary Cartesian meshes, scalability, graph theory, timing, synchronisation, error correction, clocks, phase locked loops, digital systems, clock signals
16	Kei-Yong Khoo, Alan N. Willson Jr.	Single-transistor transparent-latch clocking.	ARVLSI	1995	DBLP DOI BibTeX RDF	transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits
16	Hao Zheng, Kewal K. Saluja, Rajiv Jain	Test application time reduction for scan based sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	scan based sequential circuits, single clock configuration, nonscan flip-flops, test vector length, nonatomic two-clock scan method, test generation environment, logic testing, sequential circuits, flip-flops, clocks, partial scan, boundary scan testing, test application time
16	Steve Brown, Germán Gutiérrez, Reed Nelson, Chris VanKrevelen	A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers.	VTS	1995	DBLP DOI BibTeX RDF	emitter-coupled logic, triple channel ATE controller, timing verniers, precision edge timing, drive waveforms, returning signals, system clock frequency, ECL, 500 MHz, 40 ps, timing, clocks, automatic test equipment, logic arrays, programmable controllers, gate array, high speed testing
16	Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Functional clock schedule optimization.	VLSI Design	1995	DBLP DOI BibTeX RDF	clock schedule optimization, time frames, level-sensitive sequential circuits, scheduling, delays, delays, timing, sequential circuits, flip-flops, clocks, circuit optimisation, latches, false paths
16	William L. Bradley, Ranga Vemuri	Transformations for functional verification of synthesized designs.	VLSI Design	1995	DBLP DOI BibTeX RDF	low-level functional verification, synthesized designs, clocking mechanisms, provably equivalent model, hierarchical network of modules, reduced state set, de-phase transform, align transform, algorithm, formal verification, transforms, transforms, logic CAD, clocks, hierarchical system, reachable states
16	Vernon L. Chi	Salphasic Distribution of Clock Signals for Synchronous Systems.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	transmission line theory, loaded transmission line, printed circuit board clock planes, clock plane, phase skew, salphasic clock, synchronisation, clocks, distribution network, clock skews, synchronous systems, synchronous system, propagation delay, system clock, phase shifts, clock signals, clock signal
16	Alan Olson, Kang G. Shin	Fault-Tolerant Clock Synchronization in Large Multicomputer Systems.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	fault-tolerant clock synchronization, large multicomputer systems, clock value, maximum skew, maximum time, fault tolerance, reliability, fault tolerant computing, multiprocessing systems, synchronisation, clocks, clock skew, clock drift, synchronization algorithm
16	Marina Papatriantafilou, Philippas Tsigas	On Self-Stabilizing Wait-Free Clock Synchronization.	SWAT	1994	DBLP DOI BibTeX RDF	PRAM computation model, Fault tolerance, Concurrency, Distributed Computing, Synchronization, Self-Stabilization, Synchronous Systems, Wait-Free Synchronization, Digital Clocks
16	Ahmed El-Amawy	Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	constant skew bound, arbitrarily large computing structures, communicating cells, skew upper bound, maximum clocking rate, 2-D mesh framework, node design, nonplanar structures, parallel architectures, stability, hypercubes, network topology, synchronisation, hypercube networks, clocks, clock skew, global synchronization
16	Jacob Savir, William H. McAnney	Random Pattern Testability of Delay Faults.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	combinational logic networks, logic testing, delay faults, combinatorial circuits, latches, random pattern testability, system clocks
16	Nohbyung Park, Alice C. Parker	Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	maximum execution overlap, high-speed digital systems, performance evaluation, data dependencies, clocking, clocks, digital systems, branching, resource conflicts