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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1250 occurrences of 725 keywords
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Results
Found 1399 publication records. Showing 1399 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
24 | Jean-Michel Hélary, Achour Mostéfaoui, Michel Raynal |
Virtual Precedence in Asynchronous Systems: Cencept and Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WDAG ![In: Distributed Algorithms, 11th International Workshop, WDAG '97, Saarbrücken, Germany, September 24-26, 1997, Proceedings, pp. 170-184, 1997, Springer, 3-540-63575-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Virtual Precedence, Check-pointing, Causality, Partial Order, Logical Clocks |
24 | Miroslav Svéda |
Embedded system design: a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), March 11-15, 1996, Friedrichshafen, Germany., pp. 260-, 1996, IEEE Computer Society, 0-8186-7355-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
pumps, embedded distributed systems, dispenser control, local time concept, system-wide global clock, environment specification, system functional specification, logical structure description, petrol pumping station, explosion danger, uncontrolled petrol flow, real-time systems, formal specification, prototyping, distributed processing, controller, implementation, systems analysis, synchronisation, flow control, safety critical system, clocks, distributed control, software prototyping, safety-critical software, embedded system design, counter, control system CAD |
24 | Krishna B. Rajan, David E. Long, Miron Abramovici |
Increasing testability by clock transformation (getting rid of those darn states). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 224-230, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
clock transformation, sequential test generation, darn states, easy-to-reach states, logic testing, partitioning, design for testability, sequential circuits, DFT, fault coverage, testability, flip-flops, flip-flops, clocks, logic partitioning |
24 | Ching-Farn Eric Wu, Yew-Huey Liu, Yarsun Hsu |
Timestamp consistency and trace-driven analysis for distributed parallel systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 680-686, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
IBM computers, timestamp consistency, trace-driven analysis, distributed parallel systems, continuous event data stream, parallel program execution progress, separate streams, logical event order, local clock discrepancy, performance analysis techniques, IBM SPn systems, system events, minimal trace overhead, trace-driven analysis tools, NAS kernel benchmarks, performance evaluation, parallel processing, message passing, message passing, timing, parallel machines, clocks, system monitoring, integrated approach, multiple processors |
24 | Luis F. G. Sarmenta, Gill A. Pratt, Stephen A. Ward |
Rational clocking [digital systems design]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 271-278, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
rational clocking, independently-clocked digital subsystems, finite probability, phase relationship, delays, delays, logic design, logic design, synchronisation, clocks, minimisation of switching nets, digital systems design, synchronization failure |
24 | Carl Ebeling, Brian Lockyear |
On the performance of level-clocked circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 342-357, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits |
24 | Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews |
High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 91-107, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
counterflow-clocked pipelining, HDTV subband vector quantizer chips, clock skew problems, back-propagating clock signals, high speed clocks, dynamic latches, composition rules, two-dimensional data-flow, image compression chip set, subband VQ, VLSI, timing, image coding, pipeline processing, digital signal processing chips, vector quantisation, telecommunication computing, clock distribution, VLSI chips, high definition television |
24 | Martin De Wulf, Laurent Doyen 0001, Nicolas Markey, Jean-François Raskin |
Robust safety of timed automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 33(1-3), pp. 45-84, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Robustness, Implementability, Perturbation, Timed automaton, Drift |
24 | Virginia Papailiopoulou, Laya Madani, Lydie du Bousquet, Ioannis Parissis |
Extending Structural Test Coverage Criteria for Lustre Programs with Multi-clock Operators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMICS ![In: Formal Methods for Industrial Critical Systems, 13th International Workshop, FMICS 2008, L'Aquila, Italy, September 15-16, 2008, Revised Selected Papers, pp. 23-36, 2008, Springer, 978-3-642-03239-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Zhang Fu, Marina Papatriantafilou, Philippas Tsigas |
Mitigating Distributed Denial of Service Attacks in Multiparty Applications in the Presence of Clock Drifts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SRDS ![In: 27th IEEE Symposium on Reliable Distributed Systems (SRDS 2008), Napoli, Italy, October 6-8, 2008, pp. 63-72, 2008, IEEE Computer Society, 978-0-7695-3410-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Marcel Busse, Thilo Streichert |
Time Synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithms for Sensor and Ad Hoc Networks ![In: Algorithms for Sensor and Ad Hoc Networks, Advanced Lectures [result from a Dagstuhl seminar]., pp. 359-380, 2007, Springer, 978-3-540-74990-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Adib Allahham, Hassane Alla |
Monitoring of a Class of Timed Discrete Events Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICRA ![In: 2007 IEEE International Conference on Robotics and Automation, ICRA 2007, 10-14 April 2007, Roma, Italy, pp. 1003-1008, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Dana Fisman |
On the Characterization of Until as a Fixed Point Under Clocked Semantics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 19-33, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Veerapaneni Nagbhushan, C. Y. Roger Chen |
Algorithms to simplify multi-clock/edge timing constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 444-449, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Emmanuelle Anceaume, Carole Delporte-Gallet, Hugues Fauconnier, Michel Hurfin, Josef Widder |
Clock Synchronization in the Byzantine-Recovery Failure Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: Principles of Distributed Systems, 11th International Conference, OPODIS 2007, Guadeloupe, French West Indies, December 17-20, 2007. Proceedings, pp. 90-104, 2007, Springer, 978-3-540-77095-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Malolan Chetlur, Philip A. Wilsey |
Causality and Proactive Cancellation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DS-RT ![In: 10th IEEE International Symposium on Distributed Simulation and Real-Time Applications (DS-RT 2006), 2-4 October 2006, Malaga, Spain, pp. 193-200, 2006, IEEE Computer Society, 0-7695-2697-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Jeanette Tsang, Konstantin Beznosov |
A Security Analysis of the Precise Time Protocol (Short Paper). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICS ![In: Information and Communications Security, 8th International Conference, ICICS 2006, Raleigh, NC, USA, December 4-7, 2006, Proceedings, pp. 50-59, 2006, Springer, 3-540-49496-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
IEEE 1588, Precise Time Protocol, Network Time Protocol, time synchronization, security analysis |
24 | Giacomo Bucci, Luigi Sassoli, Enrico Vicario |
Correctness Verification and Performance Analysis of Real-Time Systems Using Stochastic Preemptive Time Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 31(11), pp. 913-927, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
performance and dependability evaluation, maximal step semantics, well definedness, stochastic preemptive Time Petri nets, preemptive scheduling, discrete time, confusion, Real-time reactive systems, correctness verification |
24 | André Günther, Christian Hoene |
Measuring Round Trip Times to Determine the Distance Between WLAN Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NETWORKING ![In: NETWORKING 2005: Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; Mobile and Wireless Communication Systems, 4th International IFIP-TC6 Networking Conference, Waterloo, Canada, May 2-6, 2005, Proceedings, pp. 768-779, 2005, Springer, 3-540-25809-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Rajeev Alur, Salvatore La Torre, P. Madhusudan |
Perturbed Timed Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HSCC ![In: Hybrid Systems: Computation and Control, 8th International Workshop, HSCC 2005, Zurich, Switzerland, March 9-11, 2005, Proceedings, pp. 70-85, 2005, Springer, 3-540-25108-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Anurag Agarwal, Vijay K. Garg |
Efficient dependency tracking for relevant events in shared-memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the Twenty-Fourth Annual ACM Symposium on Principles of Distributed Computing, PODC 2005, Las Vegas, NV, USA, July 17-20, 2005, pp. 19-28, 2005, ACM, 1-58113-994-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
shared-memory, vector clock, predicate detection |
24 | Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy 0001 |
Energy recovery clocked dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 468-471, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
logic, clock, domino, energy recovery |
24 | Satoshi Kawanami, Takeshi Nishimura, Tomoya Enokido, Makoto Takizawa 0001 |
A Scalable Group Communication Protocol with Global Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: 19th International Conference on Advanced Information Networking and Applications (AINA 2005), 28-30 March 2005, Taipei, Taiwan, pp. 625-630, 2005, IEEE Computer Society, 0-7695-2249-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida |
Skew measurements in clock distribution circuits using an analytic signal method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7), pp. 997-1009, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Parosh Aziz Abdulla, Johann Deneux, Pritha Mahata |
Multi-Clock Timed Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LICS ![In: 19th IEEE Symposium on Logic in Computer Science (LICS 2004), 14-17 July 2004, Turku, Finland, Proceedings, pp. 345-354, 2004, IEEE Computer Society, 0-7695-2192-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Jean-Michel Hélary, Michel Raynal, Giovanna Melideo, Roberto Baldoni |
Efficient Causality-Tracking Timestamping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Knowl. Data Eng. ![In: IEEE Trans. Knowl. Data Eng. 15(5), pp. 1239-1250, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
message-passing, causality, timestamp, vector clock, Asynchronous distributed computation |
24 | An-Swol Hu, Sergio D. Servetto |
Asymptotically optimal time synchronization in dense sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wireless Sensor Networks and Applications ![In: Proceedings of the Second ACM International Conference on Wireless Sensor Networks and Applications, WSNA 2003, San Diego, CA, USA, September 19, 2003, pp. 1-10, 2003, ACM, 1-58113-764-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Saurabh Ganeriwal, Ram Kumar 0001, Mani B. Srivastava |
Timing-sync protocol for sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SenSys ![In: Proceedings of the 1st International Conference on Embedded Networked Sensor Systems, SenSys 2003, Los Angeles, California, USA, November 5-7, 2003, pp. 138-149, 2003, ACM, 1-58113-707-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
sensor networks, medium access control, time synchronization, packet delay, clock drift |
24 | Kai-Steffen Hielscher, Reinhard German |
A Low-Cost Infrastructure for High Precision High Volume Performance Measurements of Web Clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer Performance Evaluation / TOOLS ![In: Computer Performance Evaluations, Modelling Techniques and Tools. 13th International Conference, TOOLS 2003, Urbana, IL, USA, September 2-5, 2003, Proceedings, pp. 11-28, 2003, Springer, 3-540-40814-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Murali Kudlugi, Russell Tessier |
Static scheduling of multidomain circuits for fast functional verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11), pp. 1253-1268, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Maria Sorea |
A Decidable Fixpoint Logic for Time-Outs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONCUR ![In: CONCUR 2002 - Concurrency Theory, 13th International Conference, Brno, Czech Republic, August 20-23, 2002, Proceedings, pp. 255-271, 2002, Springer, 3-540-44043-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Minsoo Ryu, Jungkeun Park, Seongsoo Hong |
Timing Constraint Remapping to Achieve Time Equi-Continuity in Distributed Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(12), pp. 1310-1320, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
timing constraint transformation, real-time scheduling, clock synchronization, Distributed real-time system |
24 | Dongyao Ji, Yuming Wang |
Comments on "An approach to the formal verification of the two-party cryptographic protocols" by Zhang, Li and Xiao. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGOPS Oper. Syst. Rev. ![In: ACM SIGOPS Oper. Syst. Rev. 35(1), pp. 6-7, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida |
Testing clock distribution circuits using an analytic signal method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001, pp. 323-331, 2001, IEEE Computer Society, 0-7803-7169-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Mingfu Li, Hsin-Min Peng, Chia-Shu Liao |
Fast Computation of Time Deviation and Modified Allan Deviation for Telecommunications Clock Stability Characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 5th International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN 2000), 7-10 December 2000, Dallas / Richardson, TX, USA, pp. 156-160, 2000, IEEE Computer Society, 0-7695-0936-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Vern Paxson |
On Calibrating Measurements of Packet Transit Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 1998 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, SIGMETRICS '98 / PERFORMANCE '98, Madison, Wisconsin, USA, June 22-26, 1998, pp. 11-21, 1998, ACM, 0-89791-982-3. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Johan Bengtsson, Bengt Jonsson 0001, Johan Lilius, Wang Yi 0001 |
Partial Order Reductions for Timed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONCUR ![In: CONCUR '98: Concurrency Theory, 9th International Conference, Nice, France, September 8-11, 1998, Proceedings, pp. 485-500, 1998, Springer, 3-540-64896-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
24 | Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal |
Improving Circuit Testability by Clock Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 288-293, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
24 | Farn Wang, Aloysius K. Mok, E. Allen Emerson |
Symbolic Model Checking for Distributed Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FME ![In: FME '93: Industrial-Strength Formal Methods, First International Symposium of Formal Methods Europe, Odense, Denmark, April 19-23, 1993, Proceedings, pp. 632-651, 1993, Springer, 3-540-56662-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
24 | Hagit Attiya |
Implementing FIFO Queus and Stacks (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
WDAG ![In: Distributed Algorithms, 5th International Workshop, WDAG '91, Delphi, Greece, October 7-9, 1991, Proceedings, pp. 80-94, 1991, Springer, 3-540-55236-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
24 | T. K. Srikanth, Sam Toueg |
Optimal clock synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 34(3), pp. 626-645, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
24 | Darryl Veitch, Julien Ridoux, Satish Babu Korada |
Robust synchronization of absolute and difference clocks over networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 17(2), pp. 417-430, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
TSC, software clock, synchronization, timing, GPS, network measurement, round-trip time, NTP |
24 | Jinkyu Koo, Rajesh Krishna Panta, Saurabh Bagchi, Luis Antonio Montestruque |
A tale of two synchronizing clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SenSys ![In: Proceedings of the 7th International Conference on Embedded Networked Sensor Systems, SenSys 2009, Berkeley, California, USA, November 4-6, 2009, pp. 239-252, 2009, ACM, 978-1-60558-519-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low duty cycle, synchronization, sensor |
24 | Isamu Tsuneizumi, Ailixier Aikebaier, Tomoya Enokido, Makoto Takizawa 0001 |
A flexible group communication protocol with hybrid clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MoMM ![In: MoMM'2009 - The 7th International Conference on Advances in Mobile Computing and Multimedia, 14-16 December 2009, Kuala Lumpur, Malaysia, pp. 469-474, 2009, ACM, 978-1-60558-659-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Taolue Chen, Jian Lu 0001 |
Towards the Complexity of Controls for Timed Automata with a Small Number of Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSKD (5) ![In: Fifth International Conference on Fuzzy Systems and Knowledge Discovery, FSKD 2008, 18-20 October 2008, Jinan, Shandong, China, Proceedings, Volume 5, pp. 134-138, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Ales Smrcka, Vojtech Rehák, Tomás Vojnar, David Safránek, Petr Matousek, Z. Rehák |
Verifying VHDL Designs with Multiple Clocks in SMV. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMICS/PDMC ![In: Formal Methods: Applications and Technology, 11th International Workshop, FMICS 2006 and 5th International Workshop PDMC 2006, Bonn, Germany, August 26-27, and August 31, 2006, Revised Selected Papers, pp. 148-164, 2006, Springer, 978-3-540-70951-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Shengyong Chen, Chunyan Yao, Gang Xiao 0001, Y. S. Ying, Wanliang Wang |
Fault Detection and Prediction of Clocks and Timers Based on Computer Audition and Probabilistic Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN ![In: Computational Intelligence and Bioinspired Systems, 8th International Work-Conference on Artificial Neural Networks, IWANN 2005, Vilanova i la Geltrú, Barcelona, Spain, June 8-10, 2005, Proceedings, pp. 952-959, 2005, Springer, 3-540-26208-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Roberto Gómez Cárdenas, Jorge Herrerías Guerrero, Erika Mata Sanchez |
Using Lamport's Logical Clocks to Consolidate Log Files from Different Sources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IICS ![In: Innovative Internet Community Systems, 5th International Workshop, IICS 2005, Paris, France, June 20-22, 2005, Revised Papers, pp. 126-133, 2005, Springer, 3-540-33973-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | François Laroussinie, Nicolas Markey, Philippe Schnoebelen |
Model Checking Timed Automata with One or Two Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONCUR ![In: CONCUR 2004 - Concurrency Theory, 15th International Conference, London, UK, August 31 - September 3, 2004, Proceedings, pp. 387-401, 2004, Springer, 3-540-22940-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Jo C. Ebergen |
Circuits Without Clocks: What Makes Them Tick? ![Search on Bibsonomy](Pics/bibsonomy.png) |
OPODIS ![In: Principles of Distributed Systems, 7th International Conference, OPODIS 2003 La Martinique, French West Indies, December 10-13, 2003 Revised Selected Papers, pp. 2, 2003, Springer, 3-540-22667-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Geralyn Abinader, Joey Stein, Molly Lenore |
Moving clocks and bending space: a learning/interactive museum environment (LIME). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGGRAPH Educators Program ![In: Educators program from the 30th annual conference on Computer graphics and interactive techniques, 2003, San Diego, California, USA, July 27 - 31, 2003, 2003, ACM, 978-1-4503-7459-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Javier Miranda, Michael González Harbour |
A Proposal to Integrate the POSIX Execution-Time Clocks into Ada 95. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ada-Europe ![In: Reliable Software Technologies - Ada-Europe 2003, 8th Ada-Europe International Conference on Reliable Software Technologies, Toulouse, France, June 16-20, 2003, Proceedings, pp. 344-358, 2003, Springer, 3-540-40376-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Scheduling, Execution-Time, Ada 95, Hard Real-Time, GNAT |
24 | Szilvia Gyapay, Reiko Heckel, Dániel Varró |
Graph Transformation with Time: Causality and Logical Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICGT ![In: Graph Transformation, First International Conference, ICGT 2002, Barcelona, Spain, October 7-12, 2002, Proceedings, pp. 120-134, 2002, Springer, 3-540-44310-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Zhe Dang |
Binary Reachability Analysis of Pushdown Timed Automata with Dense Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 13th International Conference, CAV 2001, Paris, France, July 18-22, 2001, Proceedings, pp. 506-518, 2001, Springer, 3-540-42345-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Sarmistha Neogy, Anupam Sinha, Pradip Kumar Das |
Checkpoint Processing in Distributed Systems Software Using Synchronized Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC ![In: 2001 International Symposium on Information Technology (ITCC 2001), 2-4 April 2001, Las Vegas, NV, USA, pp. 555-559, 2001, IEEE Computer Society, 0-7695-1062-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
Synthesis-for-testability of controller-datapath pairs that use gated clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 613-618, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Jacob Savir |
On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 296-299, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
24 | Rance Cleaveland, Gerald Lüttgen, Michael Mendler |
An Algebraic Theory of Multiple Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONCUR ![In: CONCUR '97: Concurrency Theory, 8th International Conference, Warsaw, Poland, July 1-4, 1997, Proceedings, pp. 166-180, 1997, Springer, 3-540-63141-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
24 | Glenn Jennings, Esther Jennings |
A discrete syntax for level-sensitive latched circuits having n clocks and m phases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1), pp. 111-126, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
24 | Thomas A. Henzinger, Peter W. Kopke, Howard Wong-Toi |
The Expressive Power of Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 22nd International Colloquium, ICALP95, Szeged, Hungary, July 10-14, 1995, Proceedings, pp. 417-428, 1995, Springer, 3-540-60084-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
24 | Atul Adya, Robert Gruber, Barbara Liskov, Umesh Maheshwari |
Efficient Optimistic Concurrency Control Using Loosely Synchronized Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Conference ![In: Proceedings of the 1995 ACM SIGMOD International Conference on Management of Data, San Jose, California, USA, May 22-25, 1995., pp. 23-34, 1995, ACM Press, 978-0-89791-731-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
24 | Peter B. Danzig, Stephen W. Melvin |
High Resolution Timing with Low Resolution Clocks and A Microsecond Resolution Timer for Sun Workstations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGOPS Oper. Syst. Rev. ![In: ACM SIGOPS Oper. Syst. Rev. 24(1), pp. 23-26, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
24 | Bernadette Charron-Bost |
Concerning the Size of Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Semantics of Systems of Concurrent Processes ![In: Semantics of Systems of Concurrent Processes, LITP Spring School on Theoretical Computer Science, La Roche Posay, France, April 23-27, 1990, Proceedings, pp. 176-184, 1990, Springer, 3-540-53479-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
24 | Barbara Liskov, Liuba Shrira, John Wroclawski |
Efficient At-Most-Once Messages Based on Synchronized Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM Symposium on Communications Architectures & Protocols, SIGCOMM 1990, Philadelpia, PA, USA, September 24-27, 1990, pp. 41-49, 1990, ACM, 0-89791-405-8. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
24 | Leslie Lamport, P. M. Melliar-Smith |
Synchronizing Clocks in the Presence of Faults ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 32(1), pp. 52-78, January 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
16 | Thomas Schmid 0002, Dustin Torres, Mani B. Srivastava |
Low-power high-precision timing hardware for sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SenSys ![In: Proceedings of the 7th International Conference on Embedded Networked Sensor Systems, SenSys 2009, Berkeley, California, USA, November 4-6, 2009, pp. 337-338, 2009, ACM, 978-1-60558-519-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
HLTimer, clocks, time synchronization |
16 | Arnd Hartmanns, Holger Hermanns |
A Modest Approach to Checking Probabilistic Timed Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
QEST ![In: QEST 2009, Sixth International Conference on the Quantitative Evaluation of Systems, Budapest, Hungary, 13-16 September 2009, pp. 187-196, 2009, IEEE Computer Society, 978-0-7695-3808-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Probabilistic timed automata, model checking, compositional modelling, digital clocks |
16 | Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay |
Slew-aware clock tree design for reliable subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 15-20, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
slew, clocks, subthreshold |
16 | Piotr Zielinski |
Low-latency atomic broadcast in the presence of contention. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 20(6), pp. 435-450, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Generic Broadcast, Synchronized clocks, Fault-tolerance, Atomic Broadcast |
16 | Thomas Schmid 0002, Zainul Charbiwala, Jonathan Friedman, Young H. Cho, Mani B. Srivastava |
Exploiting manufacturing variations for compensating environment-induced clock drift in time synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2008, Annapolis, MD, USA, June 2-6, 2008, pp. 97-108, 2008, ACM, 978-1-60558-005-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
emulation, clocks, time synchronization, oscillator |
16 | Franco Cicirelli, Angelo Furfaro, Libero Nigro |
Distributed simulation of modular time Petri nets: An approach and a case study exploiting temporal uncertainty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 35(2), pp. 153-179, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Temporal uncertainty, Time interval based event delivery, Modelling complex real-time systems, Modularity constructs, Petri Net Markup Language, Distributed simulation, Time Petri nets, Time warp, Temporal analysis, Logical clocks |
16 | Vijay K. Garg, Chakarat Skawratananond, Neeraj Mittal |
Timestamping messages and events in a distributed system using synchronous communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 19(5-6), pp. 387-402, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Timestamping messages and events, Edge decomposition, Vertex cover, Synchronous communication, Vector clocks |
16 | Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux |
A Survey and Taxonomy of GALS Design Styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(5), pp. 418-428, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
globally asynchronous, locally synchronous (GALS), clock domains, pausible clocks, loosely synchronous, synchronization, asynchronous |
16 | Anand Rajaram, David Z. Pan |
Variation tolerant buffered clock network synthesis with cross links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 157-164, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
non-tree clocks, physical design, VLSI CAD, clock network |
16 | Philippe Charles, Christian Grothoff, Vijay A. Saraswat, Christopher Donawa, Allan Kielstra, Kemal Ebcioglu, Christoph von Praun, Vivek Sarkar |
X10: an object-oriented approach to non-uniform cluster computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA ![In: Proceedings of the 20th Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2005, October 16-20, 2005, San Diego, CA, USA, pp. 519-538, 2005, ACM, 1-59593-031-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
atomic blocks, non-uniform cluster computing (NUCC), partitioned global address space (PGAS), Java, scalability, multithreading, productivity, clocks, data distribution, places, X10 |
16 | Anand Rajaram, David Z. Pan, Jiang Hu |
Improved algorithms for link-based non-tree clock networks for skew variability reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005, pp. 55-62, 2005, ACM, 1-59593-021-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
non-tree clocks, physical design, VLSI CAD, clock network |
16 | Attila Pásztor, Darryl Veitch |
PC based precision timing without GPS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 2002, June 15-19, 2002, Marina Del Rey, California, USA, pp. 1-10, 2002, ACM, 1-58113-531-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
pc clocks, software clock, synchronization, timing, GPS, network measurement, NTP |
16 | Johann Großschädl |
The Chinese Remainder Theorem and its Application in a High-Speed RSA Crypto Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 16th Annual Computer Security Applications Conference (ACSAC 2000), 11-15 December 2000, New Orleans, Louisiana, USA, pp. 384-393, 2000, IEEE Computer Society, 0-7695-0859-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
RSA/spl gamma/ crypto-chip, RSA encryption scheme, hardware performance, long-integer modular arithmetic, private key operations, multiplier architecture, high-speed hardware accelerator, reconfigurable multiplier datapath, word-serial multiplier, modular reduction method, multiplier core, decryption rate, 200 MHz, 560 kbit/s, 2 Mbit/s, parallelism, pipelining, public key cryptography, reconfigurable architectures, clocks, Chinese Remainder Theorem, microprocessor chips, multiplying circuits, modular multiplications, modular exponentiations, pipeline arithmetic, clock frequency |
16 | Kim Guldstrand Larsen, Bernhard Steffen, Carsten Weise |
Continuous Modeling of Real-Time and Hybrid Systems: From Concepts to Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 1(1-2), pp. 64-85, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Continuous time modeling, Timed automata-based modeling, Drifting clocks, Formal methods, Hybrid systems, Discrete time modeling |
16 | Allen E. Sjogren, Chris J. Myers |
Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA, pp. 47-61, 1997, IEEE Computer Society, 0-8186-7913-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Mixed synchronous/asynchronous interfacing, stoppable clocks, high-speed pipelines, globally synchronous locally asynchronous, metastability, synchronization failure |
16 | Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh |
Efficient Testing of Clock Regenerator Circuits in Scan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 95-100, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
clock regenerators, fault simulation, test pattern generation, clocks, microprocessor testing |
16 | Nevin Heintze, J. D. Tygar |
A Model for Secure Protocols and Their Compositions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 22(1), pp. 16-30, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
logic of authentication, protocols-composition of, security, model, model checking, communication, Authentication, formal methods, cryptography, protocols, composition, time, computer security, clocks, protocol analysis, protocol analysis, timed models |
16 | Massoud Pedram |
Power minimization in IC design: principles and applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(1), pp. 3-56, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
adiabatic circuits, dynamic power dissipation, low power layout, low power synthesis, lower-power design, power analysis and estimation, power minimization and management, silicon-on-insulator technology, switched capacitance, synthesis, system design, power management, layout, probabilistic analysis, symbolic simulation, CMOS circuits, switching activity, statistical sampling, computer-aided design of VLSI, gated clocks, energy-delay product |
16 | Chuchang Liu, Mehmet A. Orgun |
Executing specifications of distributed computations with Chronolog(MC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 1996 ACM Symposium on Applied Computing, SAC'96, Philadelphia, PA, USA, February 17-19, 1996, pp. 393-400, 1996, ACM, 0-89791-820-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
simulation, distributed computations, logic programming, temporal logic, clocks, executable specification |
16 | Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli |
Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 9th International Symposium on System Synthesis, ISSS '96, San Diego, CA, USA, November 6-8, 1996., pp. 57-, 1996, ACM / IEEE Computer Society, 0-8186-7563-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
low power, High level synthesis, finite state machines, gated clocks |
16 | Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska |
Design and performance of CMOS TSPC cells for high speed pseudo random testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 368-373, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists |
16 | Samit Chaudhuri, Stephen A. Blythe, Robert A. Walker 0001 |
An exact methodology for scheduling in a 3D design space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 78-83, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
2D design space, 3D design space, 3D scheduling problem, Voyager design space exploration system, candidate clock lengths, clock length, globally optimal solution, schedule length, three dimensional scheduling, three-dimensional design space, two dimensional design space, scheduling, optimisation, high level synthesis, search problems, clocks, tight bounds, network synthesis, search space pruning |
16 | Hong Hao, Kanti Bhabuthmal |
Clock controller design in SuperSPARC II microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 124-129, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
SuperSPARC II, internal clock pulses, internal clock, free running mode, IEEE 1149.1 interface, microprocessor, clocks, microprocessor chips, clock controller |
16 | Gill A. Pratt, John Nguyen |
Distributed synchronous clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 316-330, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
distributed synchronous clocking, hardware clock, synchronous processor, distributed error correction algorithm, global phase alignment, mode lock, k-ary Cartesian meshes, scalability, graph theory, timing, synchronisation, error correction, clocks, phase locked loops, digital systems, clock signals |
16 | Kei-Yong Khoo, Alan N. Willson Jr. |
Single-transistor transparent-latch clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 331-341, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
transparent-latch clocking, single-phase clocking scheme, CMOS VLSI designs, single NMOS transistor, allowable width, clock driver, dynamic buffer, architecture-driven voltage scaling, pipelining latches, latch-intensive architectures, filter structures, transposed-form FIR filter, VLSI, flip-flops, clocks, integrated circuit design, digital filters, FIR filters, power dissipation, CMOS digital integrated circuits |
16 | Hao Zheng, Kewal K. Saluja, Rajiv Jain |
Test application time reduction for scan based sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 188-191, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
scan based sequential circuits, single clock configuration, nonscan flip-flops, test vector length, nonatomic two-clock scan method, test generation environment, logic testing, sequential circuits, flip-flops, clocks, partial scan, boundary scan testing, test application time |
16 | Steve Brown, Germán Gutiérrez, Reed Nelson, Chris VanKrevelen |
A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 467-471, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
emitter-coupled logic, triple channel ATE controller, timing verniers, precision edge timing, drive waveforms, returning signals, system clock frequency, ECL, 500 MHz, 40 ps, timing, clocks, automatic test equipment, logic arrays, programmable controllers, gate array, high speed testing |
16 | Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
Functional clock schedule optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 93-98, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
clock schedule optimization, time frames, level-sensitive sequential circuits, scheduling, delays, delays, timing, sequential circuits, flip-flops, clocks, circuit optimisation, latches, false paths |
16 | William L. Bradley, Ranga Vemuri |
Transformations for functional verification of synthesized designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 243-248, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
low-level functional verification, synthesized designs, clocking mechanisms, provably equivalent model, hierarchical network of modules, reduced state set, de-phase transform, align transform, algorithm, formal verification, transforms, transforms, logic CAD, clocks, hierarchical system, reachable states |
16 | Vernon L. Chi |
Salphasic Distribution of Clock Signals for Synchronous Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(5), pp. 597-602, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
transmission line theory, loaded transmission line, printed circuit board clock planes, clock plane, phase skew, salphasic clock, synchronisation, clocks, distribution network, clock skews, synchronous systems, synchronous system, propagation delay, system clock, phase shifts, clock signals, clock signal |
16 | Alan Olson, Kang G. Shin |
Fault-Tolerant Clock Synchronization in Large Multicomputer Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(9), pp. 912-923, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
fault-tolerant clock synchronization, large multicomputer systems, clock value, maximum skew, maximum time, fault tolerance, reliability, fault tolerant computing, multiprocessing systems, synchronisation, clocks, clock skew, clock drift, synchronization algorithm |
16 | Marina Papatriantafilou, Philippas Tsigas |
On Self-Stabilizing Wait-Free Clock Synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SWAT ![In: Algorithm Theory - SWAT '94, 4th Scandinavian Workshop on Algorithm Theory, Aarhus, Denmark, July 6-8, 1994, Proceedings, pp. 267-277, 1994, Springer, 3-540-58218-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
PRAM computation model, Fault tolerance, Concurrency, Distributed Computing, Synchronization, Self-Stabilization, Synchronous Systems, Wait-Free Synchronization, Digital Clocks |
16 | Ahmed El-Amawy |
Clocking Arbitrarily Large Computing Structures Under Constant Skew Bound. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(3), pp. 241-255, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
constant skew bound, arbitrarily large computing structures, communicating cells, skew upper bound, maximum clocking rate, 2-D mesh framework, node design, nonplanar structures, parallel architectures, stability, hypercubes, network topology, synchronisation, hypercube networks, clocks, clock skew, global synchronization |
16 | Jacob Savir, William H. McAnney |
Random Pattern Testability of Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(3), pp. 291-300, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
combinational logic networks, logic testing, delay faults, combinatorial circuits, latches, random pattern testability, system clocks |
16 | Nohbyung Park, Alice C. Parker |
Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(6), pp. 678-690, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
maximum execution overlap, high-speed digital systems, performance evaluation, data dependencies, clocking, clocks, digital systems, branching, resource conflicts |
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