Search results for "silicon"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
27	John Lazzaro, John Wawrzynek	A multi-sender asynchronous extension to the AER protocol.	ARVLSI	1995	DBLP DOI BibTeX RDF	multi-sender extension, AER, address-event representation, asynchronous point-to-point communications protocol, silicon neural systems, protocols, neural chips
27	Ryan Cochran, Abdullah Nazma Nowroz, Sherief Reda	Post-silicon power characterization using thermal infrared emissions.	ISLPED	2010	DBLP DOI BibTeX RDF	power characterization, thermal infrared emissions
27	Robert C. Aitken	The challenges of correlating silicon and models in high variability CMOS processes.	ISPD	2009	DBLP DOI BibTeX RDF	design validation
27	Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw	Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
27	Atul Madhavan, Vikram L. Dalal, Max A. Noack	Superlattice structures for nanocrystalline silicon solar cells.	EIT	2008	DBLP DOI BibTeX RDF
27	Farinaz Koushanfar, Petros Boufounos, Davood Shamsi	Post-silicon timing characterization by compressed sensing.	ICCAD	2008	DBLP DOI BibTeX RDF
27	Jae Wook Kim, Boris Murmann, Robert W. Dutton	Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices.	ISQED	2008	DBLP DOI BibTeX RDF	bandgap reference, germanium devices, hybrid integration
27	Sung-Boem Park, Subhasish Mitra	IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors.	DAC	2008	DBLP DOI BibTeX RDF	verification, debug, validation, design for debug
27	R. Jacob Vogelstein, Udayan Mallik, Joshua T. Vogelstein, Gert Cauwenberghs	Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses.	IEEE Trans. Neural Networks	2007	DBLP DOI BibTeX RDF
27	Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, Todd M. Austin	Low-cost protection for SER upsets and silicon defects.	DATE	2007	DBLP DOI BibTeX RDF
27	Ehab Anis, Nicola Nicolici	Interactive presentation: Low cost debug architecture using lossy compression for silicon debug.	DATE	2007	DBLP DOI BibTeX RDF
27	Kolin Paul, Joël Porquet, Josep Llosa	Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration.	DSD	2007	DBLP DOI BibTeX RDF
27	Kai-Hui Chang, Igor L. Markov, Valeria Bertacco	Automating post-silicon debugging and repair.	ICCAD	2007	DBLP DOI BibTeX RDF
27	Xin Li 0001, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi	Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.	ICCAD	2007	DBLP DOI BibTeX RDF
27	Kip Killpack, Chandramouli V. Kashyap, Eli Chiprout	Silicon Speedpath Measurement and Feedback into EDA flows.	DAC	2007	DBLP DOI BibTeX RDF
27	Wenhui Wang	Application of Bayesian Network to Tendency Prediction of Blast Furnace Silicon Content in Hot Metal.	LSMS (1)	2007	DBLP DOI BibTeX RDF
27	Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw	A statistical framework for post-silicon tuning through body bias clustering.	ICCAD	2006	DBLP DOI BibTeX RDF
27	Soumendu Bhattacharya, Vishwanath Natarajan, Abhijit Chatterjee, Sankar Nair	Efficient DNA Sensing with Fabricated Silicon Nanopores: Diagnosis Methodology and Algorithms.	VLSI Design	2006	DBLP DOI BibTeX RDF
27	Sean A. Stauth, Babak A. Parviz	Integration of Silicon Circuit Components Onto Plastic substrates Using Fluidic Self-Assembly.	ICMENS	2005	DBLP DOI BibTeX RDF
27	Shi-Hua Luo, Xiang-Guan Liu, Min Zhao	Prediction for Silicon Content in Molten Iron Using a Combined Fuzzy-Associative-Rules Bank.	FSKD (2)	2005	DBLP DOI BibTeX RDF
27	Rakesh B. Katragadda, Yong Xu	A Novel Intelligent Textile Technology Based on Silicon Flexible Skins.	ISWC	2005	DBLP DOI BibTeX RDF
27	Federico Sandoval-Ibarra, L. Flores-Gómez	Design of Silicon-Based Suspended Inductors for UHF Applications.	CONIELECOMP	2004	DBLP DOI BibTeX RDF
27	Debashis Nayak, Srikanth Venkataraman, Paul J. Thadikaran	Razor: A Tool for Post-Silicon Scan ATPG Pattern Debug and Its Application.	VTS	2004	DBLP DOI BibTeX RDF
27	Hari Balachandran, Kenneth M. Butler, Neil Simpson	Facilitating Rapid First Silicon Debug.	ITC	2002	DBLP DOI BibTeX RDF
27	Shahid Masud, John V. McCanny	Design of Silicon IP Cores for Biorthogonal Wavelet Transforms.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	rapid design, FPGA, synthesis, system-on-a-chip, dsp
27	Mark Stephenson, Jonathan Babb, Saman P. Amarasinghe	Bitwidth analysis with application to silicon compilation.	PLDI	2000	DBLP DOI BibTeX RDF
27	Wayne H. Wolf	CAD Techniques for Embedded Systems-on-Silicon.	ICCD	1999	DBLP DOI BibTeX RDF
27	Panagiotis Androutsos, Harry E. Ruda, Anastasios N. Venetsanopoulos	Semi-interactive Structure and Fault Analysis of (111)7x7 Silicon Micrographs.	VISUAL	1999	DBLP DOI BibTeX RDF
27	Tom Marshburn, Ivy Lui, Rick Brown, Dan Cheung, Gary Lum, Peter Cheng	DATAPATH: a CMOS data path silicon assembler.	DAC	1986	DBLP DOI BibTeX RDF
24	Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki	Toward Dark Silicon in Servers.	IEEE Micro	2011	DBLP DOI BibTeX RDF	Dark silicon, specialized computing, scalability, power, energy, multicore
24	Sassan Tabatabaei, Aaron Partridge	Silicon MEMS Oscillators for High-Speed Digital Systems.	IEEE Micro	2010	DBLP DOI BibTeX RDF	silicon oscillator, microelectromechanical systems, MEMS resonator, MEMS packaging, serial interfaces, hardware, clock, oscillator, digital clocking
24	Hyeon Bae, Tae-Ryong Jeon, Sungshin Kim, Hyun-Soo Kim, DongSeop Kim, Seung Soo Han, Gary S. May	Optimization of silicon solar cell fabrication based on neural network and genetic programming modeling.	Soft Comput.	2010	DBLP DOI BibTeX RDF	Silicon solar cell fabrication, Genetic algorithm, Neural network, Genetic programming, Particle swarm optimization
24	John Goodenough 0001, Rob Aitken	Post-silicon is too late avoiding the $50 million paperweight starts with validated designs.	DAC	2010	DBLP DOI BibTeX RDF	low power design, emulation, post-silicon validation
24	Ho Fai Ko, Nicola Nicolici	Resource-Efficient Programmable Trigger Units for Post-Silicon Validation.	ETS	2009	DBLP DOI BibTeX RDF	programmable trigger unit, false trigger analysis, post-silicon validation
24	Junrong Liang, Jiang Zheng, Xin Zhao	Distribution of Antioxidatases in Cell of Diatom Nitzschia Closterium and Response to Different Environmental Silicon Concentrations.	ESIAT (1)	2009	DBLP DOI BibTeX RDF	diatom Nitzschia closterium, plasma membrane, antioxidatase, PPO, POD, environmental silicon concentration, CAT, SOD
24	Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk	A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	Field programmable gate array, system-on-chip, integrated circuit, silicon debug
24	Xiaosong Xu, Hailin Liu 0005, Fuxue Zhang	Phase Processing of No-Drive Structure Silicon Micromachined Gyroscope.	PACIIA (1)	2008	DBLP DOI BibTeX RDF	rotating carrier, silicon micromachined gyroscope, eigenvalue, phase
24	R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram	Architectures for Silicon Nanoelectronics and Beyond.	Computer	2007	DBLP DOI BibTeX RDF	Silicon devices, Computer architectures, Nanotechnology
24	Pradip Bose	Pre-Silicon Modeling and Analysis: Impact On Real Design.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Pre-silicon modeling, performance modeling, CMOS
24	Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham	On-chip delay measurement for silicon debug.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	design for testability, delay fault testing, silicon debug
24	Andreas G. Andreou, Kwabena A. Boahen	A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina.	ARVLSI	1995	DBLP DOI BibTeX RDF	silicon retina, analog VLSI focal plane processor, phototransduction, local gain control, single chip system, vertebrate distal retina, ultra low power dissipation, n-well double metal double poly digital oriented CMOS technology, current-mode subthreshold CMOS, 48000 pixel, computer vision, VLSI, edge detection, CMOS integrated circuits, image sensors, contrast, edge enhancement, CMOS imager, focal planes, area efficiency, 1.2 micron
23	Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan	TSV stress aware timing analysis with applications to 3D-IC layout optimization.	DAC	2010	DBLP DOI BibTeX RDF	mobility variation, timing analysis, stress, TSV, 3DIC
23	Eli Chiprout	On-die power grids: the missing link.	DAC	2010	DBLP DOI BibTeX RDF	decap, voltage, locality, power grid, resonance
23	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
23	Todd M. Austin, Valeria Bertacco, Scott A. Mahlke, Yu Cao	Reliable Systems on Unreliable Fabrics.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
23	Tommy Bojan, Igor Frumkin, Robert Mauri	Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning.	MTV	2007	DBLP DOI BibTeX RDF
23	I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann	Instruction Set Extension Generation with Considering Physical Constraints.	HiPEAC	2007	DBLP DOI BibTeX RDF	Pipestage Timing Constraint, ASIP, Instruction set extension, Extensible Processors
23	Vijay Degalahal, Tim Tuan	Methodology for high level estimation of FPGA power consumption.	ASP-DAC	2005	DBLP DOI BibTeX RDF
23	Arun Shrimali, Anand Venkitachalam, Ravi Arora	Issues and Challenges in Ramp to Production.	ISQED	2005	DBLP DOI BibTeX RDF
23	Gilles-Eric Descamps, Satish Bagalkotkar, Subramaniam Ganesan, Sridhar Subramaniam, Hem Hingarh	The iFlow Design Factory: Evolving Chip Design from an Art to a Process, through Adaptive Resource Management, and Qualified Data Exchange.	ISQED	2003	DBLP DOI BibTeX RDF
23	Rolf Ernst, Kees A. Vissers, Pieter van der Wolf, Gert-Jan van Rootselaar	System level design and debug of high-performance embedded media systems (tutorial).	ICCAD	1999	DBLP BibTeX RDF
21	Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban	Power-efficient, reliable microprocessor architectures: modeling and design methods.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power-efficient design, pre-silicon modeling, reliable operation
21	Vasilis F. Pavlidis, Giovanni De Micheli	Power distribution paths in 3-D ICS.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	power distribution network, 3-D ICS, 3-D integration, through silicon vias
21	Rajeev K. Ranjan 0001, Claudionor Coelho, Sebastian Skalberg	Beyond verification: leveraging formal for debugging.	DAC	2009	DBLP DOI BibTeX RDF	behavioral indexing, post-silicon debugging, traceless debugging, formal verification, debugging, property verification
21	Tsung-Ching Huang, Kwang-Ting (Tim) Cheng, Huai-Yuan Tseng, Chen-Pang Kung	Reliability analysis for flexible electronics: Case study of integrated a-Si: H TFT scan driver.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	amorphous hydrogenated silicon (a-Si:H), flexible electronics, scan driver, thin-film transistor, Reliability, threshold voltage
21	Stefan Tillich, Martin Feldhofer, Thomas Popp, Johann Großschädl	Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	substitution box (S-box), inversion in the finite field GF($28$), standard cell implementation, Advanced Encryption Standard (AES), power consumption, silicon area, critical path delay
21	Wing-Man Tang, Cheung H. Leung, Pui-To Lai	Effects of Insulator Thickness on the Sensing Properties of MISiC Schottky-Diode Hydrogen Sensor.	DELTA	2008	DBLP DOI BibTeX RDF	Hydrogen sensor, silicon carbide, SiO2
21	Jeffrey A. Kash	Leveraging Optical Interconnects in Future Supercomputers and Servers.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	optical network on chip, silicon photonics
21	Paul D. Franzon, W. Rhett Davis, Michael B. Steer, Steve Lipa, Eun Chu Oh, Thorlindur Thorolfsson, Samson Melamed, Sonali Luniya, Tad Doxsee, Stephen Berkeley, Ben Shani, Kurt Obermiller	Design and CAD for 3D integrated circuits.	DAC	2008	DBLP DOI BibTeX RDF	thermal modeling, TSV, through silicon via, 3DIC
21	Linda Dailey Paulson	News Briefs.	Computer	2007	DBLP DOI BibTeX RDF	silicon clock, computer technology, digital camera, click fraud
21	Yaodong Cui, Qiang Wang	Exact and heuristic algorithms for the circle cutting problem in the manufacturing industry of electric motors.	J. Comb. Optim.	2007	DBLP DOI BibTeX RDF	Two-dimensional cutting, Silicon steel plates, Stators and rotors, Cutting
21	Joe Sullivan, Conor Ryan	A destructive evolutionary process: a pilot implementation.	GECCO	2007	DBLP DOI BibTeX RDF	silicon design, reliability, experimentation, flash memory
21	Jonathan P. Bowen, Tim Bergin, Christopher H. Sterling	Reviews.	IEEE Ann. Hist. Comput.	2006	DBLP DOI BibTeX RDF	Halley's Comet, Work Projects Administration, time line, origins of the Internet, Silicon Valley, General Electric, Litton Industries, Shockley Semiconductor, Fairchild Semiconductor, human computers
21	Egidio Ragonese, Alessandro Italia, Giuseppe Palmisano	An image-reject down-converter for 802.11a and HIPERLAN2 wireless LANs.	Telecommun. Syst.	2006	DBLP DOI BibTeX RDF	Image rejection, Radio receiver, Silicon bipolar technology, Wireless local area network, Inductors
21	Miron Abramovici, Paul Bradley, Kumar N. Dwarakanath, Peter Levin, Gérard Memmi, Dave Miller	A reconfigurable design-for-debug infrastructure for SoCs.	DAC	2006	DBLP DOI BibTeX RDF	assertion-based debug, at-speed debug, what-if experiments, silicon debug
21	Steve Leibson, James Kim	Configurable Processors: A New Era in Chip Design.	Computer	2005	DBLP DOI BibTeX RDF	nanometer silicon lithography, microprocessors, multiprocessor systems, MPSoCs, configurable processors
21		Inventions: A Result of Risk-Taking, Diversity, and Holistic Thinking - An interview with Bernard S. Meyerson, IBM Fellow, Vice President, and Chief Technologist of IBM's System Technology Group.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	silicon germanium, semiconductor
21	Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green	Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	systematic yield loss, test structure, BEOL, DFM, process monitoring, silicon debug, infrastructure IP
21		Panel Summaries.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	IEEE European Test Symposium, IEEE Infrastructure IP Workshop, silicon debug, microelectronics, infrastructure IP
21	Lech Józwiak	Life-Inspired Systems.	DSD	2004	DBLP DOI BibTeX RDF	Life-inspired Systems, Silicon and System Complexity, Embedded Systems, System on Chip, Design Methodology, System in Package
21	Sandeep Kumar Goel, Bart Vermeulen	Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains
21	Nathalie Picollet-D'hahan, Fabien Sauter, Florence Ricoul, Catherine Pudda, Frédérique Marcel, Thomas Sordel, François Chatelain, Isabelle Chartier	Multi-Patch : A Chip-Based Ion-Channel Assay System for Drug Screening.	ICMENS	2003	DBLP DOI BibTeX RDF	silicon microfabrication, electrophysiology, ion channels
21	Yervant Zorian	Yield Improvement and Repair Trade-Off for Large Embedded Memories.	DATE	2000	DBLP DOI BibTeX RDF	silicon repair, BIST, DFM, Yield improvement
21	José Luis Bosque, Oscar David Robles, Angel Rodríguez, Luis Pastor	Study of a Parallel CBIR Implementation using MPI.	CAMP	2000	DBLP DOI BibTeX RDF	parallel CBIR implementation, bidimensional RGB images, distributed memory multiprocessor environment, master process, slave process, Silicon Graphics Origin 2000, MPI, image database, visual databases, parallel implementation, content based information retrieval, shared memory machine
21	Eric W. MacDonald, Nur A. Touba	Testing domino circuits in SOI technology.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	silicon-on-insulator, SOI technology, dynamic circuit styles, fault modeling analysis, overall fault coverage, parasitic bipolar leakage, CMOS logic, logic testing, integrated circuit testing, automatic testing, fault simulation, CMOS logic circuits, leakage currents, domino circuits
21	Michael J. Flynn	What's ahead in computer design?	EUROMICRO	1997	DBLP DOI BibTeX RDF	die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size
21	Yves Gagnon, Yvon Savaria, Michel Meunier, Claude Thibeault	Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model.	DFT	1997	DBLP DOI BibTeX RDF	defect-tolerant circuit, contamination, wafer test, silicon chip, reconfiguration, redundancy, integrated circuit testing, manufacturing, yield, cost model, integrated circuit, figure of merit, fault tolerant circuit
21	Craig Farnsworth, David A. Edwards, Jianwei Liu, Shiv S. Sikand	A hybrid asynchronous system design environment.	ASYNC	1995	DBLP DOI BibTeX RDF	hybrid asynchronous system design environment, hybrid design scheme, asynchronous circuit synthesis, Tangram silicon complier, synchronous design techniques, concurrency, high level synthesis, asynchronous circuits, power reduction, performance gains, micropipelines
21	Vijay K. Jain, L. Lin	High-speed double precision computation of nonlinear functions.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	high-speed double precision computation, interpolative approach, third degree polynomial, image processing, interpolation, interpolation, scientific computing, digital arithmetic, multiplications, coprocessors, coprocessors, real-time image processing, nonlinear functions, silicon area
21	Jehoshua Bruck, Danny Dolev, Ching-Tien Ho, Rimon Orni, H. Raymond Strong	PCODE: an efficient and reliable collective communication protocol for unreliable broadcast domain.	IPPS	1995	DBLP DOI BibTeX RDF	PCODE, unreliable broadcast domain, point-to-point protocol, Silicon Graphics Indigo workstations, broadcast, message passing, programming environments, local area networks, transport protocols, communication protocol, LAN
21	Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man	Synthesis of pipelined DSP accelerators with dynamic scheduling.	ISSS	1995	DBLP DOI BibTeX RDF	DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules
21	Tadeusz Luba	Decomposition of Multiple-Valued Functions.	ISMVL	1995	DBLP DOI BibTeX RDF	silicon space, PLA implementations, information storing systems, information systems, logic design, decomposition, logic synthesis, programmable logic arrays, multivalued logic, logic circuits, data bases, multiple-valued functions
21	Evangelos P. Markatos, Thomas J. LeBlanc	Using Processor Affinity in Loop Scheduling on Shared-Memory Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	processoraffinity, kernel programs, Silicon Graphics multiprocessor, BBN Butterfly, SequentSymmetry, KSR-1, scheduling, performance evaluation, synchronization, shared-memory multiprocessors, shared memory systems, iterations, performance improvements, communication overhead, loop scheduling, loop iterations, load imbalance
21	W. Stephen Adolph, Hassan K. Reghbati, Amar Sanmugasunderam	A frame based system for representing knowledge about VLSI design: a proposal.	DAC	1986	DBLP DOI BibTeX RDF	computer assisted design, knowledge representation, VLSI design, silicon compilation
21	Atsushi Sanada 0002, Kazuo Ishii, Tetsuya Yagi	A Robot Vision System Using a Silicon Retina.	Brain-Inspired Information Technology	2010	DBLP DOI BibTeX RDF
21	Ho Fai Ko, Nicola Nicolici	Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
21	Tao Chen 0010, Liguo Chen, Lining Sun	Piezoelectrically driven silicon microgrippers integrated with sidewall piezoresistive sensor.	ICRA	2009	DBLP DOI BibTeX RDF
21	Satya Saripalli, Vikram Dalal	Microcrystalline silicon-germanium solar cells fabricated using VHF PECVD.	EIT	2008	DBLP DOI BibTeX RDF
21	Ashutosh Chakraborty, Sean X. Shi, David Z. Pan	Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices.	DATE	2008	DBLP DOI BibTeX RDF
21	Garrick Orchard, Alexander F. Russell, Kevin Mazurek, Francesco Tenore, Ralph Etienne-Cummings	Configuring silicon neural networks using genetic algorithms.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Wei Tang 0002, Andreas G. Andreou, Eugenio Culurciello	A low-power silicon-on-sapphire tunable ultra-wideband transmitter.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Mel Ho, Pantelis Georgiou, Suket Singhal, Nick Oliver, Chris Toumazou	A bio-inspired closed-loop insulin delivery based on the silicon pancreatic beta-cell.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Houbin Li, Xiaohui Zhang, Wenjuan Gu, Shengping Yi, Chi Huang	The Preparation and Characterization of a Compatibilizer: Silicon Dioxide Nanoparticles Grafted with L-Lactic Acid Oligomer.	CSSE (6)	2008	DBLP DOI BibTeX RDF
21	Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang 0006	BackSpace: Formal Analysis for Post-Silicon Debug.	FMCAD	2008	DBLP DOI BibTeX RDF
21	Todd J. Foster, Dennis L. Lastor, Padmaraj Singh	First Silicon Functional Validation and Debug of Multicore Microprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	Justin Gregg, Tom W. Chen	Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	Dimitris Gizopoulos, Robert C. Aitken, Sandip Kundu	Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems".	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
21	John V. Arthur, Kwabena A. Boahen	Synchrony in Silicon: The Gamma Rhythm.	IEEE Trans. Neural Networks	2007	DBLP DOI BibTeX RDF
21	Prashant Agrawal, Srinivasa R. S. T. G, Ajit N. Oke, Saurabh Vijay	An Approach for Pre-Silicon Power Modeling.	ICCTA	2007	DBLP DOI BibTeX RDF
21	John V. Arthur, Kwabena Boahen 0001	Silicon Neurons that Inhibit to Synchronize.	ISCAS	2007	DBLP DOI BibTeX RDF