Search results for "yield"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
32	Sandrine Barberan, Frederic Duvivier	Management of Critical Areas and Defectivity Data for Yield Trend Modeling.	DFT	1998	DBLP DOI BibTeX RDF	critical areas, defect analysis, yield modeling
32	Leendert M. Huisman	Yield fluctuations and defect models.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	chip testing, defect distribution, field failures, clustering, yield, defect coverage
31	Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka	Statistical yield analysis of silicon-on-insulator embedded DRAM.	ISQED	2009	DBLP DOI BibTeX RDF
31	Shingo Watanabe, Masanori Hashimoto, Toshinori Sato	A case for exploiting complex arithmetic circuits towards performance yield enhancement.	ISQED	2009	DBLP DOI BibTeX RDF
31	Sridhar Varadan, Janet Meiling Wang, Jiang Hu	Handling partial correlations in yield prediction.	ASP-DAC	2008	DBLP DOI BibTeX RDF
31	Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan	Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models.	VLSI Design	2008	DBLP DOI BibTeX RDF
31	Guo Yu, Peng Li 0001	Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling.	ICCAD	2007	DBLP DOI BibTeX RDF
31	Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou 0001	Yield-Aware Cache Architectures.	MICRO	2006	DBLP DOI BibTeX RDF
31	Fangyi Luo, Yongbo Jia, Wayne Wei-Ming Dai	Yield-preferred via insertion based on novel geotopological technology.	ASP-DAC	2006	DBLP DOI BibTeX RDF
31	Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande	NoC Interconnect Yield Improvement Using Crosspoint Redundancy.	DFT	2006	DBLP DOI BibTeX RDF
31	Sujan Pandey, Manfred Glesner	Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.	DAC	2006	DBLP DOI BibTeX RDF	communication bus synthesis, voltage scaling
31	Carlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles	How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results.	ISQED	2005	DBLP DOI BibTeX RDF
31	Yervant Zorian	Investment vs. Yield Relationship for Memories in SOC.	ITC	2004	DBLP DOI BibTeX RDF
31	Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken	Detection of Yield Trends.	DFT	1997	DBLP DOI BibTeX RDF
31	D. D. Sharma, Fred J. Meyer, Dhiraj K. Pradhan	Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
31	Bruno Ciciani, Giuseppe Iazeolla	A Markov chain-based yield formula for VLSI fault-tolerant chips.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
30	Chin-Te Kao, Sam Wu, Jwu E. Chen	A case study of failure analysis and guardband determination for a 64M-bit DRAM.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	guardband determination, prevention strategy, test derivation, test cost, 64 Mbit, integrated circuit testing, yield, DRAM, failure analysis, failure analysis, test selection, DRAM chips, product quality, integrated circuit yield, integrated circuit economics
30	Hari Balachandran, D. M. H. Walker	Improvement of SRAM-based failure analysis using calibrated Iddq testing.	VTS	1996	DBLP DOI BibTeX RDF	defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield
29	Stephen Bijansky, Adnan Aziz	TuneFPGA: post-silicon tuning of dual-Vdd FPGAs.	DAC	2008	DBLP DOI BibTeX RDF	FPGA, delay, process variation, yield, tuning
28	Andrew B. Kahng	How to get real mad.	ISPD	2008	DBLP DOI BibTeX RDF	design-aware manufacturing, integrated circuit physical design, manufacturing-aware design, performance analysis, design for manufacturability
28	Srikanth Venkataraman, Nagesh Tamarapalli	DFM / DFT / SiliconDebug / Diagnosis.	VLSI Design	2008	DBLP DOI BibTeX RDF
28	Michel Côté, Philippe Hurat	Standard Cell Printability Grading and Hot Spot Detection.	ISQED	2005	DBLP DOI BibTeX RDF
28	John Ferguson	Shifting Methods: Adopting a Design for Manufacture Flow.	ISQED	2004	DBLP DOI BibTeX RDF
28	Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou	An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors.	EDCC	1994	DBLP DOI BibTeX RDF
28	Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram	Dominant critical gate identification for power and yield optimization in logic circuits.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low-vt, process variations, yield
28	Yan Li 0029, Vladimir Stojanovic	Yield-driven iterative robust circuit optimization algorithm.	DAC	2009	DBLP DOI BibTeX RDF	robust circuit optimization, variability, yield, analog circuits
28	N. Pete Sedcole, Peter Y. K. Cheung	Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modeling, FPGA, Delay, reconfiguration, process variation, yield
28	Kristian Granhaug, Snorre Aunet	Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Subthreshold CMOS, Output-wired redundancy, Yield and defect tolerance
28	Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham	Cache Design for Low Power and High Yield.	ISQED	2008	DBLP DOI BibTeX RDF	reduce voltage swing, sram yield, SRAM 6T cell, cache design, parametric failure
28	Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike	Performance and yield enhancement of FPGAs with within-die variation using multiple configurations.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, configuration, within-die variation, timing yield
28	Adesh K. Sharma, R. K. Sharma 0001, H. S. Kasana	Empirical comparisons of feed-forward connectionist and conventional regression models for prediction of first lactation 305-day milk yield in Karan Fries dairy cows.	Neural Comput. Appl.	2006	DBLP DOI BibTeX RDF	Dairy production, Karan Fries cows, 305-day milk yield, Prediction, Radial basis function networks, Connectionist models, Back-propagation networks
28	Dirk Müller 0003	Optimizing yield in global routing.	ICCAD	2006	DBLP DOI BibTeX RDF	Steiner tree packing, multi-commodity flows, yield optimization, VLSI routing
28	Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou 0001	Improved multilevel routing with redundant via placement for yield and reliability.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	redundant via, routing, VLSI, DFM, yield enhancement
28	Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg	On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	fault diagnosis, yield improvement
28	Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey	Deformations of IC Structure in Test and Yield Learning.	ITC	2003	DBLP DOI BibTeX RDF	yield learning, defect characterization, diagnosis, fault modeling, defects
28	Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah	Statistical timing for parametric yield prediction of digital integrated circuits.	DAC	2003	DBLP DOI BibTeX RDF	statistical timing, yield prediction
28	Kassem Saleh, Robert L. Probert, W. Li, W. Fong	An approach for high-yield requirements capture for e-commerce and its application.	Int. J. Digit. Libr.	2002	DBLP DOI BibTeX RDF	High-yield scenarios, Requirements capture approach, UML, Electronic commerce
28	Vibhu Kalyan	Dynamic Customer Value Management: Asset Values under Demand Uncertainty using Airline Yield Management and Related Techniques.	Inf. Syst. Frontiers	2002	DBLP DOI BibTeX RDF	MAV, value management, asset values, uncertainty, resources, yield management
28	Yervant Zorian	Embedding infrastructure IP for SOC yield improvement.	DAC	2002	DBLP DOI BibTeX RDF	embedded test & repair, semiconductor IP, yield optimization, test resource partitioning
28	Yervant Zorian	Yield Improvement and Repair Trade-Off for Large Embedded Memories.	DATE	2000	DBLP DOI BibTeX RDF	silicon repair, BIST, DFM, Yield improvement
28	Nobuhiro Tomabechi	Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems.	DFT	1999	DBLP DOI BibTeX RDF	subsystem-dividing, yield, defect-tolerant, WSI, multi-dimensional
28	Andrea Boni, Andrea Pierazzi	Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCs.	DFT	1998	DBLP DOI BibTeX RDF	BiCMOS analog integrated circuits, Monte Carlo methods, Yield optimization, Analog-digital conversion
28	Jeffrey Z. Su, Wayne Wei-Ming Dai	Post-route optimization for improved yield using a rubber-band wiring model.	ICCAD	1997	DBLP DOI BibTeX RDF	Rubber-Band, Topological Wiring Even Wire Distribution, Yield, Design for Manufacturability, Spacing, Bridge Fault, Routability, Critical Area, Layout Optimization, Routing Congestion
28	Fran Hanchek, Shantanu Dutt	Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	circuit reconfiguration, node covering, fault tolerance, field programmable gate array (FPGA), yield improvement
28	Kanji Hirabayashi	A parametric yield model.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	AC yield, delay defect, exponential distribution
28	Yinan N. Shen, Fabrizio Lombardi	Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	redundant memory, diagnosis, yield, repair, WSI
27	Azadeh Davoodi, Ankur Srivastava 0001	Variability Driven Gate Sizing for Binning Yield Optimization.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
27	Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan	Track Routing and Optimization for Yield.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
27	Chih-Min Fan, Yun-Pei Lu	A Bayesian framework to integrate knowledge-based and data-driven inference tools for reliable yield diagnoses.	WSC	2008	DBLP DOI BibTeX RDF
27	Jae Chul Cha, Sandeep K. Gupta 0001	Characterization of granularity and redundancy for SRAMs for optimal yield-per-area.	ICCD	2008	DBLP DOI BibTeX RDF
27	Julien Vial, Alberto Bosio, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Using TMR Architectures for Yield Improvement.	DFT	2008	DBLP DOI BibTeX RDF
27	Lin Xie, Azadeh Davoodi	Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations.	ISQED	2008	DBLP DOI BibTeX RDF
27	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
27	Lucas Brusamarello, Roberto da Silva, Ricardo A. L. Reis, Gilson I. Wirth	Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations.	ISVLSI	2007	DBLP DOI BibTeX RDF
27	Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer	Reduction of detected acceptable faults for yield improvement via error-tolerance.	DATE	2007	DBLP DOI BibTeX RDF
27	Cesare Ferri, Sherief Reda, R. Iris Bahar	Strategies for improving the parametric yield and profits of 3D ICs.	ICCAD	2007	DBLP DOI BibTeX RDF
27	Mingjing Chen, Alex Orailoglu	Circuit-level mismatch modelling and yield optimization for CMOS analog circuits.	ICCD	2007	DBLP DOI BibTeX RDF
27	Srikanth Venkataraman	DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield.	ISQED	2007	DBLP DOI BibTeX RDF
27	Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif	Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.	ISQED	2007	DBLP DOI BibTeX RDF
27	Xin Li 0001, Lawrence T. Pileggi	Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits.	DAC	2007	DBLP DOI BibTeX RDF
27	Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan	TROY: Track Router with Yield-driven Wire Planning.	DAC	2007	DBLP DOI BibTeX RDF
27	Kyungmee O. Kim	Relating integrated circuit yield and time-dependent reliability for various defect density distributions.	IEEE Trans. Reliab.	2006	DBLP DOI BibTeX RDF
27	Wei-Shen Wang, Michael Orshansky	Robust estimation of parametric yield under limited descriptions of uncertainty.	ICCAD	2006	DBLP DOI BibTeX RDF
27	Min Pan, Chris C. N. Chu, Hai Zhou 0001	Timing yield estimation using statistical static timing analysis.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
27	Dong-Hyun Baek, In-Jae Jeong, Chang Hee Han	Application of Data Mining for Improving Yield in Wafer Fabrication System.	ICCSA (4)	2005	DBLP DOI BibTeX RDF
27	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	False Path and Clock Scheduling Based Yield-Aware Gate Sizing.	VLSI Design	2005	DBLP DOI BibTeX RDF
27	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	A yield improvement methodology using pre- and post-silicon statistical clock scheduling.	ICCAD	2004	DBLP DOI BibTeX RDF
27	Andreas J. Strojwas, Michael Campbell, Vassilios Gerousis, Jim Hogan, John Kibarian, Marc Levitt, Walter Ng, Dipu Pramanik, Mark Templeton	When IC yield missed the target, who is at fault?	DAC	2004	DBLP DOI BibTeX RDF
27	André K. Nieuwland, Richard P. Kleihorst	The positive effect on IC yield of embedded Fault Tolerance for SEUs.	IOLTS	2003	DBLP DOI BibTeX RDF
27	Emmanuel Rondey, Yann Tellier, Simone Borri	A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios.	MTDT	2002	DBLP DOI BibTeX RDF
27	Yuichi Hamamura, Kazunori Nemoto, Takaaki Kumazawa, Hisafumi Iwata, Kousuke Okuyama, Shiro Kamohara, Aritoshi Sugimoto	Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure.	DFT	2002	DBLP DOI BibTeX RDF
27	Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh	Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model.	ITC	2002	DBLP DOI BibTeX RDF
27	José Pineda de Gyvez	Yield modeling and BEOL fundamentals.	SLIP	2001	DBLP DOI BibTeX RDF
27	Ron Ross, Keith McCasland	Early Detection of Design Sensitivities that Cause Yield Loss for New Products.	ISQED	2001	DBLP DOI BibTeX RDF
27	Valery Axelrad, Nicolas B. Cobb, M. O'Brien, Thuy Do, Tom Donnelly, Yuri Granik, Emile Y. Sahouria, Victor Boksha, Artur Balasinski	Efficient Full-Chip Yield Analysis Methodology for OPC-Corrected VLSI Designs.	ISQED	2000	DBLP DOI BibTeX RDF
27	ShaoWei Pan, Yu Hen Hu	PYFS-a statistical optimization method for integrated circuit yield enhancement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
27	Sy-Yen Kuo	YOR: a yield-optimizing routing algorithm by minimizing critical areas and vias.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
27	Albert V. Ferris-Prabhu	On the assumptions contained in semiconductor yield models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
27	José Pineda de Gyvez, Jochen A. G. Jess	On the design and implementation of a wafer yield editor.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
27	Dale E. Hocevar, Paul F. Cox, Ping Yang 0001	Parametric yield optimization for MOS circuit blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
27	Tian-Shen Tang, M. A. Styblinski	Yield optimization for nondifferentiable density functions using convolution techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
27	Steve Perry, Mike Mitchell, David J. Pilling	Yield analysis modeling.	DAC	1985	DBLP DOI BibTeX RDF
26	Rani S. Ghaida, Payman Zarkesh-Ha	A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects.	J. Electron. Test.	2009	DBLP DOI BibTeX RDF	Layout sensitivity, Narrow defects, Electromigration, Critical area, Yield prediction, Yield modeling, Spot defects
26	Carlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, Patrick McNamara	An effective DFM strategy requires accurate process and IP pre-characterization.	DAC	2005	DBLP DOI BibTeX RDF	test chips, yield, DFM, yield models
26	Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar	Testability-oriented channel routing.	VLSI Design	1995	DBLP DOI BibTeX RDF	IC testing quality, testability-oriented channel routing, IC layout modification, test escape probability, iterative channel routing tool, fault undetectability, WrenTR, fault diagnosis, integrated circuit testing, design for testability, fault detectability, network routing, circuit layout CAD, bridging fault, circuit optimisation, integrated circuit layout, design strategies, yield loss, integrated circuit yield
26	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model.	VTS	2001	DBLP DOI BibTeX RDF
25	Jaeheon Yi, Cormac Flanagan	Effects for cooperable and serializable threads.	TLDI	2010	DBLP DOI BibTeX RDF	atomicity, yield, race conditions, effect system
25	Aarti Choudhary, Sandip Kundu	A process variation tolerant self-compensating FinFET based sense amplifier design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	sense amplifier, robustness, process -variation, yield, sram, finfet
25	Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu	Raisin: Redundancy Analysis Algorithm Simulation.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	repair rate, BIRA, Raisin, yield, BISR, redundancy analysis, algorithm simulation
25	Jun Zhang, Yiming Wang, Jinping Li, Ping Yang	A Neural Network Model for Predicting Cotton Yields.	CCTA	2007	DBLP DOI BibTeX RDF	precision farming, cotton yield, artificial neural network
25	Qi Lin, Mei Ma, Tony Vo, Jenny Fan, Xin Wu, Richard Li, Xiao-Yu Li	Design-for-Manufacture for Multi Gate Oxide CMOS Process.	ISQED	2007	DBLP DOI BibTeX RDF	multi gate oxide, FPGA, layout, yield, DFM
25	Kang Yi, Kyeong-Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil	Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Low power image filter design, Memory yield enhancement, Memory-error resilient design, H.264 codec, BIST, Embedded memory, BISR
25	David T. Blaauw, Kaviraj Chopra	CAD tools for variation tolerance.	DAC	2005	DBLP DOI BibTeX RDF	variability, yield, design flows
25	Israel Koren, Zahava Koren	Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs.	DFT	1997	DBLP DOI BibTeX RDF	Memory IC, yield, defect-tolerance
24	Serkan Ozdemir, Yan Pan, Abhishek Das, Gokhan Memik, Gabriel H. Loh, Alok N. Choudhary	Quantifying and coping with parametric variations in 3D-stacked microarchitectures.	DAC	2010	DBLP DOI BibTeX RDF	processor pipeline, process variations, 3D integration, cache architectures
24	Youngshin Han, Junghee Kim, Chilgee Lee	Automatic Detection of Failure Patterns Using Data Mining.	KES (2)	2005	DBLP DOI BibTeX RDF
24	Srinivas Raghvendra, Philippe Hurat	DFM: Linking Design and Manufacturing.	VLSI Design	2005	DBLP DOI BibTeX RDF
24	Junichi Hirase	High Precision Result Evaluation of VLSI.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
24	Saeed Shamshiri, Kwang-Ting (Tim) Cheng	Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	yield and cost modeling, Fault tolerance, reliability, system on a chip, redundant design
24	Mottaqiallah Taouil, Said Hamdioui	Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories.	ETS	2011	DBLP DOI BibTeX RDF	3D stacked-IC, memory redundancy, 3D memory, yield enhancement