Search results for "ATPG"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Spyros Tragoudas, Maria K. Michael	Functional ATPG for Delay Faults.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
26	Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara	An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
26	Aiman H. El-Maleh, Mark Kassab, Janusz Rajski	A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance.	DAC	1998	DBLP DOI BibTeX RDF	model checking, verification, guided search
26	A. Dargelas, C. Gauthron, Yves Bertrand	MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
26	Paolo Camurati, Marco Gilli, Paolo Prinetto, Matteo Sonza Reorda	The Use of Model Checking in ATPG for Sequential Circuits.	CAV	1990	DBLP DOI BibTeX RDF
26	André Ivanov, Vinod K. Agarwal	Dynamic testability measures for ATPG.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
24	Xiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu	ECR: a low complexity generalized error cancellation rewiring scheme.	DAC	2010	DBLP DOI BibTeX RDF	error cancellation, ATPG, rewire
24	Scott Davidson 0001	The commonality of vector generation techniques.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	output compression, non-fault-directed test, semi-fault-directed test, ATPG, test compression, full scan, vector generation, logic BIST
24	Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos	Hybrid-SBST Methodology for Efficient Testing of Processor Cores.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	H-SBST, RTPG, computer architecture, ATPG, functional testing, microprocessor testing, software-based self-test
24	Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker 0001	Power Droop Testing.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	power droop, signal integrity errors, high-frequency effects, low-frequency effects, ATPG, heuristic method, D-algorithm
24	Seongmoon Wang, Wenlong Wei	A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture.	ASP-DAC	2007	DBLP DOI BibTeX RDF	peak current reduction, average power dissipation, clock tree construction, special scan cells, scan chain reordering, ATPG, scan designs
24	Hani Rizk, Christos A. Papachristou, Francis G. Wolff	A Self Test Program Design Technique for Embedded DSP Cores.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	self test programs, pseudorandom BIST, LSFR, DSP, ATPG
24	Abhishek Singh 0001, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel	Defect Simulation Methodology for iDDT Testing.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	iDDT, transient current testing, device testing, ATPG, fault simulation, IDDQ, defect simulation, defect-based test
24	Martin Stáva, Ondrej Novák	Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW.	DSD	2006	DBLP DOI BibTeX RDF	FPGA, VLSI, ATPG, hardware, on-line learning, Backtrace
24	Vishnu C. Vimjam, Michael S. Hsiao	Fast illegal state identification for improving SAT-based induction.	DAC	2006	DBLP DOI BibTeX RDF	learning, ATPG, SAT, induction
24	Scott Davidson 0001	Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	X-tolerant, IC outlier, ATPG, BIST, yield, IDDQ, International Test Conference, test metrics
24	Maher N. Mneimneh, Karem A. Sakallah	Principles of Sequential-Equivalence Verification.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	conceptual and algorithmic approache, ATPG, sequential-equivalence checking, satisfiability solvers
24	Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara	New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	scan and non-scan, fault efficiency, ATPG
24	Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja	Multiple Faults: Modeling, Simulation and Test.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	ATPG Modeling, Fault Modeling, Multiple Fault
24	Hiroyuki Higuchi	An implication-based method to detect multi-cycle paths in large sequential circuits.	DAC	2002	DBLP DOI BibTeX RDF	multi-cycle path, sequential circuits, ATPG, implication
24	Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker 0001	Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	sequential circuit ATPG, single observation time test strategy, multiple observation time test strategy, genetic algorithm, symbolic simulation
24	Zhigang Yin, Yinghua Min, Xiaowei Li 0001	An Approach to RTL Fault Extraction and Test Generation.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	ATPG (Automatic Test Pattern Generation), RTL (Register Transfer Level), Fault
24	Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya	Isomorph-Redundancy in Sequential Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	testing, redundancy, ATPG, DFT, stuck-at faults, sequential machines
24	Li-C. Wang, Magdy S. Abadir	On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	custom circuits, high level circuit extraction, ATPG, DFT, time-to-market
24	Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	A new framework for static timing analysis, incremental timing refinement, and timing simulation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	incremental timing refinement, signal arrival, target fault, test generation efficiency, logic testing, delays, timing, test generation, integrated circuit testing, computation, automatic test pattern generation, ATPG, static timing analysis, delay model, timing simulation
24	Emil Gizdarski, Hideo Fujiwara	Spirit: satisfiability problem implementation for redundancy identification and test generation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Boolean satisfiability method, SPIRIT, ATPG system, logic testing, computability, automatic test pattern generation, combinational circuits, combinational circuits, test pattern generation, test sets
24	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	Design for sequential testability: an internal state reseeding approach for 100 % fault coverage.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	sequential testability, internal state reseeding, observation points, minimum DFT insertion, non-scan approach, fault efficiency, 100 percent, fault diagnosis, logic testing, controllability, controllability, design for testability, logic design, sequential circuits, automatic test pattern generation, ATPG, observability, fault coverage, flip-flops, at-speed testing, benchmark circuits, CPU time, partial reset
24	Tsuyoshi Shinogi, Terumine Hayashi	A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	compact test generation, parallel processing, ATPG, IDDQ testing
24	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen	On Verifying the Correctness of Retimed Circuits.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	3-valued equivalence, delay-compensation, sequential ATPG, formal verification, retiming, equivalence-Checking
24	Antoni Ferré, Joan Figueras	On estimating bounds of the quiescent current for IDDQ testin.	VTS	1996	DBLP DOI BibTeX RDF	quiescent current bounds, sensing circuitry design, VLSI, logic testing, integrated circuit testing, ATPG, automatic testing, CMOS integrated circuits, leakage currents, I/sub DDQ/ testing, CMOS ICs, hierarchical approach
24	Subhrajit Bhattacharya, Sujit Dey	H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads.	VTS	1996	DBLP DOI BibTeX RDF	H-SCAN, parallel register connectivity, on-chip response, sequential test vectors, combinational test vectors, combinational ATPG program, RT-level design, integrated circuit testing, design for testability, automatic testing, fault simulation, fault coverage, test pattern generation, comparator, boundary scan testing, test application time, high-level design, area overhead, testing methodology
24	Marcello Dalpasso, Michele Favalli, Piero Olivo	Test pattern generation for IDDQ: increasing test quality.	VTS	1995	DBLP DOI BibTeX RDF	ATPG strategy, quiescent power supply current monitoring, logic testing, integrated circuit testing, automatic testing, fault coverage, test pattern generation, CMOS logic circuits, I/sub DDQ/ testing
18	Pallav Gupta, Rui Zhang, Niraj K. Jha	Automatic Test Generation for Combinational Threshold Logic Networks.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
18	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
18	Ho Fai Ko, Nicola Nicolici	Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
18	Jiri Jenícek	Efficient Test Pattern Compression Method Using Hard Fault Preferring.	DSD	2008	DBLP DOI BibTeX RDF
18	Minjin Zhang, Huawei Li 0001, Xiaowei Li 0001	Multiple Coupling Effects Oriented Path Delay Test Generation.	VTS	2008	DBLP DOI BibTeX RDF	crosstalk, delay test, path delay fault
18	Shih-Ping Lin 0001, Chung-Len Lee 0001, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu	A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
18	Kunal P. Ganeshpure, Sandip Kundu	Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults.	DATE	2007	DBLP DOI BibTeX RDF
18	Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel	Computation and Application of Absolute Dominators in Industrial Designs.	ETS	2007	DBLP DOI BibTeX RDF
18	Srivaths Ravi 0001, V. R. Devanathan, Rubin A. Parekhji	Methodology for low power test pattern generation using activity threshold control logic.	ICCAD	2007	DBLP DOI BibTeX RDF
18	Nina Amla, Kenneth L. McMillan	Combining Abstraction Refinement and SAT-Based Model Checking.	TACAS	2007	DBLP DOI BibTeX RDF
18	Jimson Mathew, Hafizur Rahaman 0001, Dhiraj K. Pradhan	Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set.	IOLTS	2007	DBLP DOI BibTeX RDF
18	Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell	Zero Cost Test Point Insertion Technique for Structured ASICs.	VLSI Design	2007	DBLP DOI BibTeX RDF
18	Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram	Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design.	DAC	2007	DBLP DOI BibTeX RDF
18	Yung-Chieh Lin, Feng Lu 0002, Kwang-Ting Cheng	Pseudofunctional testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
18	Seongmoon Wang, Srimat T. Chakradhar	A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
18	Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina	Testability Estimation Based on Controllability and Observability Parameters.	DSD	2006	DBLP DOI BibTeX RDF
18	Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito	Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters.	DFT	2006	DBLP DOI BibTeX RDF
18	Yu Huang 0005	On N-Detect Pattern Set Optimization.	ISQED	2006	DBLP DOI BibTeX RDF
18	Shweta Chary, Michael L. Bushnell	Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
18	Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya	An Efficient Scan Tree Design for Compact Test Pattern Set.	VLSI Design	2006	DBLP DOI BibTeX RDF
18	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Optimized reseeding by seed ordering and encoding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
18	Ahmad A. Al-Yamani, Edward J. McCluskey	Test chip experimental results on high-level structural test.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	test experiment, Structural test, VLSI test, complex gates
18	Bhushan Vaidya, Mehdi Baradaran Tahoori	Delay Test Generation with All Reachable Output Propagation and Multiple Excitations.	DFT	2005	DBLP DOI BibTeX RDF
18	Nisar Ahmed, Mohammad Tehranipoor	Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique.	DFT	2005	DBLP DOI BibTeX RDF
18	Intaik Park, Ahmad A. Al-Yamani, Edward J. McCluskey	Effective TARO Pattern Generation.	VTS	2005	DBLP DOI BibTeX RDF
18	Loganathan Lingappan, Niraj K. Jha	Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits.	VTS	2005	DBLP DOI BibTeX RDF
18	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
18	Octavian Petre, Hans G. Kerkhoff	Scan Test Strategy for Asynchronous-Synchronous Interfaces.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (GALS), asynchronous synchronous interface, synchronizers, scan test
18	Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew	Understanding Yield Losses in Logic Circuits.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
18	Feng Shi 0010, Yiorgos Makris	SPIN-TEST: automatic test pattern generation for speed-independent circuits.	ICCAD	2004	DBLP DOI BibTeX RDF
18	Pallav Gupta, Rui Zhang, Niraj K. Jha	An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks.	ICCD	2004	DBLP DOI BibTeX RDF
18	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	At-Speed Functional Verification of Programmable Devices.	DFT	2004	DBLP DOI BibTeX RDF
18	Davide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre	Yield Analysis of Logic Circuits.	VTS	2004	DBLP DOI BibTeX RDF
18	C. V. Krishna, Nur A. Touba	3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme.	VTS	2004	DBLP DOI BibTeX RDF
18	Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai	VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.	ITC	2004	DBLP DOI BibTeX RDF
18	Stephen Pateras	Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both.	ITC	2004	DBLP DOI BibTeX RDF
18	Manan Syal, Michael S. Hsiao, Sreejit Chakravarty	Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks.	ITC	2004	DBLP DOI BibTeX RDF
18	Alfred L. Crouch, John C. Potter, Jason Doege	AC Scan Path Selection for Physical Debugging.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
18	Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger	Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.	VTS	2003	DBLP DOI BibTeX RDF
18	Ahmad A. Al-Yamani, Edward J. McCluskey	Built-In Reseeding for Serial Bist.	VTS	2003	DBLP DOI BibTeX RDF
18	Seongmoon Wang, Srimat T. Chakradhar	A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs.	ITC	2003	DBLP DOI BibTeX RDF
18	Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski	Impact of Multiple-Detect Test Patterns on Product Quality.	ITC	2003	DBLP DOI BibTeX RDF
18	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	A New Functional Fault Model for FPGA Application-Oriented Testing.	DFT	2002	DBLP DOI BibTeX RDF
18	M. Enamul Amyeen, Irith Pomeranz, W. Kent Fuchs	Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits.	VTS	2002	DBLP DOI BibTeX RDF
18	Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich	Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.	VTS	2002	DBLP DOI BibTeX RDF	Microprocessor, Delay Testing
18	Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra	Program Slicing for Hierarchical Test Generation.	VTS	2002	DBLP DOI BibTeX RDF
18	Indradeep Ghosh, Masahiro Fujita	Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
18	Andreas G. Veneris, Magdy S. Abadir, Ivor Ting	Design rewiring based on diagnosis techniques.	ASP-DAC	2001	DBLP DOI BibTeX RDF
18	Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater	A SmartBIST Variant with Guaranteed Encoding.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
18	Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri	Timing Verification and Delay Test Generation for Hierarchical Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
18	Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao	Testing, Verification, and Diagnosis in the Presence of Unknowns.	VTS	2000	DBLP DOI BibTeX RDF
18	Indradeep Ghosh, Masahiro Fujita	Automatic test pattern generation for functional RTL circuits using assignment decision diagrams.	DAC	2000	DBLP DOI BibTeX RDF
18	Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici	FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy.	DATE	1999	DBLP DOI BibTeX RDF
18	Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara	A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
18	Sujit Dey, Anand Raghunathan, Kenneth D. Wagner	Design for Testability Techniques at the Behavioral and Register-Transfer Levels.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability
18	Li-C. Wang, Magdy S. Abadir	Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	high-level test generation, assertion test generation, design validation, logic verification, symbolic trajectory evaluation
18	Shing-Wu Tung, Jing-Yang Jou	Verification Pattern Generation for Core-Based Design Using Port Order Fault Model.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
18	Michael L. Bushnell, John Giraldi	A Functional Decomposition Method for Redundancy Identification and Test Generation.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	redundancy identification, logic testing, automatic test generation, backtracing
18	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda	New static compaction techniques of test sequences for sequential circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
18	Liang-Chi Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	High Quality Robust Tests for Path Delay Faults.	VTS	1997	DBLP DOI BibTeX RDF	test generation, fault modeling, delay test, robust test
18	Uwe Gläser, Heinrich Theodor Vierhaus	Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
18	Kwang-Ting Cheng	Gate-level test generation for sequential circuits.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	testing, automatic test generation, IC testing, sequential circuit test generation
18	Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits.	PPSN	1996	DBLP DOI BibTeX RDF
18	Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin	Redundancy Identification Using Transitive Closure.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
18	Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel	Enhancing high-level control-flow for improved testability.	ICCAD	1996	DBLP DOI BibTeX RDF	synthesis for testability, at-speed testing, testability measures, test point insertion, high-level description
18	Kee Sup Kim, Charles R. Kime	Partial scan flip-flop selection by use of empirical testability.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	scan flip-flop selection, serial scan, design for testability, testability, partial scan
18	Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal	Toward massively parallel automatic test generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
18	Torsten Grüning, Udo Mahlstedt, Wilfried Daehn, Cengiz Özcan	Accelerated test pattern generation by cone-oriented circuit partitioning.	EURO-DAC	1990	DBLP DOI BibTeX RDF