Search results for "CMP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi	Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.	ASP-DAC	2009	DBLP DOI BibTeX RDF
19	Jin Sun 0006, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang	NBTI aware workload balancing in multi-core systems.	ISQED	2009	DBLP DOI BibTeX RDF
19	Aditya P. Karmarkar, Xiaopeng Xu, Victor Moroz, Greg Rollins, Xiao Lin	Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology.	ISQED	2009	DBLP DOI BibTeX RDF
19	A. Elyada, Ran Ginosar, Uri C. Weiser	Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
19	Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang 0007, Yan Tang	Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor.	DATE	2008	DBLP DOI BibTeX RDF
19	John Cieslewicz, Kenneth A. Ross	Data partitioning on chip multiprocessors.	DaMoN	2008	DBLP DOI BibTeX RDF
19	Yang Ding, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin	A helper thread based EDP reduction scheme for adapting application execution in CMPs.	IPDPS	2008	DBLP DOI BibTeX RDF
19	Luis Angel D. Bathen, Nikil D. Dutt, Sudeep Pasricha	A framework for memory-aware multimedia application mapping on chip-multiprocessors.	ESTIMedia	2008	DBLP DOI BibTeX RDF
19	Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud	Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	design for manufacturability, dummy fill
19	Jae-Seok Yang, Andrew R. Neureuther	Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner.	ISQED	2008	DBLP DOI BibTeX RDF	worst corner, noise, crosstalk, variation, signal integrity
19	Antonio Flores, Manuel E. Acacio, Juan L. Aragón	Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs.	ICPP	2008	DBLP DOI BibTeX RDF
19	Carolina Bonacic, Carlos García 0001, Mauricio Marín, Manuel Prieto 0001, Francisco Tirado, Cesar Vicente	Improving Search Engines Performance on Multithreading Processors.	VECPAR	2008	DBLP DOI BibTeX RDF
19	Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni	Design Exploration of Optical Interconnection Networks for Chip Multiprocessors.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics
19	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Utilizing shared data in chip multiprocessors with the nahalal architecture.	SPAA	2008	DBLP DOI BibTeX RDF	chip multiprocessors, cache memories
19	Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-Hsin S. Lee	Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	MESI protocol, internal and external snoops, self-modifying code, chip multiprocessors
19	Guangyu Chen, Feihui Li, Seung Woo Son 0001, Mahmut T. Kandemir	Application mapping for chip multiprocessors.	DAC	2008	DBLP DOI BibTeX RDF	NoC (Network on Chip), compilers, power optimization, chip multiprocessing, application mapping
19	Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
19	Michael Gschwind	The Cell Broadband Engine: Exploiting Multiple Levels of Parallelism in a Chip Multiprocessor.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	compute-transfer parallelism, multi-level application parallelism, Chip multiprocessor, Cell Broadband Engine, heterogeneous chip multiprocessor
19	James Laudon, Lawrence Spracklen	The Coming Wave of Multithreaded Chip Multiprocessors.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	performance, parallel programming, multithreading, Chip multiprocessing
19	Niti Madan, Rajeev Balasubramonian	Power Efficient Approaches to Redundant Multithreading.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	redundant multi-threading (RMT), dynamic frequency scaling, Reliability, power, soft errors, transient faults, heterogeneous chip multiprocessors
19	Assaf Shacham, Keren Bergman, Luca P. Carloni	On the Design of a Photonic Network-on-Chip.	NOCS	2007	DBLP DOI BibTeX RDF
19	Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara	Power-Aware Compiler Controllable Chip Multiprocessor.	PACT	2007	DBLP DOI BibTeX RDF
19	Guangyu Chen, Feihui Li, Mahmut T. Kandemir	Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime Approach.	PACT	2007	DBLP DOI BibTeX RDF
19	Ronald G. Dreslinski, Bo Zhai, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester	An Energy Efficient Parallel Architecture Using Near Threshold Operation.	PACT	2007	DBLP DOI BibTeX RDF
19	Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks	Understanding voltage variations in chip multiprocessors using a distributed power-delivery network.	DATE	2007	DBLP DOI BibTeX RDF
19	Onur Mutlu, Thomas Moscibroda	Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors.	MICRO	2007	DBLP DOI BibTeX RDF
19	Guilherme Ottoni, David I. August	Global Multi-Threaded Instruction Scheduling.	MICRO	2007	DBLP DOI BibTeX RDF
19	Subarna Sinha, Jianfeng Luo, Charles C. Chiang	Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process.	ASP-DAC	2007	DBLP DOI BibTeX RDF
19	Jisheng Zhao, Matthew Horsnell, Ian Rogers, Andrew Dinn, Chris C. Kirkham, Ian Watson	Optimizing Chip Multiprocessor Work Distribution Using Dynamic Compilation.	Euro-Par	2007	DBLP DOI BibTeX RDF	Automatic parallelization, dynamic execution, feedback-directed optimization
19	Ayaz Ali, S. Lennart Johnsson, Jaspal Subhlok	Scheduling FFT computation on SMP and multicore systems.	ICS	2007	DBLP DOI BibTeX RDF	fast Fourier transform, shared memory, multicore, automatic parallelization, automatic performance tuning
19	Hongbo Zeng, Kun Huang, Ming Wu, Weiwu Hu	Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
19	Michela Becchi, Mark A. Franklin, Patrick Crowley	Performance/area efficiency in chip multiprocessors with micro-caches.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	networking workload, chip multiprocessor, cache hierarchies
19	Tianzhou Chen, Guobing Chen, Hongjun Dai, Qingsong Shi	A function-based on-chip communication design in the heterogeneous multi-core architecture.	MUE	2007	DBLP DOI BibTeX RDF
19	Fengguang Song, Shirley Moore, Jack J. Dongarra	L2 Cache Modeling for Scientific Applications on Chip Multi-Processors.	ICPP	2007	DBLP DOI BibTeX RDF	cache performance modeling, architecture, chip multi-processor, multi-threaded programming
19	Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykumar	Speculative thread decomposition through empirical optimization.	PPoPP	2007	DBLP DOI BibTeX RDF	empirical search, chip multiprocessor, decomposition, multi-core, thread-level speculation
19	Ali-Reza Adl-Tabatabai, Christos Kozyrakis, Bratin Saha	Transactional programming in a multi-core environment.	PPoPP	2007	DBLP DOI BibTeX RDF	parallel programming, transactional memory, atomicity, hardware architecture
19	Munkang Choi, Linda S. Milor	Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
19	Myungho Lee, Yeonseung Ryu, Sugwon Hong, Chungki Lee	Performance Impact of Resource Conflicts on Chip Multi-processor Servers.	PARA	2006	DBLP DOI BibTeX RDF
19	Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe	Reunion: Complexity-Effective Multicore Redundancy.	MICRO	2006	DBLP DOI BibTeX RDF
19	Jian Li 0059, José F. Martínez	Dynamic power-performance adaptation of parallel computation on chip multiprocessors.	HPCA	2006	DBLP DOI BibTeX RDF
19	Pengyong Ma, Shuming Chen	MID: a Novel Coherency Protocol in Chip Multiprocessor.	CIT	2006	DBLP DOI BibTeX RDF
19	Tomasz Madajczak, Henryk Krawczyk	Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs.	PARELEC	2006	DBLP DOI BibTeX RDF
19	Michela Becchi, Patrick Crowley	Dynamic thread assignment on heterogeneous multiprocessor architectures.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	simulation, chip multiprocessor, heterogeneous architectures
19	Björn Jäger, Mario Porrmann, Ulrich Rückert 0001	Bio-inspired massively parallel architectures for nanotechnologies.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Pavlos Petoumenos, Georgios Keramidas, Håkan Zeffer, Stefanos Kaxiras, Erik Hagersten	Modeling Cache Sharing on Chip Multiprocessor Architectures.	IISWC	2006	DBLP DOI BibTeX RDF
19	Suzanne Rivoire, Rebecca Schultz, Tomofumi Okuda, Christos Kozyrakis	Vector Lane Threading.	ICPP	2006	DBLP DOI BibTeX RDF
19	Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter	Interconnect-Aware Coherence Protocols for Chip Multiprocessors.	ISCA	2006	DBLP DOI BibTeX RDF
19	Engin Ipek, Sally A. McKee, Rich Caruana, Bronis R. de Supinski, Martin Schulz 0001	Efficiently exploring architectural design spaces via predictive modeling.	ASPLOS	2006	DBLP DOI BibTeX RDF	sensitivity studies, artificial neural networks, performance prediction, design space exploration
19	Xiaoqi Yang 0003, Qilong Zheng, Guoliang Chen 0001, Zhen Yao	Reverse Compilation for Speculative Parallel Threading.	PDCAT	2006	DBLP DOI BibTeX RDF
19	Jian Li 0059, José F. Martínez	Power-performance considerations of parallel computing on chip multiprocessors.	ACM Trans. Archit. Code Optim.	2005	DBLP DOI BibTeX RDF	Voltage/frequency scaling, granularity, parallel efficiency
19	Ben Wun, Jeremy Buhler, Patrick Crowley	Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor.	IEEE PACT	2005	DBLP DOI BibTeX RDF
19	Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin	Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture.	HPCA	2005	DBLP DOI BibTeX RDF
19	Lawrence Spracklen, Santosh G. Abraham	Chip Multithreading: Opportunities and Challenges.	HPCA	2005	DBLP DOI BibTeX RDF
19	Francisco J. Villa, Manuel E. Acacio, José M. García 0001	Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture.	HPCC	2005	DBLP DOI BibTeX RDF
19	Weidong Shi, Hsien-Hsin S. Lee, Guofei Gu, Laura Falk, Trevor N. Mudge, Mrinmoy Ghosh	An Intrusion-Tolerant and Self-Recoverable Network Service System Using A Security Enhanced Chip Multiprocessor.	ICAC	2005	DBLP DOI BibTeX RDF	Intrusion-tolerant computing, survivable service, buffer overflow, self-healing, rootkits, chip multi processor
19	Philo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, Douglas W. Clark	Coordinated, distributed, formal energy management of chip multiprocessors.	ISLPED	2005	DBLP DOI BibTeX RDF	power, dynamic voltage scaling
19	Björn Jäger, Jörg-Christian Niemann, Ulrich Rückert 0001	Analytical approach to massively parallel architectures for nanotechnologies.	ASAP	2005	DBLP DOI BibTeX RDF
19	Kyriakos Stavrou, Pedro Trancoso	TSIC: Thermal Scheduling Simulator for Chip Multiprocessors.	Panhellenic Conference on Informatics	2005	DBLP DOI BibTeX RDF
19	Michael Zhang, Krste Asanovic	Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors.	ISCA	2005	DBLP DOI BibTeX RDF
19	Seongbeom Kim, Dhruba Chandra, Yan Solihin	Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture.	IEEE PACT	2004	DBLP DOI BibTeX RDF
19	Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir	Optimizing Bus Energy Consumption of On-Chip Multiprocessors Using Frequent Values.	PDP	2004	DBLP DOI BibTeX RDF	On-chip Multiprocessors, Power Optimization, Value Locality
19	Mladen Nikitovic, Mats Brorsson	A Low Power Strategy for Future Mobile Terminals.	DATE	2004	DBLP DOI BibTeX RDF
19	Tero Rissa, Peter Y. K. Cheung, Wayne Luk	SoftSONIC: A Customisable Modular Platform for Video Applications.	FPL	2004	DBLP DOI BibTeX RDF
19	Ken W. Batcher, Robert A. Walker 0001	Cluster miss prediction with prefetch on miss for embedded CPU instruction caches.	CASES	2004	DBLP DOI BibTeX RDF	hiding memory latency, embedded systems, networking, WCET, cache design, cache prefetch
19	Yu Chen 0005, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky	Area fill synthesis for uniform layout density.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
19	G. Ramalingam, Alex Varshavsky, John Field, Deepak Goyal, Shmuel Sagiv	Deriving Specialized Program Analyses for Certifying Component-Client Conformance.	PLDI	2002	DBLP DOI BibTeX RDF	model checking, static analysis, abstract interpretation, software components, predicate abstraction
19	Jaehyuk Huh 0001, Doug Burger, Stephen W. Keckler	Exploring the Design Space of Future CMPs.	IEEE PACT	2001	DBLP DOI BibTeX RDF
19	Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha P. Chandrakasan, Rakesh Vallishayee, Sani R. Nassif	A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance.	DAC	2000	DBLP DOI BibTeX RDF
19	Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky	Filling algorithms and analyses for layout density control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
19	Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky	New Multilevel and Hierarchical Algorithms for Layout Density Control.	ASP-DAC	1999	DBLP DOI BibTeX RDF
19	Lance Hammond, Mark Willey, Kunle Olukotun	Data Speculation Support for a Chip Multiprocessor.	ASPLOS	1998	DBLP DOI BibTeX RDF
18	Renjie Liu, Xiaopeng Yang, Jiancheng Liao, Xiaodong Qu, Peng Yin, Aly E. Fathy	Parameter Inversion Method of Multilayered Media Based on Off-Grid Sparse CMP Model With Refined Orthogonal Matching Pursuit.	IEEE Trans. Geosci. Remote. Sens.	2024	DBLP DOI BibTeX RDF
18	Zhuoyuan Wu, Yuping Wang, Hengbo Ma, Zhaowei Li, Hang Qiu 0001, Jiachen Li 0001	CMP: Cooperative Motion Prediction with Multi-Agent Communication.	CoRR	2024	DBLP DOI BibTeX RDF
18	Jonghyun Oh, Young-Ha Hwang, Jun-Eun Park, Mingoo Seok, Deog-Kyoon Jeong	An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Changyu Zhou, Motoyuki Sato	MUSIC-Based Super-Resolution CMP Velocity-Depth Analysis for Multilayer Cases.	IEEE Geosci. Remote. Sens. Lett.	2023	DBLP DOI BibTeX RDF
18	Qing Zhang 0008, Huajie Huang, Jizuo Li, Yuhang Zhang, Yongfu Li 0002	CmpCNN: CMP Modeling with Transfer Learning CNN Architecture.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
18	Hendrik Brockhaus, David von Oheimb, John Gray	Certificate Management Protocol (CMP) Updates.	RFC	2023	DBLP DOI BibTeX RDF
18	Hendrik Brockhaus, Hans Aschauer, Mike Ounsworth, John Gray	Certificate Management Protocol (CMP) Algorithms.	RFC	2023	DBLP DOI BibTeX RDF
18	Hendrik Brockhaus, David von Oheimb, Steffen Fries	Lightweight Certificate Management Protocol (CMP) Profile.	RFC	2023	DBLP DOI BibTeX RDF
18	Shalabh Jain, Pradeep Pappachan, Jorge Guajardo, Sven Trieflinger, Indrasen Raghupatruni, Thomas Huber	CMP-SiL: Confidential Multi Party Software-in-the-Loop Simulation Frameworks.	ISQED	2023	DBLP DOI BibTeX RDF
18	Kaiwei Zou, Ying Wang 0001, Long Cheng 0003, Songyun Qu, Huawei Li 0001, Xiaowei Li 0001	CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
18	Nivedita Bijlani, Oscar Mendez Maldonado, Samaneh Kouchaki	G-CMP: Graph-enhanced Contextual Matrix Profile for unsupervised anomaly detection in sensor-based remote health monitoring.	CoRR	2022	DBLP DOI BibTeX RDF
18	Dijana Mosic, Predrag S. Stanimirovic, Vasilios N. Katsikis	Properties of the CMP inverse and its computation.	Comput. Appl. Math.	2022	DBLP DOI BibTeX RDF
18	Nivedita Bijlani, Oscar Mendez Maldonado, Samaneh Kouchaki	G-CMP: Graph-enhanced Contextual Matrix Profile for unsupervised anomaly detection in sensor-based remote health monitoring.	BMVC	2022	DBLP BibTeX RDF
18	Zilian Qu, Wensong Wang, Xueli Li, Qi Li, Yuanjin Zheng	Measurement and Error Analysis of Cu Film Thickness With Ta Barrier Layer on Wafer for CMP Application.	IEEE Trans. Instrum. Meas.	2021	DBLP DOI BibTeX RDF
18	Junzhe Cai, Changhao Yan, Yudong Tao, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng 0001	A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2021	DBLP DOI BibTeX RDF
18	Junzhe Cai, Changhao Yan, Yuzhe Ma, Bei Yu 0001, Dian Zhou, Xuan Zeng 0001	NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis.	DAC	2021	DBLP DOI BibTeX RDF
18	José M. Cecilia, José M. García 0001	Re-engineering the ant colony optimization for CMP architectures.	J. Supercomput.	2020	DBLP DOI BibTeX RDF
18	Baolin Tian, Junsheng Zeng, Baoqing Meng, Qian Chen, Xiaohu Guo, Kun Xue	Compressible multiphase particle-in-cell method (CMP-PIC) for full pattern flows of gas-particle system.	J. Comput. Phys.	2020	DBLP DOI BibTeX RDF
18	Junjun Zhang, Mei Yu 0001, Gangyi Jiang, Yubin Qi	CMP-based saliency model for stereoscopic omnidirectional images.	Digit. Signal Process.	2020	DBLP DOI BibTeX RDF
18	Bingxue Wang, Hongmei Du, Haifeng Ma	Perturbation bounds for DMP and CMP inverses of tensors via Einstein product.	Comput. Appl. Math.	2020	DBLP DOI BibTeX RDF
18	Jonghyun Oh, Jun-Eun Park, Young-Ha Hwang, Deog-Kyoon Jeong	25.2 A 480mA Output-Capacitor-Free Synthesizable Digital LDO Using CMP- Triggered Oscillator and Droop Detector with 99.99% Current Efficiency, 1.3ns Response Time, and 9.8A/mm2 Current Density.	ISSCC	2020	DBLP DOI BibTeX RDF
18	Guillaume Aupy, Anne Benoit, Brice Goglin, Loïc Pottier, Yves Robert	Co-scheduling HPC workloads on cache-partitioned CMP platforms.	Int. J. High Perform. Comput. Appl.	2019	DBLP DOI BibTeX RDF
18	Mihee Uhm, Jin-Moo Lee, Jieun Lee, Jung Han Lee, Sungju Choi, Byung-Gook Park, Dong Myong Kim, Sung-Jin Choi, Hyun-Sun Mo, Yong-Joo Jeong, Dae Hwan Kim	Ultrasensitive Electrical Detection of Hemagglutinin for Point-of-Care Detection of Influenza Virus Based on a CMP-NANA Probe and Top-Down Processed Silicon Nanowire Field-Effect Transistors.	Sensors	2019	DBLP DOI BibTeX RDF
18	Yuancheng Li, Jiaqi Shi	CRbS: A Code Reordering Based Speeding-up Method of Irregular Loops on CMP.	ASAP	2019	DBLP DOI BibTeX RDF
18	Karthik Sangaiah, Michael Lui, Radhika Jagtap, Stephan Diestelhorst, Siddharth Nilakantan, Ankit More, Baris Taskin, Mark Hempstead	SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads.	ACM Trans. Archit. Code Optim.	2018	DBLP DOI BibTeX RDF
18	Jialun Cao, Yongjian Li, Jun Pang 0001	L-CMP: an automatic learning-based parameterized verification tool.	ASE	2018	DBLP DOI BibTeX RDF
18	Guillaume Aupy, Anne Benoit, Brice Goglin, Loic Pottier, Yves Robert	Co-Scheduling HPC Workloads on Cache-Partitioned CMP Platforms.	CLUSTER	2018	DBLP DOI BibTeX RDF
18	Shaahin Angizi, Zhezhi He, Adnan Siraj Rakin, Deliang Fan	CMP-PIM: an energy-efficient comparator-based processing-in-memory neural network accelerator.	DAC	2018	DBLP DOI BibTeX RDF
18	Sizhao Li, Donghui Guo	Cache Coherence Scheme for HCS-Based CMP and Its System Reliability Analysis.	IEEE Access	2017	DBLP DOI BibTeX RDF