Search results for "SRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
27	Alexandre Ney, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Slow write driver faults in 65nm SRAM technology: analysis and March test solution.	DATE	2007	DBLP DOI BibTeX RDF
27	Luca Sterpone, Massimo Violante	Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs.	ETS	2007	DBLP DOI BibTeX RDF
27	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew	Soft Error Mitigation in Switch Modules of SRAM-based FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Olivier Thomas, Marina Reyboz, Marc Belleville	Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Bastien Giraud, Amara Amara, Andrei Vladimirescu	A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Riaz Naseer, Younes Boulghassoul, Jeff Draper, Sandeepan DasGupta, Art Witulski	Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio	SEU mitigation for sram-based fpgas through dynamic partial reconfiguration.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fault detection, SEU, partial dynamic reconfiguration
27	Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson	Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.	ISQED	2007	DBLP DOI BibTeX RDF
27	Tamer Cakici, Keejong Kim, Kaushik Roy 0001	FinFET Based SRAM Design for Low Standby Power Applications.	ISQED	2007	DBLP DOI BibTeX RDF
27	Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta	Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design.	VLSI Design	2007	DBLP DOI BibTeX RDF
27	Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang	A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology.	VLSI Design	2007	DBLP DOI BibTeX RDF
27	Jorge García-Vidal, Maribel March, Llorenç Cerdà, Jesús Corbal, Mateo Valero	A DRAM/SRAM Memory Scheme for Fast Packet Buffers.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	high-performance memory systems, Router architecture, storage schemes, packet buffers
27	Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali	Testing embedded RAM modules in SRAM-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
27	Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou	SRAM Cell Current in Low Leakage Design.	MTDT	2006	DBLP DOI BibTeX RDF
27	Derek Ho, Kris Iniewski, Soraya Kasnavi, A. Ivanov, S. Natarajan	Ultra-low power 90nm 6T SRAM cell for wireless sensor network applications.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif	SRAM Local Bit Line Access Failure Analyses.	ISQED	2006	DBLP DOI BibTeX RDF
27	Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson	Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.	ISQED	2006	DBLP DOI BibTeX RDF
27	Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar	RG-SRAM: A Low Gate Leakage Memory Design.	ISVLSI	2005	DBLP DOI BibTeX RDF
27	Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
27	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.	IPDPS	2005	DBLP DOI BibTeX RDF
27	Rabiul Islam, Adam Brand, Dave Lippincott	Low power SRAM techniques for handheld products.	ISLPED	2005	DBLP DOI BibTeX RDF	back-bias, bitcell, memory, leakage
27	Olivier Thomas, Amara Amara	Ultra low voltage design considerations of SOI SRAM memory cells.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
27	Matteo Sonza Reorda, Luca Sterpone, Massimo Violante	Efficient Estimation of SEU Effects in SRAM-Based FPGAs.	IOLTS	2005	DBLP DOI BibTeX RDF
27	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan	Data Retention Fault in SRAM Memories: Analysis and Detection Procedures.	VTS	2005	DBLP DOI BibTeX RDF
27	Yen-Jen Chang, Feipei Lai, Chia-Lin Yang	Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
27	M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, Alessandro Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin	Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA.	DATE	2004	DBLP DOI BibTeX RDF
27	Yi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang	A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
27	Lilian Bossuet, Guy Gogniat, Wayne P. Burleson	Dynamically Configurable Security for SRAM FPGA Bitstreams.	IPDPS	2004	DBLP DOI BibTeX RDF
27	Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Statistical design and optimization of SRAM cell for yield enhancement.	ICCAD	2004	DBLP DOI BibTeX RDF
27	Benjamin M. Mauck, Vishnumohan Ravichandran, Usman Azeez Mughal	A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis.	ITC	2004	DBLP DOI BibTeX RDF
27	Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali	Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs.	PRDC	2004	DBLP DOI BibTeX RDF
27	Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin	Analyzing Soft Errors in Leakage Optimized SRAM Design.	VLSI Design	2003	DBLP DOI BibTeX RDF
27	Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin	A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	memory BIST, memory diagnostics, memory testing, RAM, semiconductor memory
27	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
27	Robert Gibbins, R. Dean Adams, Thomas J. Eckenrode, Michael Ouellette, Yuejian Wu	Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch.	MTDT	2002	DBLP DOI BibTeX RDF
27	Mario R. Casu, Philippe Flatresse	Converting an Embedded Low-Power SRAM from Bulk to PD-SOI.	MTDT	2002	DBLP DOI BibTeX RDF
27	Hong-Yi Huang, Hsuan-Yi Su	Low-power 2P2N SRAM with column hidden refresh.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
27	Robert K. Grube, Qi Wang, Sung-Mo Kang	Design limitations in deep sub-0.1µm CMOS SRAM.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	GIDL, on-chip cache, tunneling currents, gate leakage
27	Raymond J. Sung, John C. Koob, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn	Design of an Embedded Fully-Depleted SOI SRAM.	MTDT	2001	DBLP DOI BibTeX RDF
27	Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi	Testing SRAM-Based Content Addressable Memories.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	March C algorithm, fault detection, fault modeling, memory testing, Content addressable memory
27	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	SRAM-Based FPGAs: Testing the Embedded RAM Modules.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	FPGA, test, ATPG, RAM, iterative testing
27	Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos	An analytical, transistor-level energy model for SRAM-based caches.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
27	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	SRAM-based FPGA's: testing the LUT/RAM modules.	ITC	1998	DBLP DOI BibTeX RDF
27	Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa	A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
26	Zhe Feng 0002, Naifeng Jing, GengSheng Chen, Yu Hu 0002, Lei He 0001	IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs.	FPL	2011	DBLP DOI BibTeX RDF	in-place, soft error, don't care, mitigation, SRAM-based FPGA
26	Darsen D. Lu, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu	Compact Modeling of Variation in FinFET SRAM Cells.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF	multigate MOSFETs, variability, design for manufacturing, SRAM, design and test, FinFET, compact modeling
26	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Impact of Resistive-Bridging Defects in SRAM Core-Cell.	DELTA	2010	DBLP DOI BibTeX RDF	core-cell, resistive-bridging defects, SRAM
26	Amara Amara, Bastien Giraud, Olivier Thomas	An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology.	DELTA	2010	DBLP DOI BibTeX RDF	SRAM cell, Planar Double-Gate (DG), Fully Depleted SOI (FD-SOI), read and write tradeoffs, Ultra Low Voltage (ULV)
26	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.	VLSI Design	2010	DBLP DOI BibTeX RDF	Nanoscale CMOS, SRAM, Power Dissipation, Static Noise Margin
26	Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj	FinFET SRAM Design.	VLSI Design	2010	DBLP DOI BibTeX RDF	variability, SRAM, FinFET, Double gate
26	Ghazanfar Asadi, Mehdi Baradaran Tahoori	Soft error rate estimation and mitigation for SRAM-based FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	soft error rate estimation, error recovery, SRAM-based FPGA
26	Martin Margala	Low-Power SRAM Circuit Design.	MTDT	1999	DBLP DOI BibTeX RDF	design, VLSI, low-power, SRAM, low-voltage
26	V. Kim, T. Chen	Assessing SRAM test coverage for sub-micron CMOS technologies.	VTS	1997	DBLP DOI BibTeX RDF	submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits
24	Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita	High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dopant-segregated schottky transistor, nonvolatile configurable memory
24	Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili	An energy efficient cache design using spin torque transfer (STT) RAM.	ISLPED	2010	DBLP DOI BibTeX RDF	(STT)RAM, memory technologies, cache design
24	Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen 0001, Hai Li 0001	Tolerating process variations in large, set-associative caches: The buddy cache.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	caches, Processor architectures, fault recovery, memory structures
24	Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Jian Li 0059, Yiran Chen 0001	A novel architecture of the 3D stacked MRAM L2 cache for CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
24	Roberto Cornacchia, Sándor Héman, Marcin Zukowski, Arjen P. de Vries, Peter A. Boncz	Flexible and efficient IR using array databases.	VLDB J.	2008	DBLP DOI BibTeX RDF	Array databases, Information retrieval, Query optimization, Database compression
24	Hisashige Ando, Ryuji Kan, Yoshiharu Tosaka, Keiji Takahisa, Kichiji Hatanaka	Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor.	DSN	2008	DBLP DOI BibTeX RDF
24	Sherif A. Tawfik, Volkan Kursun	Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
24	Sherif A. Tawfik, Volkan Kursun	Dynamic wordline voltage swing for low leakage and stable static memory banks.	ISCAS	2008	DBLP DOI BibTeX RDF
24	Tony Tae-Hyoung Kim, Jason Liu 0004, John Keane 0001, Chris H. Kim	Circuit techniques for ultra-low power subthreshold SRAMs.	ISCAS	2008	DBLP DOI BibTeX RDF
24	Sandeep S. Kumar, Jorge Guajardo, Roel Maes, Geert Jan Schrijen, Pim Tuyls	The Butterfly PUF: Protecting IP on every FPGA.	HOST	2008	DBLP DOI BibTeX RDF
24	Rajani Kuchipudi, Hamid Mahmoodi	Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS.	ISQED	2007	DBLP DOI BibTeX RDF
24	Nian-Feng Tzeng	Routing Table Partitioning for Speedy Packet Lookups in Scalable Routers.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	line cards, prefix matching search, routing table lookups, Caches, interconnects, routers, tries, forwarding engines
24	Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann	Memory performance prediction for high-performance microprocessors at deep submicrometer technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
24	Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Myoung-min Sim, Soonhoi Ha	Dynamic code overlay of SDF-modeled programs on low-end embedded systems.	DATE	2006	DBLP DOI BibTeX RDF
24	Qing K. Zhu	Memory Generation and Power Distribution In SOC.	DSD	2006	DBLP DOI BibTeX RDF
24	Tianzhou Chen, Wei Hu 0001, Yi Lian	Power-Efficient Microkernel of Embedded Operating System on Chip.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	power-efficient, microkernel, embedded operating system
24	Jason E. Miller, Anant Agarwal	Software-based instruction caching for embedded processors.	ASPLOS	2006	DBLP DOI BibTeX RDF	instruction cache, chaining, software caching
24	Sailesh Kumar, Jonathan S. Turner, Patrick Crowley	Addressing Queuing Bottlenecks at High Speeds.	Hot Interconnects	2005	DBLP DOI BibTeX RDF
24	Sumesh Udayakumaran, Rajeev Barua	Compiler-decided dynamic memory allocation for scratch-pad based embedded systems.	CASES	2003	DBLP DOI BibTeX RDF	embedded systems, compiler, memory allocation, scratch-pad
24	Nian-Feng Tzeng	Hardware-Assisted Design for Fast Packet Forwarding in Parallel Routers.	ICPP	2003	DBLP DOI BibTeX RDF
24	Oren Avissar, Rajeev Barua, Dave Stewart	An optimal memory allocation scheme for scratch-pad-based embedded systems.	ACM Trans. Embed. Comput. Syst.	2002	DBLP DOI BibTeX RDF	embedded, Memory, heterogeneous, storage, allocation
24	Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou	Energy recovering static memory.	ISLPED	2002	DBLP DOI BibTeX RDF	adiabatic circuitry, charge recovery, cache memories, on-chip memories, low-power computing, low-energy design
24	Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Akihito Tohata, Nobuaki Otsuka	DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs.	ITC	2002	DBLP DOI BibTeX RDF
24	Oren Avissar, Rajeev Barua, Dave Stewart	Heterogeneous memory management for embedded systems.	CASES	2001	DBLP DOI BibTeX RDF	embedded, memory, heterogeneous, storage
24	Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie	An efficient BIST method for testing of embedded SRAMs.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
24	Khoan Truong	A Simple Built-In Self Test For Dual Ported SRAMs.	MTDT	2000	DBLP DOI BibTeX RDF
24	Luca Benini, Alberto Macii, Massimo Poncino	A recursive algorithm for low-power memory partitioning.	ISLPED	2000	DBLP DOI BibTeX RDF
24	Vicente Baena Lecuyer, M. A. Aguirre, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo, Julio Faura	Decoder-driven switching matrices in multicontext FPGAs: area reduction and their effect on routability.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
24	Leonidas I. Kontothanassis, Rabin A. Sugumar, Greg Faanes, James E. Smith 0001, Michael L. Scott	Cache performance in vector supercomputers.	SC	1994	DBLP DOI BibTeX RDF
24	Ron Bourassa, Tim Coffman, Joe Brewer	Ultra large scale static rams.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
23	Björn Osterloh, Harald Michalik, Björn Fiethe	SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs.	ARCS	2009	DBLP DOI BibTeX RDF	SoCWire, dynamic reconfigurable system, Sytem-on-Chip, Network-on-Chip, SRAM-based FPGA, VMC
23	Weirong Jiang, Viktor K. Prasanna	Field-split parallel architecture for high performance multi-match packet classification using FPGAs.	SPAA	2009	DBLP DOI BibTeX RDF	multi-match packet classification, fpga, sram, nids
23	Weirong Jiang, Viktor K. Prasanna	Multi-terabit ip lookup using parallel bidirectional pipelines.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	ip lookup, terabit, pipeline, sram, bidirectional
23	Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev	Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model.	ISQED	2008	DBLP DOI BibTeX RDF	critical charge, process variation, Soft error, SRAM
23	Franz X. Ruckerbauer, Georg Georgakos	Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena.	IOLTS	2007	DBLP DOI BibTeX RDF	NSER, ASER, multi-bit upset, soft errors and radiation, CMOS, SRAM, SEU
23	Kiyoo Itoh 0001, Masanao Yamaoka, Takayuki Kawahara	Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate
23	Meng-Fan Chang, Kuei-Ann Wen	Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	supply noise, SRAM, substrate noise, ROM
23	Prassanna Sithambaram, Alberto Macii, Enrico Macii	Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	DBL, DWL, partitioning, embedded, memories, SRAM, application-specific
23	Stefanos Kaxiras, Polychronis Xekalakis	4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors.	ISLPED	2004	DBLP DOI BibTeX RDF	4T SRAM, architecture, sensor, leakage, temperature
23	Baosheng Wang, Josh Yang, André Ivanov	Reducing Test Time of Embedded SRAMs.	MTDT	2003	DBLP DOI BibTeX RDF	Embedded SRAM test, Inductive Fault Analysis, Memory Redundancy, March Test, Test Time
23	Kiyoo Itoh 0001	Low-voltage memories for power-aware systems.	ISLPED	2002	DBLP DOI BibTeX RDF	DRAM and SRAM cells, gain cells, gate-source/substrate-source back-biasing, memory-rich architectures, multi-Vr, non-volatile RAMs, on-chip voltage converters, peripheral circuits, subthreshold current, testing
23	Amit Agarwal 0001, Hai Li, Kaushik Roy 0001	DRG-cache: a data retention gated-ground cache for low power.	DAC	2002	DBLP DOI BibTeX RDF	gated-ground, low leakage cache, SRAM
23	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara	Testing for the programming circuit of LUT-based FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	programming circuit, control circuit, configuration memory cell array, FPGA, fault model, SRAM, shift registers, shift registers, look-up table
23	Wei Liang Huang, Fred J. Meyer, Fabrizio Lombardi	Multiple fault detection in logic resources of FPGAs.	DFT	1997	DBLP DOI BibTeX RDF	logic resources, AND tree, OR tree, CLB test generation, field programmable gate arrays, fault model, configurability, testability, programmability, multiple fault detection, SRAM-based FPGA
23	Ad J. van de Goor, Yervant Zorian	Effective march algorithms for testing single-order addressed memories.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Read/Write memories, single-address order, single-order addressed memory, SRAM, memory testing, March test
22	Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda	A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
22	Seyed Hassan Hadi Nemati, Nima Eslami, Mohammad Hossein Moaiyeri	A Hybrid SRAM/RRAM In-Memory Computing Architecture Based on a Reconfigurable SRAM Sense Amplifier.	IEEE Access	2023	DBLP DOI BibTeX RDF