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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 989 occurrences of 488 keywords
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Results
Found 3882 publication records. Showing 3880 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
27 | Alexandre Ney, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
Slow write driver faults in 65nm SRAM technology: analysis and March test solution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 528-533, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Luca Sterpone, Massimo Violante |
Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007, pp. 159-164, 2007, IEEE Computer Society, 978-0-7695-2827-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew |
Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 141-144, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Olivier Thomas, Marina Reyboz, Marc Belleville |
Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 2778-2781, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Bastien Giraud, Amara Amara, Andrei Vladimirescu |
A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3022-3025, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Riaz Naseer, Younes Boulghassoul, Jeff Draper, Sandeepan DasGupta, Art Witulski |
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1879-1882, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio |
SEU mitigation for sram-based fpgas through dynamic partial reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 55-60, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
fault detection, SEU, partial dynamic reconfiguration |
27 | Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson |
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 185-191, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Tamer Cakici, Keejong Kim, Kaushik Roy 0001 |
FinFET Based SRAM Design for Low Standby Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 127-132, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Deblina Sarkar, Samiran Ganguly, Deepanjan Datta, A. Ananda Prasad Sarab, Sudeb Dasgupta |
Modeling of Leakages in Nano-Scale DG MOSFET to Implement Low Power SRAM: A Device/Circuit Co-Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 183-188, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang |
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 665-672, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Jorge García-Vidal, Maribel March, Llorenç Cerdà, Jesús Corbal, Mateo Valero |
A DRAM/SRAM Memory Scheme for Fast Packet Buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(5), pp. 588-602, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
high-performance memory systems, Router architecture, storage schemes, packet buffers |
27 | Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali |
Testing embedded RAM modules in SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 228, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou |
SRAM Cell Current in Low Leakage Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 65-70, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Derek Ho, Kris Iniewski, Soraya Kasnavi, A. Ivanov, S. Natarajan |
Ultra-low power 90nm 6T SRAM cell for wireless sensor network applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif |
SRAM Local Bit Line Access Failure Analyses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 204-209, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson |
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 557-563, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar |
RG-SRAM: A Low Gate Leakage Memory Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 295-296, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 |
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 176-181, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan |
Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Rabiul Islam, Adam Brand, Dave Lippincott |
Low power SRAM techniques for handheld products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 198-202, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
back-bias, bitcell, memory, leakage |
27 | Olivier Thomas, Amara Amara |
Ultra low voltage design considerations of SOI SRAM memory cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4094-4097, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Matteo Sonza Reorda, Luca Sterpone, Massimo Violante |
Efficient Estimation of SEU Effects in SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 54-59, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan |
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 183-188, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Yen-Jen Chang, Feipei Lai, Chia-Lin Yang |
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(8), pp. 827-836, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, Alessandro Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin |
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 584-589, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Yi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang |
A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 272-276, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Lilian Bossuet, Guy Gogniat, Wayne P. Burleson |
Dynamically Configurable Security for SRAM FPGA Bitstreams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy 0001 |
Statistical design and optimization of SRAM cell for yield enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 10-13, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Benjamin M. Mauck, Vishnumohan Ravichandran, Usman Azeez Mughal |
A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 105-113, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Ghazanfar Asadi, Seyed Ghassem Miremadi, Hamid R. Zarandi, Ali Reza Ejlali |
Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 3-5 March 2004, Papeete, Tahiti, pp. 327-332, 2004, IEEE Computer Society, 0-7695-2076-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin |
Analyzing Soft Errors in Leakage Optimized SRAM Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 227-233, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin |
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(6), pp. 637-647, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
memory BIST, memory diagnostics, memory testing, RAM, semiconductor memory |
27 | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante |
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 607-615, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Robert Gibbins, R. Dean Adams, Thomas J. Eckenrode, Michael Ouellette, Yuejian Wu |
Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 83-, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Mario R. Casu, Philippe Flatresse |
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 163-167, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Hong-Yi Huang, Hsuan-Yi Su |
Low-power 2P2N SRAM with column hidden refresh. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 591-594, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Robert K. Grube, Qi Wang, Sung-Mo Kang |
Design limitations in deep sub-0.1µm CMOS SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, New York, NY, USA, April 18-19, 2002, pp. 94-97, 2002, ACM, 1-58113-462-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
GIDL, on-chip cache, tunneling currents, gate leakage |
27 | Raymond J. Sung, John C. Koob, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn |
Design of an Embedded Fully-Depleted SOI SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 9th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2001), 6-7 August 2001, San Jose, CA, USA, pp. 13-, 2001, IEEE Computer Society, 0-7695-1242-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi |
Testing SRAM-Based Content Addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(10), pp. 1054-1063, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
March C algorithm, fault detection, fault modeling, memory testing, Content addressable memory |
27 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
SRAM-Based FPGAs: Testing the Embedded RAM Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 159-167, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FPGA, test, ATPG, RAM, iterative testing |
27 | Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos |
An analytical, transistor-level energy model for SRAM-based caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 198-201, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
27 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
SRAM-based FPGA's: testing the LUT/RAM modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 1102-1111, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
27 | Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa |
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(4), pp. 377-387, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
26 | Zhe Feng 0002, Naifeng Jing, GengSheng Chen, Yu Hu 0002, Lei He 0001 |
IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 482-485, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
in-place, soft error, don't care, mitigation, SRAM-based FPGA |
26 | Darsen D. Lu, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu |
Compact Modeling of Variation in FinFET SRAM Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 27(2), pp. 44-50, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multigate MOSFETs, variability, design for manufacturing, SRAM, design and test, FinFET, compact modeling |
26 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
Impact of Resistive-Bridging Defects in SRAM Core-Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 265-269, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
core-cell, resistive-bridging defects, SRAM |
26 | Amara Amara, Bastien Giraud, Olivier Thomas |
An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 241-244, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
SRAM cell, Planar Double-Gate (DG), Fully Depleted SOI (FD-SOI), read and write tradeoffs, Ultra Low Voltage (ULV) |
26 | Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan |
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 45-50, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Nanoscale CMOS, SRAM, Power Dissipation, Static Noise Margin |
26 | Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj |
FinFET SRAM Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 440-445, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
variability, SRAM, FinFET, Double gate |
26 | Ghazanfar Asadi, Mehdi Baradaran Tahoori |
Soft error rate estimation and mitigation for SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 149-160, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
soft error rate estimation, error recovery, SRAM-based FPGA |
26 | Martin Margala |
Low-Power SRAM Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA, pp. 115-122, 1999, IEEE Computer Society, 0-7695-0259-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
design, VLSI, low-power, SRAM, low-voltage |
26 | V. Kim, T. Chen |
Assessing SRAM test coverage for sub-micron CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 24-30, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
submicron CMOS technologies, SRAM test coverage assessment, memory fault probability model, memory array, data retention faults, memory fault coverages, memory test algorithms, functional fault class coverages, 0.5 to 1 mum, stuck-at faults, transition faults, stuck-open faults, coupling faults, physical defects, CMOS memory circuits |
24 | Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita |
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 291, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dopant-segregated schottky transistor, nonvolatile configurable memory |
24 | Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili |
An energy efficient cache design using spin torque transfer (STT) RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 389-394, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
(STT)RAM, memory technologies, cache design |
24 | Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen 0001, Hai Li 0001 |
Tolerating process variations in large, set-associative caches: The buddy cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(2), pp. 8:1-8:34, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
caches, Processor architectures, fault recovery, memory structures |
24 | Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Jian Li 0059, Yiran Chen 0001 |
A novel architecture of the 3D stacked MRAM L2 cache for CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 239-249, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Roberto Cornacchia, Sándor Héman, Marcin Zukowski, Arjen P. de Vries, Peter A. Boncz |
Flexible and efficient IR using array databases. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLDB J. ![In: VLDB J. 17(1), pp. 151-168, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Array databases, Information retrieval, Query optimization, Database compression |
24 | Hisashige Ando, Ryuji Kan, Yoshiharu Tosaka, Keiji Takahisa, Kichiji Hatanaka |
Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 62-69, 2008, IEEE Computer Society, 978-1-4244-2397-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Sherif A. Tawfik, Volkan Kursun |
Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 788-791, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Sherif A. Tawfik, Volkan Kursun |
Dynamic wordline voltage swing for low leakage and stable static memory banks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1894-1897, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Tony Tae-Hyoung Kim, Jason Liu 0004, John Keane 0001, Chris H. Kim |
Circuit techniques for ultra-low power subthreshold SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2574-2577, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Sandeep S. Kumar, Jorge Guajardo, Roel Maes, Geert Jan Schrijen, Pim Tuyls |
The Butterfly PUF: Protecting IP on every FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HOST ![In: IEEE International Workshop on Hardware-Oriented Security and Trust, HOST 2008, Anaheim, CA, USA, June 9, 2008. Proceedings, pp. 67-70, 2008, IEEE Computer Society, 978-1-4244-2401-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Rajani Kuchipudi, Hamid Mahmoodi |
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 27-32, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
24 | Nian-Feng Tzeng |
Routing Table Partitioning for Speedy Packet Lookups in Scalable Routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 17(5), pp. 481-494, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
line cards, prefix matching search, routing table lookups, Caches, interconnects, routers, tries, forwarding engines |
24 | Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann |
Memory performance prediction for high-performance microprocessors at deep submicrometer technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), pp. 1705-1718, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Hae-woo Park, Kyoungjoo Oh, Soyoung Park, Myoung-min Sim, Soonhoi Ha |
Dynamic code overlay of SDF-modeled programs on low-end embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 945-946, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Qing K. Zhu |
Memory Generation and Power Distribution In SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 491-495, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Tianzhou Chen, Wei Hu 0001, Yi Lian |
Power-Efficient Microkernel of Embedded Operating System on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 473-479, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
power-efficient, microkernel, embedded operating system |
24 | Jason E. Miller, Anant Agarwal |
Software-based instruction caching for embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 293-302, 2006, ACM, 1-59593-451-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
instruction cache, chaining, software caching |
24 | Sailesh Kumar, Jonathan S. Turner, Patrick Crowley |
Addressing Queuing Bottlenecks at High Speeds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: 13th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2005), 17-19 August 2005, Stanford, CA, USA, pp. 107-113, 2005, IEEE Computer Society, 0-7695-2449-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Sumesh Udayakumaran, Rajeev Barua |
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 276-286, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
embedded systems, compiler, memory allocation, scratch-pad |
24 | Nian-Feng Tzeng |
Hardware-Assisted Design for Fast Packet Forwarding in Parallel Routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 32nd International Conference on Parallel Processing (ICPP 2003), 6-9 October 2003, Kaohsiung, Taiwan, pp. 11-, 2003, IEEE Computer Society, 0-7695-2017-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
24 | Oren Avissar, Rajeev Barua, Dave Stewart |
An optimal memory allocation scheme for scratch-pad-based embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 1(1), pp. 6-26, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
embedded, Memory, heterogeneous, storage, allocation |
24 | Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou |
Energy recovering static memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 92-97, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
adiabatic circuitry, charge recovery, cache memories, on-chip memories, low-power computing, low-energy design |
24 | Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Akihito Tohata, Nobuaki Otsuka |
DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 164-169, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Oren Avissar, Rajeev Barua, Dave Stewart |
Heterogeneous memory management for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 34-43, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
embedded, memory, heterogeneous, storage |
24 | Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie |
An efficient BIST method for testing of embedded SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 73-76, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Khoan Truong |
A Simple Built-In Self Test For Dual Ported SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA, pp. 79-84, 2000, IEEE Computer Society, 0-7695-0689-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Luca Benini, Alberto Macii, Massimo Poncino |
A recursive algorithm for low-power memory partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 78-83, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
24 | Vicente Baena Lecuyer, M. A. Aguirre, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo, Julio Faura |
Decoder-driven switching matrices in multicontext FPGAs: area reduction and their effect on routability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 463-466, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Leonidas I. Kontothanassis, Rabin A. Sugumar, Greg Faanes, James E. Smith 0001, Michael L. Scott |
Cache performance in vector supercomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings Supercomputing '94, Washington, DC, USA, November 14-18, 1994, pp. 255-264, 1994, IEEE Computer Society, 0-8186-6605-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
24 | Ron Bourassa, Tim Coffman, Joe Brewer |
Ultra large scale static rams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 2(4), pp. 301-311, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
23 | Björn Osterloh, Harald Michalik, Björn Fiethe |
SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings, pp. 50-59, 2009, Springer, 978-3-642-00453-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SoCWire, dynamic reconfigurable system, Sytem-on-Chip, Network-on-Chip, SRAM-based FPGA, VMC |
23 | Weirong Jiang, Viktor K. Prasanna |
Field-split parallel architecture for high performance multi-match packet classification using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2009: Proceedings of the 21st Annual ACM Symposium on Parallelism in Algorithms and Architectures, Calgary, Alberta, Canada, August 11-13, 2009, pp. 188-196, 2009, ACM, 978-1-60558-606-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multi-match packet classification, fpga, sram, nids |
23 | Weirong Jiang, Viktor K. Prasanna |
Multi-terabit ip lookup using parallel bidirectional pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 5th Conference on Computing Frontiers, 2008, Ischia, Italy, May 5-7, 2008, pp. 241-250, 2008, ACM, 978-1-60558-077-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ip lookup, terabit, pipeline, sram, bidirectional |
23 | Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev |
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 207-212, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
critical charge, process variation, Soft error, SRAM |
23 | Franz X. Ruckerbauer, Georg Georgakos |
Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 203-204, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
NSER, ASER, multi-bit upset, soft errors and radiation, CMOS, SRAM, SEU |
23 | Kiyoo Itoh 0001, Masanao Yamaoka, Takayuki Kawahara |
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 529-533, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate |
23 | Meng-Fan Chang, Kuei-Ann Wen |
Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 41(1), pp. 81-91, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
supply noise, SRAM, substrate noise, ROM |
23 | Prassanna Sithambaram, Alberto Macii, Enrico Macii |
Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 377-380, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
DBL, DWL, partitioning, embedded, memories, SRAM, application-specific |
23 | Stefanos Kaxiras, Polychronis Xekalakis |
4T-decay sensors: a new class of small, fast, robust, and low-power, temperature/leakage sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 108-113, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
4T SRAM, architecture, sensor, leakage, temperature |
23 | Baosheng Wang, Josh Yang, André Ivanov |
Reducing Test Time of Embedded SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 47-52, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Embedded SRAM test, Inductive Fault Analysis, Memory Redundancy, March Test, Test Time |
23 | Kiyoo Itoh 0001 |
Low-voltage memories for power-aware systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 1-6, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
DRAM and SRAM cells, gain cells, gate-source/substrate-source back-biasing, memory-rich architectures, multi-Vr, non-volatile RAMs, on-chip voltage converters, peripheral circuits, subthreshold current, testing |
23 | Amit Agarwal 0001, Hai Li, Kaushik Roy 0001 |
DRG-cache: a data retention gated-ground cache for low power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 473-478, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
gated-ground, low leakage cache, SRAM |
23 | Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara |
Testing for the programming circuit of LUT-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 242-247, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
programming circuit, control circuit, configuration memory cell array, FPGA, fault model, SRAM, shift registers, shift registers, look-up table |
23 | Wei Liang Huang, Fred J. Meyer, Fabrizio Lombardi |
Multiple fault detection in logic resources of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 186-194, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
logic resources, AND tree, OR tree, CLB test generation, field programmable gate arrays, fault model, configurability, testability, programmability, multiple fault detection, SRAM-based FPGA |
23 | Ad J. van de Goor, Yervant Zorian |
Effective march algorithms for testing single-order addressed memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(4), pp. 337-345, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
Read/Write memories, single-address order, single-order addressed memory, SRAM, memory testing, March test |
22 | Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(7), pp. 2075-2086, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Seyed Hassan Hadi Nemati, Nima Eslami, Mohammad Hossein Moaiyeri |
A Hybrid SRAM/RRAM In-Memory Computing Architecture Based on a Reconfigurable SRAM Sense Amplifier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 72159-72171, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
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