Search results for "Virtex"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Nicolas Farrugia, Franck Mamalet, Sébastien Roux, Fan Yang 0019, Michel Paindavoine	A Parallel Face Detection System Implemented on FPGA.	ISCAS	2007	DBLP DOI BibTeX RDF
16	Dong-U Lee, John D. Villasenor, Wayne Luk, Philip Heng Wai Leong	A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	elementary function approximation, minimax approximation and algorithms, simulation, optimization, field programmable gate arrays, computer arithmetic, error analysis, random number generation, Algorithms implemented in hardware
16	Bo Yang 0010, Ramesh Karri, David A. McGrew	A High-Speed Hardware Architecture for Universal Message Authentication Code.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
16	Usama Malik, Oliver Diessel	The Entropy of FPGA Reconfiguration.	FPL	2006	DBLP DOI BibTeX RDF
16	Daniel Ziener, Stefan Assmus, Jürgen Teich	Identifying FPGA IP-Cores Based on Lookup Table Content Analysis.	FPL	2006	DBLP DOI BibTeX RDF
16	Hanho Lee, Chang-Seok Choi	Implementation of a FIR Filter on a Partial Reconfigurable Platform.	KES (3)	2006	DBLP DOI BibTeX RDF
16	Michael Hübner 0001, Katarina Paulsson, Jürgen Becker 0001	Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores.	IPDPS	2005	DBLP DOI BibTeX RDF
16	Todd S. Sproull, Gordon J. Brebner, Christopher E. Neely	Mutable Codesign for Embedded Protocol Processing.	FCCM	2005	DBLP DOI BibTeX RDF
16	T. S. B. Sudarshan, Rahil Mir, S. Vijayalakshmi	DRIL- A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration, Replication, Inner-Loop Pipelining, Loop Folding Techniques.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF	Blowfish, inner loop pipeline, loop folding, four - tier architecture, Platform independent architecture, DRIL Architecture, replication, Dynamic reconfiguration
16	Balasubramanian Sethuraman, Prasun Bhattacharya, Jawad Khan, Ranga Vemuri	LiPaR: A light-weight parallel router for FPGA-based networks-on-chip.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	SoCRouter, FPGA, networks-on-chip
16	Nicholas Weaver, John R. Hauser, John Wawrzynek	The SFRA: a corner-turn FPGA architecture.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA CAD, FPGA design study, FPGA optimization, FPGA architecture
16	Ian Kuon, Aaron Egier, Jonathan Rose	Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
16	Erik Chmelar	Subframe multiplexing for FPGA manufacturing test configuration.	FPGA	2004	DBLP DOI BibTeX RDF
16	Elias Todorovich, Eduardo I. Boemo, Francisco Cardells-Tormo, Javier Valls	Power analysis and estimation tool integrated with XPOWER.	FPGA	2004	DBLP DOI BibTeX RDF
16	Nalin Sidahao	Optimized Field Programmable Gate Array Based Function Evaluation.	FPL	2004	DBLP DOI BibTeX RDF
16	Quoc Thai Ho, Daniel Massicotte	FPGA Implementation of Adaptive Multiuser Detector for DS-CDMA Systems.	FPL	2004	DBLP DOI BibTeX RDF
16	Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung	Multiple Restricted Multiplication.	FPL	2004	DBLP DOI BibTeX RDF
16	Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps	Comparative Study of SRT-Dividers in FPGA.	FPL	2004	DBLP DOI BibTeX RDF
16	Maya B. Gokhale, Janette Frigo, Christine Ahrens, Justin L. Tripp, Ronald G. Minnich	Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer.	FPL	2004	DBLP DOI BibTeX RDF
16	Michael J. Thul, Norbert Wehn	FPGA implementation of parallel turbo-decoders.	SBCCI	2004	DBLP DOI BibTeX RDF	wireless, parallel architecture, FPGA implementation, turbo-decoder
16	Maya B. Gokhale, Paul S. Graham, Darrel Eric Johnson, Nathan Rollins, Michael J. Wirthlin	Dynamic Reconfiguration for Management of Radiation-Induced Faults in FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF
16	Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West	ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers.	FCCM	2004	DBLP DOI BibTeX RDF
16	Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis	A reusable IP FFT core for DSP applications.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
16	Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang	Energy-efficient signal processing using FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	energy efficient design techniques, matrix multiplicaiton, FPGA, FFT, performance estimation
16	Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä	A fully pipelined memoryless 17.8 Gbps AES-128 encryptor.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, pipelining, advanced encryption standard (AES)
16	Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson	Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
16	Seokjin Lee, Hua Xiang 0001, D. F. Wong 0001, Richard Y. Sun	Wire type assignment for FPGA routing.	FPGA	2003	DBLP DOI BibTeX RDF	min-cost flow algorithm, wire type assignment, FPGA routing
16	Brandon Blodget, Philip James-Roxby, Eric Keller, Scott McMillan, Prasanna Sundararajan	A Self-reconfiguring Platform.	FPL	2003	DBLP DOI BibTeX RDF
16	Irwin Kennedy	Exploiting Redundancy to Speedup Reconfiguration of an FPGA.	FPL	2003	DBLP DOI BibTeX RDF
16	Jean-Luc Beuchat	FPGA Implementations of the RC6 Block Cipher.	FPL	2003	DBLP DOI BibTeX RDF
16	Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Francisco José Mora Mas	Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA.	FPL	2003	DBLP DOI BibTeX RDF
16	Jean-Luc Beuchat	Modular Multiplication for FPGA Implementation of the IDEA Block Cipher.	ASAP	2003	DBLP DOI BibTeX RDF
16	Klaus Buchenrieder, Andreas Pyttel, Alexander Sedlmeier	A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering.	DATE	2002	DBLP DOI BibTeX RDF
16	Anna Labbé, Annie Pérez	AES Implementation on FPGA: Time - Flexibility Tradeoff.	FPL	2002	DBLP DOI BibTeX RDF
16	Jérémie Detrey, Florent de Dinechin	Multipartite Tables in JBits for the Evaluation of Functions on FPGAs.	IPDPS	2002	DBLP DOI BibTeX RDF
16	Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri	Framework for Synthesis of Virtual Pipelines.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Virtual Pipeline, SLAAC-1V board, JHDL, FPGAs, Pipelining, Dynamic Reconfiguration, Partial Reconfiguration
16	Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West	Architecture and Hardware for Scheduling Gigabit Packet Streams.	Hot Interconnects	2002	DBLP DOI BibTeX RDF
16	Máire McLoone, John V. McCanny	Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm.	FPL	2001	DBLP DOI BibTeX RDF	Encryption, AES, Rijndael, FPGA Implementation
16	Pawel Chodowiec, Kris Gaj, Peter Bellows, Brian Schott	Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board.	ISC	2001	DBLP DOI BibTeX RDF
16	Andrew M. Tyrrell, Gordon Hollingworth, Stephen L. Smith 0002	Evolutionary Strategies And Intrinsic Fault Tolerance.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
16	Máire McLoone, John V. McCanny	High Performance Single-Chip FPGA Rijndael Algorithm Implementations.	CHES	2001	DBLP DOI BibTeX RDF	Encryption, AES, Rijndael, FPGA Implementation
16	Scott McMillan, Steve Guccione	Partial Run-Time Reconfiguration Using JRTR.	FPL	2000	DBLP DOI BibTeX RDF
16	Arran Derbyshire, Wayne Luk	Combining Serialization and Reconfiguration for Convolver Designs.	FCCM	2000	DBLP DOI BibTeX RDF
16	Ka Hei Leung, K. W. Ma, Wai Keung Wong, Philip Heng Wai Leong	FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor.	FCCM	2000	DBLP DOI BibTeX RDF
8	Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu 0001, Xu Cheng 0001, Jason Cong	Bit-level optimization for high-level synthesis and FPGA-based acceleration.	FPGA	2010	DBLP DOI BibTeX RDF	bit-level optimization, fpga, high-level synthesis
8	Deepak Unnikrishnan, Ramakrishna Vadlamani, Yong Liao, Abhishek Dwaraki, Jérémie Crenne, Lixin Gao 0001, Russell Tessier	Scalable network virtualization using FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, virtual networks
8	Zefu Dai, Nick Ni, Jianwen Zhu	A 1 cycle-per-byte XML parsing accelerator.	FPGA	2010	DBLP DOI BibTeX RDF	bart, schema validation, string comparison, xml parsing, ethernet, bloom filter, dom, tree construction
8	Sunwoo Kim, Won Woo Ro	FPGA implementation of highly parallelized decoder logic for network coding (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, network coding, fpga implementation, galois field arithmetic
8	Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell	A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpgas, bioinformatics, sequence alignment, data dependency analysis, smith-waterman algorithm
8	Kenneth M. Zick, John P. Hayes	On-line sensing for healthier FPGA systems.	FPGA	2010	DBLP DOI BibTeX RDF	on-line sensing, physically-adaptive computing., fpgas, reliability, process variation, leakage, temperature, dynamic power, ring oscillator, static power, health management
8	Mingjie Lin, Ilia A. Lebedev, John Wawrzynek	High-throughput bayesian computing machine with reconfigurable hardware.	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable hardware, bayesian computing
8	Marc-André Daigneault, Jean-Pierre David	Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	time-to-digital converter, vernier method, field programmable gate array, dynamic reconfiguration
8	Yi-Hua E. Yang, Viktor K. Prasanna	High throughput and large capacity pipelined dynamic search tree on FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	2-3 tree, in-place update, ip forwarding, pipelined tree, b-tree, dynamic update, incremental update, openflow
8	Rahul Bhattacharya, Santosh Biswas, Siddhartha Mukhopadhyay	FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	ams testing, concurrent test development, behavioral modeling
8	Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo 0003, Jie Zhou 0007, Li Shen	FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing.	ICS	2010	DBLP DOI BibTeX RDF	double-double precision, high precision floating-point multiplication and accumulation (HP-MAC), quad-double precision, FPGA
8	Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson 0001, Krste Asanovic	RAMP gold: an FPGA-based architecture simulator for multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	simulation, FPGA, multiprocessors
8	Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi	ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	simulator, FPGA, prototype, multiprocessor, multicore, emulator
8	Masayuki Hiromoto, Hiroki Sugano, Ryusuke Miyamoto	Partially Parallel Architecture for AdaBoost-Based Detection With Haar-Like Features.	IEEE Trans. Circuits Syst. Video Technol.	2009	DBLP DOI BibTeX RDF
8	Tian Song, Dongsheng Wang 0002, Zhizhong Tang	A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	network intrusion prevention, network security, pattern matching, network intrusion detection
8	Roman L. Lysecky, Frank Vahid	Design and implementation of a MicroBlaze-based warp processor.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation
8	Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas	FPGA-based hardware acceleration for Boolean satisfiability.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Boolean satisfiabilty (SAT), boolean constant propagation (BCP), conflict induced clauses, non-chronological backtrack, FPGA
8	Carlo Galuzzi, Chunyang Gou, Humberto Calderon, Georgi Gaydadjiev, Stamatis Vassiliadis	High-bandwidth Address Generation Unit.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Address generation unit, Stride, Parallel memory
8	Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel	High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Block turbo decoding, Full-parallel architecture, Complexity analysis, FPGA implementation
8	Petr Kobierský, Jan Korenek, Libor Polcak	Packet header analysis and field extraction for multigigabit networks.	DDECS	2009	DBLP DOI BibTeX RDF
8	Christophe Desmouliers, Erdal Oruklu, Jafar Saniie	FPGA-based design of a high-performance and modular video processing platform.	EIT	2009	DBLP DOI BibTeX RDF
8	V. Kumar Murty, Nikolajs Volkovs	ERINDALE: A Polynomial Based Hashing Algorithm.	IWCC	2009	DBLP DOI BibTeX RDF
8	Siddharth Gupta 0001, Christopher Hunter, Patrick Murphy, Ashutosh Sabharwal	WARPnet: clean slate research on deployed wireless networks.	MobiHoc	2009	DBLP DOI BibTeX RDF	warpnet, measurement, wireless, control, warp
8	Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton	SmartOpt: an industrial strength framework for logic synthesis.	FPGA	2009	DBLP DOI BibTeX RDF	abc, blif, edge flow, smartopt, fpga, interface, technology mapping
8	Yanteng Sun, Peng Li 0031, Guochang Gu, Yuan Wen, Yuan Liu, Dong Liu	HMMer acceleration using systolic array based reconfigurable architecture.	FPGA	2009	DBLP DOI BibTeX RDF	reconfigurable., systolic array, acceleration, hmmer
8	Weirong Jiang, Viktor K. Prasanna	Large-scale wire-speed packet classification on FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, decision tree, pipeline, sram, packet classification
8	Zuo Wang, Feng Shi 0009, Qi Zuo, Weixing Ji, Mengxiao Liu	N-port memory mapping for LUT-based FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	logical-to-physical mapping, n-port memory, fpga, hierarchy
8	David B. Thomas, Lee W. Howes, Wayne Luk	A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation.	FPGA	2009	DBLP DOI BibTeX RDF	mppa, fpga, monte-carlo, random numbers, gpu
8	Florian Dittmann 0001, Elmar Weber, Norma Montealegre	Implementation of the reconfiguration port scheduling on the erlangen slot machine.	FPGA	2009	DBLP DOI BibTeX RDF	erlangen slot machine, scheduling, fpgas, reconfiguration
8	Melina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang	Computation reuse in domain-specific optimization of signal recognition.	FPGA	2009	DBLP DOI BibTeX RDF	computation reuse, signal recognition, fpga
8	Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig	Performance and power of cache-based reconfigurable computing.	FPGA	2009	DBLP DOI BibTeX RDF	c-to-gates, c-to-hardware, co-processor accelerators, fpga, caches
8	Bowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu	32-bit floating-point FPGA gaussian elimination.	FPGA	2009	DBLP DOI BibTeX RDF	fpga., floating-point, gaussian elimination
8	Daniel Le Ly, Paul Chow	A high-performance FPGA architecture for restricted boltzmann machines.	FPGA	2009	DBLP DOI BibTeX RDF	neural network hardware, restricted boltzmann machines, scalable hardware designs, fpga, high-performance computing, complexity reduction
8	Xinyu Li, Omar Hammami	Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, multiprocessor, network on chip
8	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
8	Robin Pottathuparambil, Ron Sass	A parallel/vectorized double-precision exponential core to accelerate computational science applications.	FPGA	2009	DBLP DOI BibTeX RDF	exponential core, fpga, cordic
8	Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner	Fpga-based face detection system using Haar classifiers.	FPGA	2009	DBLP DOI BibTeX RDF	haar classifier, fpga, image processing, real-time, architecture, face detection, adaboost
8	Abdul-Rahman Elshafei, Azzedine Zerguine, Abdelhafid Bouhraoua	Scalable FPGA implementation for mixed-norm LMS-LMF adaptive filters.	IWCMC	2009	DBLP DOI BibTeX RDF	LMS-LMF, FPGA, adaptive filters, scalable architecture
8	Pierre Bomel, Jérémie Crenne, Linfeng Ye, Jean-Philippe Diguet, Guy Gogniat	Ultra-Fast Downloading of Partial Bitstreams through Ethernet.	ARCS	2009	DBLP DOI BibTeX RDF	bitstream server, ultra-fast downloading, FPGA, Ethernet, partial reconfiguration, link layer
8	Yanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan Liu, Dong Liu	Accelerating HMMer on FPGAs using systolic array based architecture.	IPDPS	2009	DBLP DOI BibTeX RDF
8	Jochen Strunk, Toni Volkmer, Klaus Stephan, Wolfgang Rehm, Heiko Schick	Impact of run-time reconfiguration on design and speed - A case study based on a grid of run-time reconfigurable modules inside a FPGA.	IPDPS	2009	DBLP DOI BibTeX RDF
8	Jie Li 0004, Haibo He, Hong Man, Sachi Desai	A General-Purpose FPGA-Based Reconfigurable Platform for Video and Image Processing.	ISNN (3)	2009	DBLP DOI BibTeX RDF	video and image processing, edge detection, Reconfigurable system, FPGA design, image scaling
8	Sjoerd Meijer, Hristo Nikolov, Todor P. Stefanov	On compile-time evaluation of process partitioning transformations for Kahn process networks.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	programming of MPSoC, transformations, Kahn process networks
8	Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner 0001, Jürgen Becker 0001	FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.	ARC	2009	DBLP DOI BibTeX RDF	design assurance, bitstream debugging, security, FPGA, Reconfigurable Computing, design verification, EDA tools
8	Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro	Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm.	ARC	2009	DBLP DOI BibTeX RDF	Block Cipher Algorithm, Field Programmable Gate Arrays (FPGA), Cryptography, SEED
8	Gang Zhou, Harald Michalik, László Hinsenkamp	Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	AES-GCM, pipelined Karatsuba multiplier, FPGAs, finite field arithmetic
8	Sameh M. Shohdy, Ashraf El-Sisi, Nabil A. Ismail	FPGA Implementation of Elliptic Curve Point Multiplication over GF(2191).	ISA	2009	DBLP DOI BibTeX RDF	Karatsuba-Ofman multiplier, polynomial inversion, field programmable gate arrays, Elliptic curve cryptography, Galois field, polynomial multiplication
8	Alejandro Castillo Atoche, Deni Torres Román, Yuriy Shkvarko	Near Real Time Enhancement of Remote Sensing Imagery Based on a Network of Systolic Arrays.	CIARP	2009	DBLP DOI BibTeX RDF	Network of Systolic Arrays, Remote Sensing, Hardware/Software Co-Design
8	Abdulhadi Shoufan, Thorsten Wink, H. Gregor Molter, Sorin A. Huss, Falko Strenzke	A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms.	ASAP	2009	DBLP DOI BibTeX RDF
8	Seunghun Jin, Dongkyun Kim, Thuy Tuong Nguyen, Bongjin Jun, Daijin Kim 0001, Jae Wook Jeon	An FPGA-based Parallel Hardware Architecture for Real-Time Face Detection Using a Face Certainty Map.	ASAP	2009	DBLP DOI BibTeX RDF
8	Ray C. C. Cheung, Çetin Kaya Koç, John D. Villasenor	A High-Performance Hardware Architecture for Spectral Hash Algorithm.	ASAP	2009	DBLP DOI BibTeX RDF
8	Julien Lamoureux, Tony Field, Wayne Luk	Accelerating a Virtual Ecology Model with FPGAs.	ASAP	2009	DBLP DOI BibTeX RDF
8	Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan	FPGA Based High Performance Double-Precision Matrix Multiplication.	VLSI Design	2009	DBLP DOI BibTeX RDF
8	Weirong Jiang, Viktor K. Prasanna	Field-split parallel architecture for high performance multi-match packet classification using FPGAs.	SPAA	2009	DBLP DOI BibTeX RDF	multi-match packet classification, fpga, sram, nids
8	David B. Thomas, Wayne Luk	Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	FPGA, Random numbers, multivariate Gaussian distribution
8	David Slogsnat, Alexander Giese, Mondrian Nüssle, Ulrich Brüning 0001	An open-source HyperTransport core.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	HTX, HyperTransport, FPGA, prototyping, RTL