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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2239 occurrences of 940 keywords
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Results
Found 7472 publication records. Showing 7472 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
43 | Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak |
Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Animesh Kumar, Jan M. Rabaey, Kannan Ramchandran |
SRAM supply voltage scaling: A reliability perspective. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
43 | Andrew B. Kahng, Swamy Muddu, Puneet Sharma |
Impact of Gate-Length Biasing on Threshold-Voltage Selection. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Vijay Degalahal, Lin Li 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
Soft errors issues in low-power caches. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Le Yan, Jiong Luo, Niraj K. Jha |
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Chintan Patel, Abhishek Singh 0001, Jim Plusquellic |
Defect Detection Using Quiescent Signal Analysis. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
multiple current measurements, Quiescent Signal Analysis, IDDQ, current testing, defect-based testing, parametric testing |
43 | Liqiong Wei, Zhanping Chen, Kaushik Roy 0001, Mark C. Johnson, Yibin Ye, Vivek De |
Design and optimization of dual-threshold circuits for low-voltage low-power applications. |
IEEE Trans. Very Large Scale Integr. Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
42 | Min Ni, Seda Ogrenci Memik |
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
dual-Vth, leakage power optimization, gate sizing, clock skew scheduling |
42 | Siva G. Narendra |
Challenges and design choices in nanoscale CMOS. |
ACM J. Emerg. Technol. Comput. Syst. |
2005 |
DBLP DOI BibTeX RDF |
nanoscale, process variation, CMOS, leakage power |
42 | Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001 |
Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
process variation, yield, leakage, dual-Vt, metal gate |
40 | Jonathan Katz, Vinod Vaikuntanathan |
Signature Schemes with Bounded Leakage Resilience. |
ASIACRYPT |
2009 |
DBLP DOI BibTeX RDF |
|
40 | Kwangok Jeong, Andrew B. Kahng, Hailong Yao |
Revisiting the linear programming framework for leakage power vs. performance optimization. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
40 | Yu Wang 0002, Ku He, Rong Luo, Hui Wang 0004, Huazhong Yang |
Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Behnam Amelifard, Farzan Fallah, Massoud Pedram |
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Roberto Giorgi, Paolo Bennati |
Reducing Leakage through Filter Cache. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Andrea Alimonda, Andrea Acquaviva, Salvatore Carta |
Temperature and Leakage Aware Power Control for Embedded Streaming Applications. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Jinseob Jeong, Seungwhun Paik, Youngsoo Shin |
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum |
ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc Gaudiot |
Adaptive techniques for leakage power management in L2 cache peripheral circuits. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Meng Wang 0005, Zili Shao, Hui Liu 0006, Chun Jason Xue |
Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors. |
DIPES |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Yousra Alkabani, Tammara Massey, Farinaz Koushanfar, Miodrag Potkonjak |
Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
input vector control, low power, manufacturing variability |
40 | Youngsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi |
Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Nikhil Jayakumar, Sunil P. Khatri |
An algorithm to minimize leakage through simultaneous input vector control and circuit modification. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Jaehyun Kim, Youngsoo Shin |
Minimizing leakage power in sequential circuits by using mixed Vt flip-flops. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Houman Homayoun, Alexander V. Veidenbaum |
Reducing leakage power in peripheral circuits of L2 caches. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan |
Voltage drop reduction for on-chip power delivery considering leakage current variations. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Rodrigo Jaramillo-Ramirez, Mohab Anis |
A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Khaled R. Heloue, Navid Azizi, Farid N. Najm |
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Ashesh Rastogi, Wei Chen, Sandip Kundu |
On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Jun Seomun, Jaehyun Kim, Youngsoo Shin |
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Jae-Joon Kim, Kaushik Roy 0001 |
A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Chris H. Kim, Kaushik Roy 0001, Steven Hsu, Ram Krishnamurthy 0001, Shekhar Borkar |
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
40 | José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura 0001 |
Leakage Power Characterization Considering Process Variations. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Se Hun Kim, Vincent John Mooney |
Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Sarvesh Bhardwaj, Yu Cao 0001, Sarma B. K. Vrudhula |
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Hyung-Ock Kim, Youngsoo Shin |
Analysis and optimization of gate leakage current of power gating circuits. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Kris Tiri, Patrick Schaumont, Ingrid Verbauwhede |
Side-Channel Leakage Tolerant Architectures. |
ITNG |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Emrah Acar, Kanak Agarwal, Sani R. Nassif |
Characterization of total chip leakage using inverse (reciprocal) gamma distribution. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Volkan Kursun, Zhiyu Liu |
Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri |
A probabilistic method to determine the minimum leakage vector for combinational designs. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino |
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Deniz Dal, Adrian Nunez, Nazanin Mansouri |
Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos |
Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Ranganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori |
Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
40 | Wei Zhang 0002 |
Compiler-Directed Data Cache Leakage Reduction. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Enrico Macii |
Leakage power optimization in standard-cell designs. |
SBCCI |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Feng Gao 0017, John P. Hayes |
Exact and heuristic approaches to input vector control for leakage power reduction. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Volkan Kursun, Eby G. Friedman |
Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Y. Z. Xu, O. Pohland, C. Cai, Helmut Puchner |
Leakage Increase of Narrow and Short BCPMOS. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Ali Muhtaroglu, Benoit Provost, Tawfik Rahal-Arabi, Greg Taylor |
I/O Self-Leakage Test. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung |
Leakage Reduction techniques in a 0.13um SRAM Cell. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj |
Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
40 | Navid Azizi, Farid N. Najm, Andreas Moshovos |
Low-leakage asymmetric-cell SRAM. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Yann-Hang Lee, Krishna P. Reddy, C. Mani Krishna 0001 |
Scheduling Techniques for Reducing Leakage Power in Hard Real-Time Systems. |
ECRTS |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Chandramouli Gopalakrishnan, Srinivas Katkoori |
An Architectural Leakage Power Simulator for VHDL Structural Datapaths. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
40 | SeongHan Shin, Kazukuni Kobara, Hideki Imai |
Leakage-Resilient Authenticated Key Establishment Protocols. |
ASIACRYPT |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Rafik S. Guindi, Farid N. Najm |
Design Techniques for Gate-Leakage Reduction in CMOS Circuits. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
40 | Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David T. Blaauw |
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy 0001 |
Leakage control with efficient use of transistor stacks in single threshold CMOS. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David T. Blaauw |
Robust SAT-Based Search Algorithm for Leakage Power Reduction. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Yi-Ping You, Chingren Lee, Jenq Kuen Lee |
Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors. |
LCPC |
2002 |
DBLP DOI BibTeX RDF |
|
39 | Jinhui Wang, Lei Zuo, Na Gong, Daming Gao, Shuqin Geng, Wang Zhang, Ligang Hou, Xiaohong Peng, Wuchen Wu |
Estimation for Speed and Leakage Power of Dual Threshold Domino OR Based on Wavelet Neural Networks. |
ISNN (1) |
2009 |
DBLP DOI BibTeX RDF |
Dual threshold domino OR, Leakage power, Speed, Wavelet Neural Networks |
39 | Jian-Jia Chen, Tei-Wei Kuo |
Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
job procrastination, leakage-aware scheduling, scheduling, dynamic voltage scaling, energy-aware systems |
39 | Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas |
Modeling and estimating leakage current in series-parallel CMOS networks. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
leakage current modeling, static power dissipation, CMOS gates |
39 | Jian-Jia Chen, Tei-Wei Kuo |
Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor. |
LCTES |
2006 |
DBLP DOI BibTeX RDF |
leakage-aware scheduling, scheduling, dynamic voltage scaling, fixed-priority scheduling, energy-aware systems, rate-monotonic scheduling |
39 | Rahul Nagpal, Y. N. Srikant |
Compiler-assisted leakage energy optimization for clustered VLIW architectures. |
EMSOFT |
2006 |
DBLP DOI BibTeX RDF |
scheduling, leakage energy, energy-aware scheduling, clustered VLIW processors |
39 | Ke Meng, Russ Joseph |
Process variation aware cache leakage management. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
gated-VDD, selective cache ways, low power, process variation, leakage, cache management |
39 | Wann-Yun Shieh, Hsin-Dar Chen |
Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB. |
EUC Workshops |
2006 |
DBLP DOI BibTeX RDF |
register leakage power, high-end embedded processor, dynamic voltage scaling (DVS), reorder buffer |
39 | Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino |
STV-Cache: a leakage energy-efficient architecture for data caches. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
architecture, caches, leakage power |
39 | Andrea Lodi 0002, Luca Ciccarelli, Roberto Giansante |
Combining low-leakage techniques for FPGA routing design. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
low leakage, FPGA, power |
39 | Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee |
A sink-n-hoist framework for leakage power reduction. |
EMSOFT |
2005 |
DBLP DOI BibTeX RDF |
balanced scheduling, compilers for low power, power-gating mechanisms, data-flow analysis, leakage power reduction |
39 | Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry |
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), sleep transistor (ST), sub-threshold leakage power, FPGA, packing |
39 | Azadeh Davoodi, Ankur Srivastava 0001 |
Probabilistic dual-Vth leakage optimization under variability. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
optimization, process variations, leakage, automatic synthesis |
39 | Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik |
Peak temperature control and leakage reduction during binding in high level synthesis. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
switching, leakage, temperature, binding |
39 | Somsubhra Mondal, Seda Ogrenci Memik |
Fine-grain leakage optimization in SRAM based FPGAs. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
hierarchical LUT, FPGA, low power, leakage power |
39 | Xiaoyong Tang, Hai Zhou 0001, Prithviraj Banerjee |
Leakage power optimization with dual-Vth library in high-level synthesis. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
dual-Vth, optimization, high-level synthesis, leakage power |
39 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Leakage minimization of nano-scale circuits in the presence of systematic and random variations. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
optimization, statistical, leakage, geometric programming |
39 | Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang |
Nanoscale CMOS circuit leakage power reduction by double-gate device. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
double-gate device, short-channel effect, leakage power |
39 | Ali Bastani, Charles A. Zukowski |
Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
gate leakage reduction, superbuffers, low power design |
39 | Masaharu Goto, Toshinori Sato |
Leakage Energy Reduction in Register Renaming. |
ICDCS Workshops |
2004 |
DBLP DOI BibTeX RDF |
super-scalar processors, embedded processors, register renaming, deep submicron, Leakage energy |
39 | Xiaotong Zhuang, Tao Zhang 0037, Santosh Pande |
HIDE: an infrastructure for efficiently protecting information leakage on the address bus. |
ASPLOS |
2004 |
DBLP DOI BibTeX RDF |
address bus leakage protection, secure processor |
39 | Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
Statistical optimization of leakage power considering process variations using dual-Vth and sizing. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
optimization, variability, leakage |
39 | Ravindra Jejurikar, Cristiano Pereira, Rajesh K. Gupta 0001 |
Leakage aware dynamic voltage scaling for real-time embedded systems. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
critical speed, procrastication, real-time systems, leakage power, EDF scheduling, low power scheduling |
39 | Oleg Semenov, Arman Vassighi, Manoj Sachdev |
Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing. |
J. Electron. Test. |
2003 |
DBLP DOI BibTeX RDF |
MOSFET leakage, reliability, quality, CMOS integrated circuits, I DDQ testing |
39 | Xuning Chen, Li-Shiuan Peh |
Leakage power modeling and optimization in interconnection networks. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
interconnection networks, leakage power, power optimization |
39 | Weiping Liao, Fei Li 0003, Lei He 0001 |
Microarchitecture level power and thermal simulation considering temperature dependent leakage model. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
simulation, leakage, thermal |
39 | Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan |
Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
sub-threshold leakage, CMOS, within-die variation |
39 | Masaya Sumita |
High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
band-to band tunneling, body bias generator, dead lock, leakage components, process compensation, substrate bias, process variation, leakage current, CMOS scaling |
39 | Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita |
Transistor leakage fault location with ZDDQ measurement. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution |
37 | Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin |
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri |
Low power and high performance sram design using bank-based selective forward body bias. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
low power, high performance, body bias |
37 | Javid Jaffari, Mohab Anis |
Statistical Thermal Profile Considering Process Variations: Analysis and Applications. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran |
Fundamental Data Retention Limits in SRAM Standby Experimental Results. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
standby, data retention, low power, SRAM, error control code |
37 | Weiping Liao, Lei He 0001, Kevin M. Lepak |
Temperature and supply Voltage aware performance and power modeling at microarchitecture level. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Jun-Cheol Park, Vincent John Mooney III |
Pareto Points in SRAM Design Using the Sleepy Stack Approach. |
VLSI-SoC |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka |
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Dongwoo Lee, Harmander Deogun, David T. Blaauw, Dennis Sylvester |
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Rajiv V. Joshi, Kaushik Roy 0001 |
Design of Deep Sub-Micron CMOS Circuits. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy 0001, Vivek De |
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian |
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