|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 3849 occurrences of 1991 keywords
|
|
|
Results
Found 9295 publication records. Showing 9295 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
25 | Myeong-Hyeon Lee, Yoon-Hwa Choi |
An Easily Testable and Reconfigurable Pipeline for Symmetric Block Ciphers. |
FDTC |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Wen-Chung Kao, Sheng-Hong Wang, Wei-Hsin Chen, Lien-Yang Chen, Sheng-Yuan Lin |
Designing image processing pipeline for color imaging systems. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Lingfeng Li, Yang Song 0002, Takeshi Ikenaga, Satoshi Goto |
A CABAC Encoding Core with Dynamic Pipeline for H.264/AVC Main Profile. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Andrea Clematis, Daniele D'Agostino, Vittoria Gianuzzi |
Load Balancing and Computing Strategies in Pipeline Optimization for Parallel Visualization of 3D Irregular Meshes. |
PVM/MPI |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Yong Xiao, Runde Zhou |
Single-track asynchronous pipeline controller design. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
25 | Jin-Sung Park, So-Hyun Ryu, Yong-won Kwon, Chang-Sung Jeong |
Interactive Visualization Pipeline Architecture Using Work-Flow Management System on Grid for CFD Analysis. |
GCC |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Hai Phuong Le, Aladin Zayegh, Jugdutt Singh |
Noise Analysis of a Reduced Complexity Pipeline Analog-to-Digital Converter. |
DELTA |
2004 |
DBLP DOI BibTeX RDF |
|
25 | John Teifel, Rajit Manohar |
Programmable Asynchronous Pipeline Arrays. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
25 | M. A. Elhirbawy, Les S. Jennings, S. M. Al Dhalaan, W. W. L. Keerthipala |
Practical results and finite difference method to analyze the electric and magnetic field coupling between power transmission line and pipeline. |
ISCAS (3) |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Tao Feng, Nohpill Park, Yong-Bin Kim, Vincenzo Piuri |
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
25 | Gang Qu 0001, Miodrag Potkonjak |
Techniques for energy-efficient communication pipeline design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Marc Langenbach, Stephan Thesing, Reinhold Heckmann |
Pipeline Modeling for Timing Analysis. |
SAS |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Aristides Efthymiou, Jim D. Garside |
Adaptive Pipeline Depth Control for Processor Power-Management. |
ICCD |
2002 |
DBLP DOI BibTeX RDF |
|
25 | Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir |
Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. |
IOLTW |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Kiamal Z. Pekmestzi, Paraskevas Kalivas |
Constant Number Serial Pipeline Multipliers. |
J. VLSI Signal Process. |
2000 |
DBLP DOI BibTeX RDF |
constant number multiplication, serial multipliers, systolic circuits, canonic signed digit representation |
25 | Srihari Cadambi, Seth Copen Goldstein |
Efficient Place and Route for Pipeline Reconfigurable Architectures. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
25 | Bengt-Olaf Schneider, Jim van Welzen |
Efficient Polygon Clipping for an SIMD Graphics Pipeline. |
IEEE Trans. Vis. Comput. Graph. |
1998 |
DBLP DOI BibTeX RDF |
single-instruction multiple-data (SIMD) computer, deferred clipping, clip-plane pairs, edge batching, perspective projection, Polygon clipping |
25 | Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah |
Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1995 |
DBLP DOI BibTeX RDF |
|
23 | Qin Gu, Jizhou Sun |
A virtual reality emulation system model based on GPU computation. |
VRCAI |
2004 |
DBLP DOI BibTeX RDF |
fixed-function pipeline, programmable pipeline, virtual reality, GPU |
23 | Markus Lindgren, Hans Hansson, Henrik Thane |
Using measurements to derive the worst-case execution time. |
RTCSA |
2000 |
DBLP DOI BibTeX RDF |
execution time analysis, program flow analysis, low level timing information, low level timing analysis, program execution times, timing measurements, instrumented version, program fragments, non-exhaustive measurements, program paths, realistic processor model, scheduling, real-time systems, real time systems, embedded systems, worst-case execution time, pipeline processing, schedulability analysis, program diagnostics, architectural modeling, pipeline architectures, flow graphs, timing estimates, target architecture, system of linear equations |
23 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
Co-Scheduling Hardware and Software Pipelines. |
HPCA |
1996 |
DBLP DOI BibTeX RDF |
Classical Pipeline Theory, Software Pipelining, Pipeline Architecture, VLIW Architectures, Co-Scheduling |
23 | Kien A. Hua, Lishing Liu, Jih-Kwon Peir |
Designing High-Performance Processors Using Real Address Prediction. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
high-performance processors, real address prediction, cache access path, shorter cycle time, pipeline stages, prediction methods, pipeline processing, buffer storage, address translation |
23 | Wen-mei W. Hwu, Pohua P. Chang |
Efficient Instruction Sequencing with Inline Target Insertion. |
IEEE Trans. Computers |
1992 |
DBLP DOI BibTeX RDF |
instruction sequencing, inline target insertion, delayed branches, squashing, branch slots, program counter, parallel programming, compiler, pipeline, interrupts, program compilers, pipeline processing, exceptions |
23 | James E. Smith, Andrew R. Pleszkun |
Implementing Precise Interrupts in Pipelined Processors. |
IEEE Trans. Computers |
1988 |
DBLP DOI BibTeX RDF |
precise recovery, precise interrupt problem, saved process state, sequential model of program execution, architectural order, parallel pipeline structure, Cray-1S scalar architecture, performance evaluation, parallel architectures, interrupts, pipeline processing, system recovery, pipelined processors, performance degradation |
23 | Robert P. Roesser |
Two-Dimensional Microprocessor Pipelines for Image Processing. |
IEEE Trans. Computers |
1978 |
DBLP DOI BibTeX RDF |
two-dimensional pipeline, Digital image processor, microprocessor array, microprocessor pipeline, space-domain processing, state-space processing, parallel processors, microcomputers |
23 | Valek Szwarc, Luc Desormeaux, Wilson Wong, Clifford P. S. Yeung, Chong H. Chan, Tad A. Kwasniewski |
A chip set for pipeline and parallel pipeline FFT architectures. |
J. VLSI Signal Process. |
1994 |
DBLP DOI BibTeX RDF |
|
23 | Fang Liu, Meng-Cheng Huang, Xuehui Liu, Enhua Wu |
FreePipe: a programmable parallel rendering architecture for efficient multi-fragment effects. |
SI3D |
2010 |
DBLP DOI BibTeX RDF |
depth peeling, multi-fragment effects, order-independent transparency, programmable graphics pipeline, graphics hardware, compute unified device architecture (CUDA), rasterizer, atomic operation |
23 | Weirong Jiang, Viktor K. Prasanna |
Large-scale wire-speed packet classification on FPGAs. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fpga, decision tree, pipeline, sram, packet classification |
23 | Rupak Samanta, Ganesh Venkataraman, Nimay Shah, Jiang Hu |
Elastic Timing Scheme for Energy-Efficient and Robust Performance. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Elstic, Razor, Pipeline, Boosting |
23 | Tibor Horvath, Tarek F. Abdelzaher, Kevin Skadron, Xue Liu 0001 |
Dynamic Voltage Scaling in Multitier Web Servers with End-to-End Delay Control. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
voltage control, distributed algorithms, Power management, pipeline processing, optimization methods, network servers, soft real-time systems |
23 | Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra 0001, Xu Cheng 0001 |
A Retargetable Software Timing Analyzer Using Architecture Description Language. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
retargetable software timing analyzer, static WCET analysis, program path analysis, microarchitecture modeling, graph-based execution models, pipeline model, real-time systems, architecture description language, worst case execution time, embedded processors, branch prediction, schedulability analysis |
23 | Rama Sangireddy |
Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
Wide-issue processors, integer pipeline, rename logic complexity, front-end power consumption |
23 | David J. Duke, Malcolm Wallace, Rita Borgo, Colin Runciman |
Fine-grained Visualization Pipelines and Lazy Functional Languages. |
IEEE Trans. Vis. Comput. Graph. |
2006 |
DBLP DOI BibTeX RDF |
Pipeline model, functional programming, laziness |
23 | Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan |
The microarchitecture of FPGA-based soft processors. |
CASES |
2005 |
DBLP DOI BibTeX RDF |
Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor |
23 | Peggy B. McGee, Steven M. Nowick |
A lattice-based framework for the classification and design of asynchronous pipelines. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
protocols, framework, pipeline, asynchronous, digital design |
23 | Dharmesh Parikh, Kevin Skadron, Yan Zhang 0028, Mircea R. Stan |
Power-Aware Branch Prediction: Characterization and Design. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
target prediction, highly-biased branches, pipeline gating, speculation control, Low-power design, power, branch prediction, processor architecture, energy-aware systems, banking |
23 | Myungsook Klassen, Russell Stockard, Ali Akbari |
Stimulating information technology education among underrepresented minorities. |
SIGITE Conference |
2004 |
DBLP DOI BibTeX RDF |
computer science college major, computer science pipeline, status attainment model, underrepresented minorities, upward bound program, information technology, self-efficacy, social cognition theory |
23 | Miguel V. Correia 0002, Aurélio C. Campilho |
A Pipelined Real-Time Optical Flow Algorithm. |
ICIAR (2) |
2004 |
DBLP DOI BibTeX RDF |
pipeline hardware, real-time, optical flow, motion analysis |
23 | José A. Tierno, Sergey V. Rylov, Alexander V. Rylyakov, Montek Singh, Steven M. Nowick |
An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. |
ASYNC |
2002 |
DBLP DOI BibTeX RDF |
PRML read channel, magnetic recording, asynchronous pipeline, digital arithmetic, FIR filter, dynamic logic, high-throughput, low-latency, distributed arithmetic, mixed timing |
23 | Ryo Takata, Kenji Kise, Hiroki Honda, Toshitsugu Yuba |
DEM-1: A Particle Simulation Machine for Efficient Short-Range Interaction Computations. |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
Embedded Atom Method, Parallel architectures, Molecular dynamics, Pipeline architectures, Particle simulation |
23 | Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri |
Framework for Synthesis of Virtual Pipelines. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Virtual Pipeline, SLAAC-1V board, JHDL, FPGAs, Pipelining, Dynamic Reconfiguration, Partial Reconfiguration |
23 | Sukumar Nandi, Ch. Rambabu, Parimal Pal Chaudhuri |
A VLSI Architecture for Cellular Automata Based Reed-Solomon Decoder. |
ISPAN |
1999 |
DBLP DOI BibTeX RDF |
Cellular Automata(CA), S b EC-D b ED, Extended Reed-Soloman code, t b EC - t b ED, Cellular Automata Array(CAA), VLSI, pipeline |
23 | Gary S. Tyson, Todd M. Austin |
Improving the Accuracy and Performance of Memory Communication Through Renaming. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
data fetching, data value speculation, heap segment, instruction loading, memory access latency, memory communication, memory references, memory renaming, memory segments, processor pipeline, register access techniques, stores, performance, delays, accuracy, instruction-level parallelism, execution time, storage allocation, data dependence speculation, address calculation |
23 | Seongbae Park, SangMin Shim, Soo-Mook Moon |
Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques |
23 | Eric Persoon |
A Pipelined Image Analysis System Using Custom Integrated Circuits. |
IEEE Trans. Pattern Anal. Mach. Intell. |
1988 |
DBLP DOI BibTeX RDF |
pipelined image analysis system, custom integrated circuits, iconic image-processing, mask generation, programmable image delay, subsample filtering, computer vision, computerised picture processing, pipeline processing, shape recognition, digital integrated circuits, computer vision system |
22 | Umeshwar Dayal, Malú Castellanos, Alkis Simitsis, Kevin Wilkinson |
Data integration flows for business intelligence. |
EDBT |
2009 |
DBLP DOI BibTeX RDF |
data integration, data warehousing, business intelligence, ETL |
22 | Jie Chen 0007, Baoquan Chen |
Architectural Modeling from Sparsely Scanned Range Data. |
Int. J. Comput. Vis. |
2008 |
DBLP DOI BibTeX RDF |
Geometry reconstruction, Range image, 3D scanning |
22 | Weirong Jiang, Viktor K. Prasanna |
Parallel IP lookup using multiple SRAM-based pipelines. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Jason Ridenour, Jianghai Hu, Nathaniel Pettis, Yung-Hsiang Lu |
Low-Power Buffer Management for Streaming Data. |
IEEE Trans. Circuits Syst. Video Technol. |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija |
Energy optimization of pipelined digital systems using circuit sizing and supply scaling. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Xianfeng Li, Abhik Roychoudhury, Tulika Mitra |
Modeling out-of-order processors for WCET analysis. |
Real Time Syst. |
2006 |
DBLP DOI BibTeX RDF |
Worst-case execution time (WCET) analysis, Out-of-order superscalar processor, Branch prediction, Instruction cache |
22 | Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu |
Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
cache-miss tolerance, prefetching, out-of-order execution, Runahead execution |
22 | Juan L. Aragón, José M. González, Antonio González 0001 |
Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
low-power design, processor architecture, energy-aware systems, Control speculation |
22 | Christopher T. Johnston, Donald G. Bailey, Paul J. Lyons |
Towards a visual notation for pipelining in a visual programming language for programming FPGAs. |
CHINZ |
2006 |
DBLP DOI BibTeX RDF |
FPGA, pipelining, visual programming language |
22 | Wonbok Lee, Kimish Patel, Massoud Pedram |
B2Sim: : a fast micro-architecture simulator based on basic block characterization. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
basic block, micro-architecture simulation, program behavior |
22 | Manjunath Kudlur, Kevin Fan, Scott A. Mahlke |
Streamroller: : automatic synthesis of prescribed throughput accelerator pipelines. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
system-level synthesis, loop accelerator, application-specific hardware |
22 | Michael Attig, Gordon J. Brebner |
Systematic Characterization of Programmable Packet Processing Pipelines. |
FCCM |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Rahul P. Maddimsetty, Jeremy Buhler, Roger D. Chamberlain, Mark A. Franklin, Brandon Harris |
Accelerator design for protein sequence HMM search. |
ICS |
2006 |
DBLP DOI BibTeX RDF |
protein motif, hidden Markov model, HMMER |
22 | Minmin Han, Christine Hofmeister |
Modeling Request Routing in Web Applications. |
WSE |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Zuqiu Mao, Jiaoying Shi |
TOIGP: a new hierarchical depth occlusion. |
VRCIA |
2006 |
DBLP DOI BibTeX RDF |
hierarchical depth, triangle occlusion, occlusion culling, bound box, 3D graphics hardware |
22 | Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede |
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Daniel A. Jiménez, Gabriel H. Loh |
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. |
SBAC-PAD |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi 0001 |
Systematic software-based self-test for pipelined processors. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
functional testing, software-based self-test, processor testing |
22 | Jahangir Hasan, T. N. Vijaykumar |
Dynamic pipelining: making IP-lookup truly scalable. |
SIGCOMM |
2005 |
DBLP DOI BibTeX RDF |
scalable, pipelined, IP-lookup, longest prefix matching, tries |
22 | Wei Ling, Yvon Savaria |
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Billy Chen, Eyal Ofek, Heung-Yeung Shum, Marc Levoy |
Interactive deformation of light fields. |
SI3D |
2005 |
DBLP DOI BibTeX RDF |
image-based rendering, deformation, light fields, 3D photography |
22 | Nisrine Saadallah, Xiaohua Kong, Radu Negulescu |
High-Speed Reduced Stack Dual Lock Circuits. |
ASYNC |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu |
Beating in-order stalls with "flea-flicker" two-pass pipelining. |
MICRO |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Masatoshi Kameyama, Yoshiyuki Kato, Hitoshi Fujimoto, Hiroyasu Negishi, Yukio Kodama, Yoshitsugu Inoue, Hiroyuki Kawai |
3D graphics LSI core for mobile phone "Z3D". |
Graphics Hardware |
2003 |
DBLP DOI BibTeX RDF |
graphics accelerator, graphics hardware, rendering hardware |
22 | Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria |
An instruction-level energy model for embedded VLIW architectures. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma |
Optimizing pipelines for power and performance. |
MICRO |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Juan L. Aragón, José González 0002, Antonio González 0001, James E. Smith 0001 |
Dual path instruction processing. |
ICS |
2002 |
DBLP DOI BibTeX RDF |
branch misprediction penalty, dual path processing, pre-scheduling, confidence estimation |
22 | Chee How Lim, W. Robert Daasch, George Cai |
A Thermal-Aware Superscalar Microprocessor (invited). |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Kalyan Muthukumar, Gautam Doshi |
Software Pipelining of Nested Loops. |
CC |
2001 |
DBLP DOI BibTeX RDF |
|
22 | G. Hariprakash, R. Achutharaman, Amos Omondi |
DSTRIDE: Data-Cache Miss-Address-Based Stride Prefetching Scheme for Multimedia Processors. |
ACSAC |
2001 |
DBLP DOI BibTeX RDF |
|
22 | Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao |
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Yasunori Nagata, D. Michael Miller, Masao Mukaidono |
B-ternary Logic Based Asynchronous Micropipeline. |
ISMVL |
1999 |
DBLP DOI BibTeX RDF |
|
22 | Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto |
Multiple instruction streams in a highly pipelined processor. |
SPDP |
1990 |
DBLP DOI BibTeX RDF |
|
22 | Roger L. Wainwright |
Parallel Sieve Algorithms on a Hypercube Multiprocessor. |
ACM Conference on Computer Science |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Desi Rhoden, Chris Wilcox |
Hardware acceleration for Window systems. |
SIGGRAPH |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang |
Comparing Software and Hardware Schemes For Reducing the Cost of Branches. |
ISCA |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Michael Deering, Stephanie Winner, Bic Schediwy, Chris Duffy, Neil Hunt |
The triangle processor and normal vector shader: a VLSI system for high performance graphics. |
SIGGRAPH |
1988 |
DBLP DOI BibTeX RDF |
graphics VLSI, hardware lighting models, real-time image display, triangle processor, interpolation, shading |
20 | Shenglin Gui, Lei Luo 0004 |
End-to-End Schedulability Analysis for Bi-directional Real-Time Multistage Pipeline. |
ISPA |
2011 |
DBLP DOI BibTeX RDF |
generalized pipeline system, end-to-end schedulability analysis |
20 | Xiaoqiang Li, Hong An, Gu Liu, Wenting Han, Mu Xu, Wei Zhou, Qi Li 0034 |
A Non-blocking Programming Framework for Pipeline Application on Multi-core Platform. |
ISPA |
2011 |
DBLP DOI BibTeX RDF |
pipeline, programming model, work-stealing |
20 | Bo Wang, Shifeng Shang, Qiming Fang, Weimin Zheng |
Parallel Task Developing Based on Software Pipeline in Multicore System. |
ISPA |
2010 |
DBLP DOI BibTeX RDF |
parallel task building, software pipeline, multicore system |
20 | Yu Song, Xuping Jiang |
Modeling and Application of OPNET-Based Pipeline Stages for HF Channel Simulation. |
IFITA (3) |
2009 |
DBLP DOI BibTeX RDF |
HF channel, wireless channel pipeline stages, simulation, modeling, OPNET |
20 | Zheng-wei Hu, Dong-xing Duan, Zhi-yuan Xie, Xing Yang |
Pipeline Design of Transformation between Floating Point Numbers Based on IEEE754 Standard and 32-bit Integer Numbers. |
IITSI |
2009 |
DBLP DOI BibTeX RDF |
ieee754 standard, floating-point data, pipeline, data transform |
20 | Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh |
Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip. |
ITNG |
2009 |
DBLP DOI BibTeX RDF |
parallel and pipeline processing, security, network-on-chip, block cipher, software implementation |
20 | Xiumin Wang, Yang Zhang, Qiang Ye, Shihua Yang |
A New Algorithm for Designing Square Root Calculators Based on FPGA with Pipeline Technology. |
HIS (1) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, algorithm, pipeline, square root, Verilog HDL |
20 | Guangzhong Sun, Guoliang Chen 0001 |
Distributed Pipeline Programming Framework for State-Based Pattern. |
GCC |
2009 |
DBLP DOI BibTeX RDF |
Distributed Pipeline, State pattern, Object-passing, Distributed programming |
20 | Ahmad Tahmasebi, Arash Kamali, Hossein Balazadeh Bahar, Ziaeddin Daie Koozeh Kanani |
A Fully Digital Background Calibration Technique for Pipeline Analog-to-Digital Converters. |
ICSAP |
2009 |
DBLP DOI BibTeX RDF |
digital calibration, pipeline converters, Analog to digital converter (ADC) |
20 | Ahmad Tahmasebi, Arash Kamali, Ziaeddin Daie Koozeh Kanani, Jafar Sobhi |
A Simple Background Interstage Gain Calibration Technique for Pipeline ADCs. |
ICSAP |
2009 |
DBLP DOI BibTeX RDF |
Reference ADC, Stage gain, Pipeline, Calibration, Analog-to-digital converter (ADC) |
20 | Bin Zhou, David Hwang |
Implementations and Optimizations of Pipeline FFTs on Xilinx FPGAs. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Pipeline FFTs, FPGAs |
20 | Welson Sun, Michael J. Wirthlin, Stephen Neuendorffer |
Combining module selection and resource sharing for efficient FPGA pipeline synthesis. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
resource sharing, pipeline scheduling, module selection, data-path synthesis |
20 | Young-Cheol Bang, Hyunseung Choo |
On Bandwidth Adjusted Multicast Communications in Pipeline Router Architecture. |
J. Supercomput. |
2005 |
DBLP DOI BibTeX RDF |
cut-through, quality of service, multicast, pipeline, bandwidth |
20 | Friedhelm Stappert, Andreas Ermedahl, Jakob Engblom |
Efficient longest executable path search for programs with complex flows and pipeline effects. |
CASES |
2001 |
DBLP DOI BibTeX RDF |
pipeline timing, program flow, embedded systems, WCET, hard real-time, path search |
20 | Adam M. Fass, Eric A. Bier, Eytan Adar |
PicturePiper: using a re-configurable pipeline to find images on the Web. |
UIST |
2000 |
DBLP DOI BibTeX RDF |
image retrieval, pipeline, dataflow, WWW searching |
20 | SangMin Shim, Soo-Mook Moon |
Split-path Enhanced Pipeline Scheduling for Loops with Control Flows. |
MICRO |
1998 |
DBLP DOI BibTeX RDF |
all-path pipelining, enhanced pipeline scheduling, initiation interval, multi-path loops, software pipelining, modulo scheduling |
20 | Pei-Hsin Ho, Adrian J. Isles, Timothy Kam |
Formal verification of pipeline control using controlled token nets and abstract interpretation. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
controlled token net, pipeline control verification, model checking, formal verification, computer-aided design, abstract interpretation, functional verification, processor verification |
20 | Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt |
Two-Phase Asynchronous Pipeline Control. |
ASYNC |
1997 |
DBLP DOI BibTeX RDF |
two-phase asynchronous pipeline control, bounded-delay model, prototype microprocessor, microprocessor chips |
Displaying result #201 - #300 of 9295 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ 11][ 12][ >>] |
|