Search results for "latches"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Suwen Yang, Brian D. Winters, Mark R. Greenstreet	Energy Efficient Surfing.	ASYNC	2005	DBLP DOI BibTeX RDF
11	K. Praveen Jayakar Thomas, Ram Singh Rana, Yong Lian 0001	A 1GHz CMOS fourth-order continuous-time bandpass sigma delta modulator for RF receiver front end A/D conversion.	ASP-DAC	2005	DBLP DOI BibTeX RDF
11	Indradeep Ghosh	High Level Test Generation for Custom Hardware: An Industrial Perspective.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
11	Soonhak Kwon, Chang Kim, Chun Pyo Hong	Unidirectional Two Dimensional Systolic Array for Multiplication in GF(2m) Using LSB First Algorithm.	WILF	2005	DBLP DOI BibTeX RDF	LSB first algorithm, VLSI, finite field, Systolic array, data flow, fault tolerant architecture
11	Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Yung-Cheng Ma	A multiplication-accumulation computation unit with optimized compressors and minimized switching activities.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
11	Ming Zhang 0017, Naresh R. Shanbhag	An energy-efficient circuit technique for single event transient noise-tolerance.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
11	Zhiyuan Yan, Dilip V. Sarwate	Area-efficient two-dimensional architectures for finite field inversion and division.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	cryptography, finite field, Reed-Solomon codes, arithmetic, galois field
11	Hossein Asadi 0001, Mehdi Baradaran Tahoori	Soft Error Modeling and Protection for Sequential Elements.	DFT	2005	DBLP DOI BibTeX RDF
11	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Dual-Edge Triggered Static Pulsed Flip-Flops.	VLSI Design	2005	DBLP DOI BibTeX RDF
11	Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang	Logic soft errors in sub-65nm technologies design and CAD challenges.	DAC	2005	DBLP DOI BibTeX RDF	architectural vulnerability factor, built-in soft error resilience, derating, error blocking, error detection, recovery, soft error
11	Peter-Michael Seidel, Guy Even	Delay-Optimized Implementation of IEEE Floating-Point Addition.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	IEEE rounding, dual path algorithm, optimized gate sizing, buffer insertion, delay optimization, logical effort, Floating-point addition
11	Soumitra Bose	Modeling Custom Digital Circuits for Test.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	ATPG, fault simulation, logic simulation, switch-level modeling
11	Seok Il Song, Young Ho Kim, Jae Soo Yoo	An Enhanced Concurrency Control Scheme for Multidimensional Index Structures.	IEEE Trans. Knowl. Data Eng.	2004	DBLP DOI BibTeX RDF	performance evaluation, Concurrency control, multidimensional index structure
11	J. A. Palmer, James F. Mulling, Brian Dessent, Edward Grant, Jeffrey W. Eischen, Alexei Gruverman, A. I. Kingon, Paul D. Franzon	The Design, Fabrication, and Characterization of Millimeter Scale Motors for Miniature Direct Drive Robots.	ICRA	2004	DBLP DOI BibTeX RDF
11	Delong Shang, Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Danil Sokolov, Alexandre Yakovlev	A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
11	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline Design Based on Self-Resetting Stage Logic.	ISVLSI	2004	DBLP DOI BibTeX RDF
11	Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska	Eliminating False Positives in Crosstalk Noise Analysis.	DATE	2004	DBLP DOI BibTeX RDF
11	Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards	Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits.	DATE	2004	DBLP DOI BibTeX RDF
11	Ron Ho, Jonathan Gainsley, Robert J. Drost	Long Wires and Asynchronous Control.	ASYNC	2004	DBLP DOI BibTeX RDF
11	Il-soo Lee, Yong Min Hur, Tony Ambler	The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
11	Minoru Watanabe, Fuminori Kobayashi	A High-Density Optically Reconfigurable Gate Array Using Dynamic Method.	FPL	2004	DBLP DOI BibTeX RDF
11	Mario R. Casu, Luca Macchiarulo	Floorplanning for throughput.	ISPD	2004	DBLP DOI BibTeX RDF	systems-on-chip, throughput, floorplanning, wire pipelining
11	Ruiming Chen, Hai Zhou 0001	Clock schedule verification under process variations.	ICCAD	2004	DBLP DOI BibTeX RDF
11	Sani R. Nassif	The impact of variability on power.	ISLPED	2004	DBLP DOI BibTeX RDF	power, variability, integrated circuit
11	Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy 0001	A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies.	ISLPED	2004	DBLP DOI BibTeX RDF	DSM leakage control and scaling trends, dual supply ALU design, low power techniques
11	Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang	Nanoscale CMOS circuit leakage power reduction by double-gate device.	ISLPED	2004	DBLP DOI BibTeX RDF	double-gate device, short-channel effect, leakage power
11	Masayuki Tsukisaka, Masashi Imai, Takashi Nanya	Asynchronous Scan-Latch controller for Low Area Overhead DFT.	ICCD	2004	DBLP DOI BibTeX RDF
11	Chunyan Wang 0004, Kuo-Ting Wu	Design of a pixel array circuit for thinning process.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
11	Abdel Ejnioui, Abdelhalim Alsharqawi	Self-resetting stage logic pipelines.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	clockless, self-resetting, pipeline, asynchronous
11	Peilin Song, Franco Stellari, Alan J. Weger, Tian Xia	A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current.	ITC	2004	DBLP DOI BibTeX RDF
11	T. Thorp, D. Liu, P. Trivedi	Analysis of blocking dynamic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
11	Soha Hassoun, Christopher Cromer, Eduardo H. Calvillo Gámez	Static timing analysis for level-clocked circuits in the presence of crosstalk.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
11	Edmund M. Clarke, Orna Grumberg, Somesh Jha, Yuan Lu 0004, Helmut Veith	Counterexample-guided abstraction refinement for symbolic model checking.	J. ACM	2003	DBLP DOI BibTeX RDF	temporal logic, Abstraction, symbolic model checking, hardware verification
11	Hai Zhou 0001	Timing Verification with Crosstalk for Transparently Latched Circuits.	DATE	2003	DBLP DOI BibTeX RDF
11	Hai Li 0001, Swarup Bhunia, Yiran Chen 0001, T. N. Vijaykumar, Kaushik Roy 0001	Deterministic Clock Gating for Microprocessor Power Reduction.	HPCA	2003	DBLP DOI BibTeX RDF
11	Aristides Efthymiou, Jim D. Garside	Adaptive Pipeline Structures fo Speculation Control.	ASYNC	2003	DBLP DOI BibTeX RDF
11	Nikhil Jayakumar, Sunil P. Khatri	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.	ISLPED	2003	DBLP DOI BibTeX RDF	standby current, leakage current, standard cells, MTCMOS
11	Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev 0001, Kanad Ghose	Distributed Reorder Buffer Schemes for Low Power.	ICCD	2003	DBLP DOI BibTeX RDF
11	Pak-Keung Leung, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	A low power asynchronous GF(2173) ALU for elliptic curve crypto-processor.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
11	Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa	On the Design of a Register Queue Based Processor Architecture (FaRM-rq).	ISPA	2003	DBLP DOI BibTeX RDF
11	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Novel Transient Fault Hardened Static Latch.	ITC	2003	DBLP DOI BibTeX RDF
11	Kun Young Chung, Sandeep K. Gupta 0001	Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing.	ITC	2003	DBLP DOI BibTeX RDF
11	Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska	Temporofunctional crosstalk noise analysis.	DAC	2003	DBLP DOI BibTeX RDF	SAT formula, timed Boolean logic, crosstalk noise
11	Premkishore Shivakumar, Michael Kistler, Stephen W. Keckler, Doug Burger, Lorenzo Alvisi	Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic.	DSN	2002	DBLP DOI BibTeX RDF
11	Soha Hassoun, Eduardo H. Calvillo Gámez, Christopher Cromer	Verifying Clock Schedules in the Presence of Cross Talk.	DATE	2002	DBLP DOI BibTeX RDF
11	Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg	A case for dynamic pipeline scaling.	CASES	2002	DBLP DOI BibTeX RDF	configurable pipeline, fetch gating, power and energy management, shallow and deep pipelines, variable-depth pipeline, dynamic voltage scaling, clock gating
11	Aristides Efthymiou, Jim D. Garside	Adaptive Pipeline Depth Control for Processor Power-Management.	ICCD	2002	DBLP DOI BibTeX RDF
11	Tyler Thorp, Dean Liu	Analysis of Blocking Dynamic Circuits.	ICCD	2002	DBLP DOI BibTeX RDF
11	Hai Zhou 0001	Clock schedule verification with crosstalk.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	verification, delay, coupling, clock schedule
11	Baris Taskin, Ivan S. Kourtev	Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	optimization, linear programming, clock skew, cycle stealing
11	Soonhak Kwon	Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields.	ICICS	2002	DBLP DOI BibTeX RDF	systolic multiplier, finite field, basis, all one polynomial
11	Chiou-Yng Lee, Ya-Cheng Lu, Erl-Huei Lu	Low-complexity systolic multiplier over GF(2m) using weakly dual basis.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
11	Martin Foltin, Brian Foutz, Sean Tyler	Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency.	DAC	2002	DBLP DOI BibTeX RDF	timing analysis, VLSI design, timing model, circuit optimization
11	François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer	Optimal design of synchronous circuits using software pipelining techniques.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	software pipelining, retiming, Resynthesis
11	Amit Singh 0001, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska	Interconnect pipelining in a throughput-intensive FPGA architecture.	FPGA	2001	DBLP DOI BibTeX RDF
11	Shanq-Jang Ruan, Jen-Chiun Lin, Po-Hung Chen, Kun-Lin Tsai, Feipei Lai	Synthesis of partition-codec architecture for low power and small area circuit design.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
11	Michele Favalli, Cecilia Metra	Bridging Faults in Pipelined Circuits.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	fault modeling, bridging faults, CMOS circuits, pipelined circuits
11	Nikolai Starodoubtsev, Alexandre V. Bystrov, Alexandre Yakovlev	Semi-modular Latch Chains for Asynchronous Circuit Design.	PATMOS	2000	DBLP DOI BibTeX RDF
11	Saeid Nooshabadi, Juan A. Montiel-Nelson, Antonio Núñez, Roberto Sarmiento, Javier Sosa	A Single Phase Latch for High Speed GaAs Domino Circuits.	DATE	2000	DBLP DOI BibTeX RDF
11	José Antonio Sainz, R. Muñoz, J. A. Maiz, L. A. Aguado, Miquel Roca 0001	A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits.	IOLTW	2000	DBLP DOI BibTeX RDF	VLSI, Sensor, CMOS, Crosstalk, Digital
11	José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan	A wave-pipelined router architecture using ternary associative memory.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
11	Luca de Alfaro, Thomas A. Henzinger, Freddy Y. C. Mang	The Control of Synchronous Systems.	CONCUR	2000	DBLP DOI BibTeX RDF
11	Gianpiero Cabodi, Stefano Quer, Fabio Somenzi	Optimizing sequential verification by retiming transformations.	DAC	2000	DBLP DOI BibTeX RDF
11	Victor V. Zyuban, Peter M. Kogge	Application of STD to latch-power estimation.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
11	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith	Timing constraints for high-speed counterflow-clocked pipelining.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
11	Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey	Power management in high-level synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
11	David L. Harris, Mark Horowitz, Dean Liu	Timing analysis including clock skew.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
11	Zbigniew Kalbarczyk, Ravishankar K. Iyer, Gregory L. Ries, Jaqdish U. Patel, Myeong S. Lee, Yuxiao Xiao	Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation.	IEEE Trans. Software Eng.	1999	DBLP DOI BibTeX RDF	Hierarchical simulation, accurate fault modeling, dependability evaluation, fault dictionaries
11	Kedar S. Namjoshi, Robert P. Kurshan	Efficient Analysis of Cyclic Definitions.	CAV	1999	DBLP DOI BibTeX RDF
11	Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury	Reconfigurable Latch Controllers for Low Power Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
11	Oliver Hauck, M. Garg, Sorin A. Huss	Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT.	ASYNC	1999	DBLP DOI BibTeX RDF
11	Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr.	A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
11	B. Le Chapelain, A. Mechain, Yvon Savaria, Guy Bois	Development of a high performance TSPC library for implementation of large digital building blocks.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
11	Robert C. Aitken	Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage.	VTS	1999	DBLP DOI BibTeX RDF
11	Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa	Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis.	VLSI Design	1999	DBLP DOI BibTeX RDF
11	S. K. Jain, Leilei Song, Keshab K. Parhi	Efficient semisystolic architectures for finite-field arithmetic.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
11	Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu	Wave-pipelining: a tutorial and research survey.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
11	Masahiro Fujii, Keiichi Numata, Tadashi Maeda, Masatoshi Tokushima, Shigeki Wada, Muneo Fukaishi, Masaoki Ishikawa	A 150 mW 8: 1 MUX and a 170 mW 1: 8 DEMUX for 2.4 gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
11	Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev	Hazard-free implementation of speed-independent circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
11	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	statistical fault analysis, fault simulation, delay test, path-delay faults, transition faults
11	Sorin Cotofana, Stamatis Vassiliadis	Periodic symmetric functions, serial addition, and multiplication with neural networks.	IEEE Trans. Neural Networks	1998	DBLP DOI BibTeX RDF
11	Ludovic Jacomme, Frédéric Pétrot, Rajesh K. Bawa	Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis.	EUROMICRO	1998	DBLP DOI BibTeX RDF
11	Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger	Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment.	DAC	1998	DBLP DOI BibTeX RDF
11	Rumen Andonov, Sanjay V. Rajopadhye	Knapsack on VLSI: from Algorithm to Optimal Circuit.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Application specific VLSI design, unbounded knapsack problem, space-time transformations, recurrence equations, dynamic dependencies, nonlinear discrete optimization, correctness preserving transformations, systolic arrays
11	Eric M. Schwarz, Robert M. Averill III, Leon J. Sigal	A Radix-8 CMOS S/390 Multiplier.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	Booth algorithm, computer arithmetic, multiplication, multiplier, floating-point unit
11	Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar	A hierarchical decomposition methodology for multistage clock circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	performance driven router, routing, process variations, manufacturability, clock
11	Charles J. DeVane	Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	cycle simulation, levelized compiled code, logic simulation, circuit partitioning
11	Stephen B. Furber, Paul Day	Four-phase micropipeline latch control circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
11	Andrzej Krasniewski	Design of Dependable Hardware: What BIST is most Efficient?	EDCC	1996	DBLP DOI BibTeX RDF
11	David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah	Timing verification of sequential domino circuits.	ICCAD	1996	DBLP DOI BibTeX RDF	domino gates, sequential domino circuits, static timing verification, logic testing, input signals
11	Naresh Maheshwari, Sachin S. Sapatnekar	A Practical Algorithm for Retiming Level-Clocked Circuits.	ICCD	1996	DBLP DOI BibTeX RDF	level-clocked, retiming, clock skew, timing optimization
11	Zaifu Zhang, Robert D. McLeod	An Efficient Multiple Scan Chain Testing Scheme.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
11	Maher E. Rizkalla, Richard L. Aldridge, Nadeem A. Khan, Harry C. Gundrum	A CMOS VLSI Implementation of an NxN Multiplexing Circuitry for ATM Applications.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
11	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen	On Verifying the Correctness of Retimed Circuits.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	3-valued equivalence, delay-compensation, sequential ATPG, formal verification, retiming, equivalence-Checking
11	Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas	Statistical path delay fault coverage estimation for synchronous sequential circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	path delay fault coverage estimation, multi-valued algebra, signal statistics, latch updating, fault diagnosis, logic testing, delays, probability, controllability, controllability, statistical analysis, sequential circuits, observability, observabilities, logic simulation, synchronous sequential circuits, statistical estimation
11	Paul Day, John V. Woods	Investigation into micropipeline latch design styles.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
11	William P. Marnane, Will R. Moore	Testing VLSI regular arrays.	J. Electron. Test.	1995	DBLP DOI BibTeX RDF	testing regular arrays, C-testability, test vector generation
11	K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.	Parallel reduced area multipliers.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
11	Ajay Khoche, Erik Brunvand	Testing self-timed circuits using partial scan.	ASYNC	1995	DBLP DOI BibTeX RDF	sequential network, partial scan environment, logic testing, sequential circuits, asynchronous circuits, partial scan, data paths, self-timed circuits
11	Soumitra Bose, Vishwani D. Agrawal	Sequential logic path delay test generation by symbolic analysis.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions