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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 989 occurrences of 488 keywords
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Results
Found 3882 publication records. Showing 3880 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang |
An Analytical Delay Model for SRAM-Based FPGA Interconnections. |
ASP-DAC |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Vincenzo Piuri |
Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs. |
DFT |
1999 |
DBLP DOI BibTeX RDF |
Self-checking systems, Field Programmable Gate Arrays, Artificial neural networks, Space applications |
19 | Jian Xu, Paifa Si, Wei-Kang Huang, Fabrizio Lombardi |
A Novel Fault Tolerant Approach for SRAM-Based FPGAs. |
PRDC |
1999 |
DBLP DOI BibTeX RDF |
FPGA, fault-tolerant routing, fault-tolerant architecture |
19 | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
19 | James G. Eldredge, Brad L. Hutchings |
Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs. |
J. VLSI Signal Process. |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra |
Efficient FPGAs using nanoelectromechanical relays. |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
CMOS-NEM FPGA, nanoelectromechanical relay |
16 | Hoang Le, Yi-Hua E. Yang, Viktor K. Prasanna |
Memory efficient string matching: a modular approach on FPGAs (abstract only). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
deep packet classification, fpga, packet filtering |
16 | Niti Madan, Li Zhao 0002, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer 0001, Srihari Makineni, Donald Newell |
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke |
Enabling ultra low voltage system operation by tolerating on-chip cache failures. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
fault-tolerant cache, low voltage operation, dynamic voltage scaling |
16 | Junghwan Kim, Myeong-Cheol Ko, Hyun-Kyu Kang, Jinsoo Kim 0002 |
A Hybrid IP Forwarding Engine with High Performance and Low Power. |
ICCSA (2) |
2009 |
DBLP DOI BibTeX RDF |
TCAM partitioning, a hybrid architecture, power saving, IP address lookup |
16 | Sundar Iyer, Ramana Rao Kompella, Nick McKeown |
Designing packet buffers for router linecards. |
IEEE/ACM Trans. Netw. |
2008 |
DBLP DOI BibTeX RDF |
hit-rate, line-card, cache, memory hierarchy, router, switches, packet buffer |
16 | Yongsoo Joo, Yongseok Choi, Jaehyun Park 0005, Chanik Park, Sung Woo Chung, Eui-Young Chung, Naehyuck Chang |
Energy and Performance Optimization of Demand Paging With OneNAND Flash. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Eun-Tack Oh, Kwang-Sung Jung, Sung-Min Lee, Cheol-Hong Moon |
An Embedded SoC System IP to Trace Object and Distance. |
ICIC (1) |
2008 |
DBLP DOI BibTeX RDF |
Embedded SoC, IP Develop, Image Process, CCD Cameras |
16 | Valeri Kirischian, Vadim Geurkov, Lev Kirischian |
A multi-mode video-stream processor with cyclically reconfigurable architecture. |
Conf. Computing Frontiers |
2008 |
DBLP DOI BibTeX RDF |
cost-performance ratio, video-stream processor, FPGA, computer architecture, reconfigurable computing, dynamic reconfiguration, pre-fetching, temporal partitioning |
16 | Xiangyu Dong, Xiaoxia Wu, Guangyu Sun 0003, Yuan Xie 0001, Hai Li 0001, Yiran Chen 0001 |
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
3D stacking, MRAM |
16 | Nan Hua, Bill Lin 0001, Jun (Jim) Xu, Haiquan (Chuck) Zhao |
BRICK: a novel exact active statistics counter architecture. |
ANCS |
2008 |
DBLP DOI BibTeX RDF |
statistics counter, router |
16 | Yu-Wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Hung-Chi Fang, Liang-Gee Chen |
124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory. |
IEEE Trans. Circuits Syst. Video Technol. |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Michael G. Benjamin, David R. Kaeli |
Stream Image Processing on a Dual-Core Embedded System. |
SAMOS |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks |
Process Variation Tolerant 3T1D-Based Cache Architectures. |
MICRO |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Kang Yi, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil |
An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories. |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP DOI BibTeX RDF |
Embedded memory Yield, Defect Map, Memory Error Resilient Design, Video error concealment |
16 | Yu Zhou, Shijo Thekkel, Swarup Bhunia |
Low power FPGA design using hybrid CMOS-NEMS approach. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
hybrid CMOS-NEMS, low power, FPGA design |
16 | Thinh Ngoc Tran, Surin Kittitornkun |
FPGA-Based Cuckoo Hashing for Pattern Matching in NIDS/NIPS. |
APNOMS |
2007 |
DBLP DOI BibTeX RDF |
NIPS, FPGA, Pattern Matching, NIDS, Cuckoo Hashing |
16 | Valentina Salapura, José R. Brunheroto, Fernando F. Redígolo, Alan Gara |
Exploiting eDRAM bandwidth with data prefetching: simulation and measurements. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Sayeed A. Badrudduza, Giby Samson, Lawrence T. Clark |
LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Jorge Guajardo, Sandeep S. Kumar, Geert Jan Schrijen, Pim Tuyls |
FPGA Intrinsic PUFs and Their Use for IP Protection. |
CHES |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Hamed F. Dadgour, Kaustav Banerjee |
Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy 0001 |
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, T. Balsara |
A nonredundant ternary CAM circuit for network search engines. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Shen-Fu Hsiao, Yo-Chi Chen, Ming-Yu Tsai, Tze-Chong Cheng |
Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding. |
MTDT |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Yongsoo Joo, Yongseok Choi, Chanik Park, Sung Woo Chung, Eui-Young Chung, Naehyuck Chang |
Demand paging for OneNANDTM Flash eXecute-in-place. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
OneNAND, XIP, embedded systems, virtual memory, NAND flash memory, demand paging, page replacement |
16 | Sailesh Kumar, John Maschmeyer, Patrick Crowley |
Exploiting locality to ameliorate packet queue contention and serialization. |
Conf. Computing Frontiers |
2006 |
DBLP DOI BibTeX RDF |
packet queuing, cache, buffering |
16 | Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo |
Leakage energy reduction techniques in deep submicron cache memories: a comparative study. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Yi-Chih Chao, Ji-Kun Lin, Jar-Ferr Yang, Bin-Da Liu |
A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Masanori Hariyama, Michitaka Kameyama |
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Shen-Fu Hsiao, Sze-Yun Lin, Tze-Chong Cheng, Ming-Yu Tsai |
An Automatic Cache Generator Based on Content-Addressable Memory. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Mahdi Nazm Bojnordi, Naser Sedaghati-Mokhtari, Omid Fatemi, Mahmoud Reza Hashemi |
An Efficient Self-Transposing Memory Structure for 32-bit Video Processors. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Yan Lin 0001, Fei Li 0003, Lei He 0001 |
Circuits and architectures for field programmable gate array with configurable supply voltage. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Amit Agarwal 0001, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy 0001 |
A process-tolerant cache architecture for improved yield in nanoscale technologies. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Vijay Degalahal, Lin Li 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin |
Soft errors issues in low-power caches. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Yan Lin 0001, Fei Li 0003, Lei He 0001 |
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd |
16 | Somsubhra Mondal, Seda Ogrenci Memik, Debasish Das |
Hierarchical LUT structures for leakage power reduction (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Hamid R. Zarandi, Seyed Ghassem Miremadi |
Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme. |
LADC |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Kiran Puttaswamy, Gabriel H. Loh |
Implementing Caches in a 3D Technology for High Performance Processors. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo |
Variable precision arithmetic circuits for FPGA-based multimedia processors. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Bin Sheng, Wen Gao 0001, Di Wu 0022 |
An implemented architecture of deblocking filter for H.264/AVC. |
ICIP |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Jason Hiser, Jack W. Davidson |
EMBARC: an efficient memory bank assignment algorithm for retargetable compilers. |
LCTES |
2004 |
DBLP DOI BibTeX RDF |
partition assignment, embedded systems, retargetable compilers |
16 | Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson |
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Joohee Kim, Conrad H. Ziesler |
Fixed-Load Energy Recovery Memory for Low Power. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Ramesh V. Peri, John Fernando, Ravi K. Kolagotla |
Addressing mode driven low power data caches for embedded processors. |
WMPI |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie 0001, Mary Jane Irwin |
Improving soft-error tolerance of FPGA configuration bits. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Yajun Ran, Malgorzata Marek-Sadowska |
The Magic of a Via-Configurable Regular Fabric. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Amit Agarwal 0001, Bipul Chandra Paul, Kaushik Roy 0001 |
A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. |
IOLTS |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Bo-Sung Kim, Young-Gi Kim, Soon-Yang Hong |
Low Power 260 k Color TFT LCD One-Chip Driver IC. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri |
March iC-: An Improved Version of March C- for ADOFs Detection. |
VTS |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Jorge García-Vidal, Jesús Corbal, Llorenç Cerdà, Mateo Valero |
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers. |
MICRO |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Philip Machanick, Zunaid Patel |
L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy. |
Asia-Pacific Computer Systems Architecture Conference |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino |
Layout-driven memory synthesis for embedded systems-on-chip. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Cristian Estan, George Varghese, Mike Fisk |
Counting the number of active flows on a high speed link. |
Comput. Commun. Rev. |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall |
Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS. |
ASAP |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar |
Reducing leakage in a high-performance deep-submicron instruction cache. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Jong Won Park |
An Efficient Buffer Memory System for Subarray Access. |
IEEE Trans. Parallel Distributed Syst. |
2001 |
DBLP DOI BibTeX RDF |
High-resolution graphical display, buffer memory system, block access, address routing, memory module selection, image processing, address calculation |
16 | Gerhard Lienhart, Reinhard Männer, Klaus-Henning Noffz, Ralf Lay |
An FPGA-based video compressor for H.263 compatible bit streams. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
distributed arithmetic |
16 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems. |
ACM Trans. Design Autom. Electr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
system design, data cache, data partitioning, system synthesis, scratch-pad memory, on-chip memory, memory synthesis |
16 | Sandeep Sikka, George Varghese |
Memory-efficient state lookups with fast updates. |
SIGCOMM |
2000 |
DBLP DOI BibTeX RDF |
TCP/IP |
16 | Chuang Cheng, Chih-Tsun Huang, Jing-Reng Huang, Cheng-Wen Wu, Chen-Jong Wey, Ming-Chang Tsai |
BRAINS: A BIST Compiler for Embedded Memories. |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Jun Zhao 0005, V. Swamy Irrinki, Mukesh Puri, Fabrizio Lombardi |
Detection of Inter-Port Faults in Multi-Port Static RAMs. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Abderrahim Doumar, Hideo Ito |
Testing the Logic Cells and Interconnect Resources for FPGAs. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Tonia Morris, Erica Fletcher, Cyrus Afghahi, Sami Issa, Kevin Connolly, Jean-Charles Korta |
A Column-based Processing Array for High-speed Digital Image Processing. |
ARVLSI |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Spencer M. Gold, Richard B. Brown, Bruce Bernhardt |
A Quantitative Approach to Nonlinear Process Design Rule Scaling. |
ARVLSI |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Abderrahim Doumar, Hideo Ito |
An Automatic Testing and Diagnosis for FPGAs. |
PRDC |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Christian Legl, Bernd Wurth, Klaus Eckl |
Computing support-minimal subfunctions during functional decomposition. |
IEEE Trans. Very Large Scale Integr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Jesús Corbal, Roger Espasa, Mateo Valero |
Command Vector Memory Systems: High Performance at Low Cost. |
IEEE PACT |
1998 |
DBLP DOI BibTeX RDF |
memory systems, vector processors, SDRAM |
16 | Jian Liu, Rafic Z. Makki, Ayman I. Kayssi |
Dynamic Power Supply Current Testing of SRAMs. |
Asian Test Symposium |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Efficient utilization of scratch-pad memory in embedded processor applications. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Tzi-cker Chiueh, Srinidhi Varadarajan |
Design and Evaluation of a DRAM-based Shared Memory ATM Switch. |
SIGMETRICS |
1997 |
DBLP DOI BibTeX RDF |
|
16 | John Poulton |
An Embedded DRAM for CMOS ASICs. |
ARVLSI |
1997 |
DBLP DOI BibTeX RDF |
|
16 | George Kornaros, Christoforos E. Kozyrakis, Panagiota Vatsolaki, Manolis Katevenis |
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control. |
ARVLSI |
1997 |
DBLP DOI BibTeX RDF |
single-chip ATM switch, VLSI router, pipelined queue management, credit-based flow control |
16 | Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos E. Kozyrakis, Bruce McGaughy, David A. Patterson 0001, Thomas E. Anderson, Katherine A. Yelick |
The Energy Efficiency of IRAM Architectures. |
ISCA |
1997 |
DBLP DOI BibTeX RDF |
|
16 | J. Will Specks, Walter L. Engl |
Computer-aided design and scaling of deep submicron CMOS. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Ad J. van de Goor |
Using March Tests to Test SRAMs. |
IEEE Des. Test Comput. |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Shyang-Tai Su, Rafic Z. Makki |
Testing of static random access memories by monitoring dynamic power supply current. |
J. Electron. Test. |
1992 |
DBLP DOI BibTeX RDF |
Current-testable design, dynamic current monitors, dynamic power supply current, pattern sensitivity, fault modeling |
15 | Heeyeol Yu, Rabi N. Mahapatra |
A Power and Throughput-Efficient Packet Classifier with n Bloom Filters. |
IEEE Trans. Computers |
2011 |
DBLP DOI BibTeX RDF |
multiport memory, Bloom filter, SRAM, Packet processing |
15 | Fei Wu 0005, Xiang Chen, Jiguang Wan |
Cache Blocks: An Efficient Scheme for Solid State Drives without DRAM Cache. |
NAS |
2010 |
DBLP DOI BibTeX RDF |
Dirty Data, Random write, Power concumption, Comsumer electronics, SRAM, DRAM, Cache Blocks |
15 | Hassan Bajwa, Isaac G. Macwan, Vignesh Veerapandian, Xinghao Chen 0005 |
VHDL Implementation of High-Performance and Dynamically Configures Multi-port Cache Memory. |
ITNG |
2010 |
DBLP DOI BibTeX RDF |
Dynamically configured memory, Multi-port Cache Architecture, VHDL, SRAM |
15 | Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif |
Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
sram |
15 | Sanjeev K. Jain, Krishna Srivastva, Sanjiv Kainth |
A Novel Circuit to Optimize Access Time and Decoding Schemes in Memories. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Memory SRAM Register FIle ROM analog circuit |
15 | Weirong Jiang, Viktor K. Prasanna |
Large-scale wire-speed packet classification on FPGAs. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
fpga, decision tree, pipeline, sram, packet classification |
15 | Aarti Choudhary, Sandip Kundu |
A process variation tolerant self-compensating FinFET based sense amplifier design. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
sense amplifier, robustness, process -variation, yield, sram, finfet |
15 | Kaushik Roy 0001, Jaydeep P. Kulkarni, Sumeet Kumar Gupta |
Device/circuit interactions at 22nm technology node. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
22 nm technology node, DG MOSFETs, scaling, SRAM, transistor sizing, FinFETs |
15 | Annie (Yujuan) Zeng, James (JianQiang) Lü, Kenneth Rose, Ronald J. Gutmann |
First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration. |
IEEE Des. Test Comput. |
2005 |
DBLP DOI BibTeX RDF |
wafer-level 3D integration, SRAM, DRAM, cache performance, Access time, cycle time |
15 | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001 |
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage |
15 | Chanik Park, Junghee Lim, Kiwon Kwon, Jaejin Lee, Sang Lyul Min |
Compiler-assisted demand paging for embedded systems with flash memory. |
EMSOFT |
2004 |
DBLP DOI BibTeX RDF |
post-pass optimization, clustering, embedded systems, compilers, flash memory, paging, SRAM, heterogeneous memory |
15 | Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty |
Managing standby and active mode leakage power in deep sub-micron design. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS |
15 | Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg |
Data and memory optimization techniques for embedded systems. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
data optimization, memory architecture customization, memory power dissipation, high-level synthesis, survey, SRAM, allocation, data cache, DRAM, register file, architecture exploration, code transformation, address generation, size estimation |
15 | Pradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams |
Defect Analysis and a New Fault Model for Multi-port SRAMs. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
dual-port, SDDRF, electrical fault model, SRAM, defect analysis, multi-port |
15 | Said Hamdioui, Ad J. van de Goor |
An experimental analysis of spot defects in SRAMs: realistic fault models and tests. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
integrated circuit testing, fault models, fault coverage, SRAMs, functional fault models, SRAM chips, spot defects |
15 | John Woodfill, Brian Von Herzen |
Real-time stereo vision on the PARTS reconfigurable computer. |
FCCM |
1997 |
DBLP DOI BibTeX RDF |
powerful scalable reconfigurable computer, PARTS engine, real-time stereo vision, Xilinx 4025 FPGAs, partial torus, concurrent SRAM access, standard PCI card, stereo vision algorithm, stereo disparity computation, RISC-equivalent operations, 1 Mbyte, images, SRAMs, stereo image processing, personal computer, workstation, memory access |
11 | Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang |
A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. |
IEEE J. Solid State Circuits |
2024 |
DBLP DOI BibTeX RDF |
|
11 | Ashwin Sanjay Lele, Muya Chang, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury |
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. |
IEEE J. Solid State Circuits |
2024 |
DBLP DOI BibTeX RDF |
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