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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1460 occurrences of 724 keywords
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Results
Found 2136 publication records. Showing 2136 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
21 | Marco Ottavi, Gian Carlo Cardarilli, D. Cellitti, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 403-411, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
SSMM, fault tolerance, finite state machine, VHDL, signature analysis, self checking |
21 | Roberto A. Reyna, Daniel Esteve, Dominique Houzet, Marie-France Albenge |
Implementation of the SVM Neural Network Generalization Function for Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 147-, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SVM neural network generalization function, optimal decision hyperplane, training database, FPGA, Support Vector Machines, image processing, localization, VHDL, image classification, image classification, object detection, weights, learning process, statistical learning theory |
21 | Nalini K. Ratha, Anil K. Jain 0001, Diane T. Rover |
FPGA-Based Coprocessor for Text String Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 217-221, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA-based coprocessor, text string extraction, image morphology based algorithms, high-performance coprocessor, Splash 2, Sun hosts, VHDL behavioral modeling, SPARC station 20, design patterns, coprocessors, document understanding, visual effects |
21 | Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins |
Compiling and Optimizing Image Processing Algorithms for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 222-231, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SA-C, language features, SA-C algorithms, performance numbers, image processing routines, Annapolis Microsystems WildForce board, Xilinx 4036XL FPGAs, FPGAs, VHDL, optimizing compiler, high-level language, data flow graphs, data flow graphs, image processing algorithms |
21 | Basant Rajan, R. K. Shyamasundar |
Multiclock Esterel: A Reactive Framework for Asynchronous Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 201-210, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
VHDL, Reactive Systems, Asynchronous System, Synchrony, Esterel |
21 | Nicolau Cañellas, J. M. Moreno |
Speeding up Hardware Prototyping by Incremental Simulation/Emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), Paris, France, June 21-23, 2000, pp. 98-102, 2000, IEEE Computer Society, 0-7695-0668-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
logic simulation/emulation, FPGAs, VHDL, rapid prototyping |
21 | Annette Muth, Thomas Kolloch, Thomas Maier-Komor, Georg Färber |
An Evaluation of Code Generation Strategies Targeting Hardware for the Rapid Prototyping of SDL-Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), Paris, France, June 21-23, 2000, pp. 134-, 2000, IEEE Computer Society, 0-7695-0668-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
asynchronous modeling language, decomposition strategies, level of concurrency, code generation, VHDL, rapid prototyping, SDL, implementation model, application specific hardware |
21 | Andrew Stone, Elias S. Manolakos |
Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 92-102, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Optimal VHDL, DG2VHDL, Hierarchical CDFG, High Level Synthesis, Dependence Graph, Signal Flow Graph, Design Complexity |
21 | Marco Antonio Dal Poz, Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo |
A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 35-, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, VHDL, Reconfigurable Computing, Microprocessor, MPEG, RISC, Co-Design, Instruction Set, HDTV, Set-Top-Box, iDCT, cable TV |
21 | Dave Protheroe, Francesco Pessolano |
An Objective Measure of Digital System Design Quality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 227-233, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Design, Specification, Metrics, Quality, VHDL, Digital, Circuit, HDL |
21 | Ghassan Al Hayek, Chantal Robach |
From Design Validation to Hardware Testing: A Unified Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(1-2), pp. 133-140, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
VHDL, mutation testing, design validation |
21 | Massimo Buzzoni, Dario Cardini, Roberto Gallino, Roberto Romagnese |
ATM Traffic Management Systems: ASIC Fast Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 74-80, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
VHDL macrocells, FPGAs, Prototyping, ATM, Traffic Management |
21 | Valentina Salapura, Michael Gschwind |
Hardware/Software Co-Design of a Fuzzy RISC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 875-882, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism |
21 | Guido Schumacher, Wolfgang Nebel |
Object-Oriented Modelling of Parallel Hardware Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 234-241, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Language Issues, VHDL, Inheritance Anomaly |
21 | Thomas Müller-Wipperfürth, Richard Hagelauer |
Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 931-932, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
FSMD, VHDL, Statecharts, Graphical Modelling |
21 | Teresa Riesgo, Yago Torroja, Eduardo de la Torre, Javier Uceda |
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 955-956, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
VHDL, Fault modelling, Design validation, Design errors |
21 | Frank Vahid, Linus Tauro |
An Object-Oriented Communication Library for Hardware-Software CoDesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Fifth International Workshop on Hardware/Software Codesign, CODES/CASHE 1997, March 24-26, 1997, Braunschweig, Germany, pp. 81-86, 1997, IEEE Computer Society, 0-8186-7895-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Communication, Object-Oriented, C, VHDL, Libraries, Codesign |
21 | Karlheinz Agsteiner, Dieter Monjau, Sören Schulze |
Automating system construction by domain based approaches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 336-, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
system construction, domain based approaches, target system, abstract system specification, formal specification, specification, requirements, VHDL, digital systems, object-oriented approach, RISC processors |
21 | Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele |
A flexible VLSI architecture for variable block size segment matching with luminance correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 479-488, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
flexible VLSI architecture, variable block size segment matching, luminance correction, segment matching VLSI architecture, evolving motion estimation algorithms, preprocessing unit, halfpel interpolation, pixel decimation, VHDL synthesis, VLSI, CMOS technology, motion vectors, RAM, block matching algorithms, video coding standards |
21 | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar |
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 212-217, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Alternative Graphs, Malicious Fault List, VHDL, Fault Injection |
21 | Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri |
On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 547-563, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model |
21 | D. Sinclair, Ludo Cuypers, Kurt Verschaeve, E. Holz, Alexios N. Birbas, V. Mariatos, N. Kyrloglou, J.-L. Roux |
A formal approach to HW/SW co-design: the INSYDE project. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), March 11-15, 1996, Friedrichshafen, Germany., pp. 372-381, 1996, IEEE Computer Society, 0-8186-7355-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
INSYDE project, hybrid system co-design, formal description languages, requirements capture, formal verification, software tools, validation, VHDL, object-oriented design, object-oriented methods, SDL, hardware description languages, object-oriented analysis, hardware/software co-design, formal approach |
21 | Fred Rose, Todd Carpenter, Sanjaya Kumar, John Shackleton, Todd Steeves Honeywell |
A Model for the Coanalysis of Hardware and Software Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Forth International Workshop on Hardware/Software Codesign, CODES 1996, Pittsburgh, PA, USA, March 18-20, 1996, pp. 94-103, 1996, IEEE Computer Society, 0-8186-7243-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
RASSP, performance modeling, VHDL, hardware/software codesign |
21 | Stefan Fischer 0001, Jacek Wytrebowicz, Stanislaw Budkowski |
Hardware/Software Co-Design of Communication Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 476-483, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high performance distributed systems, system design techniques, standardized formal language Estelle, VHDL code, video-on-demand example, multimedia systems, multimedia systems, communication protocols, hardware/software codesign, C code |
21 | Rajesh K. Gupta 0001, Daniel Gajski, Randy Allen, Yatin Trivedi |
Opportunities and pitfalls in HDL-based system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 56-57, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
textual Hardware Description Languages, system designs, VHDL, modeling language, hardware description languages, Verilog, HDLs, hardware systems |
21 | Gerald G. Pechanek, M. Stojancic, Stamatis Vassiliadis, C. John Glossner |
MFAST: a single chip highly parallel image processing architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP ![In: Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995, pp. 69-72, 1995, IEEE Computer Society, 0-8186-7310-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
MFAST, single chip highly parallel image processing architecture, IBM Mwave, graphics processing, scalable array of processing elements, folded array, transpose operations, Mwave Folded Array Signal Transform processor, scalable DSP, algorithm execution, 2D DCT program, functional simulator models, 16 bit/s, 50 MHz, real-time systems, parallel architectures, VHDL, discrete cosine transforms, discrete cosine transform, hardware description languages, video signal processing, digital signal processing chips, matrix operations, real-time video processing |
21 | Timothy J. McBrayer, Philip A. Wilsey |
Process combination to increase event granularity in parallel logic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 572-578, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
event granularity, VHDL description, parallel processing, logic CAD, circuit analysis computing, logic circuits, logic circuits, symmetric multiprocessors, logic simulation, digital system design, parallel logic simulation, parallel logic simulators |
21 | Franco Fummi, Donatella Sciuto, M. Serro |
Synthesis for testability of large complexity controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 180-185, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates |
21 | Anne-Lise Courbis, Jean François Santucci |
Pseudo-random behavioral ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 192-, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
pseudo-random behavioral ATPG, fault diagnosis, logic testing, VHDL, automatic testing, hardware description languages |
21 | Luca Penzo, Donatella Sciuto, Cristina Silvano |
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 156-160, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
odd-weight-column byte error detection, SEC-DED codes, single error correction, double error detection, single byte error detection, SEC-DED-SBD codes, high performances VLSI implementations, high speed encoding/decoding circuits, parallel data manipulation, VHSIC Hardware Description Language, VHDL description, parallel processing, VLSI, software tool, error correction codes, application specific integrated circuits, logic CAD, decoding, VLSI design, error detection codes, hardware description languages, integrated logic circuits, digital integrated circuits |
21 | T. Collette, Hassane Essafi, Didier Juvin, J. Kaiser |
SYMPATIX: a SIMD computer performing the low and intermediate levels of image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE ![In: PARLE '92: Parallel Architectures and Languages Europe, 4th International PARLE Conference, Paris, France, June 15-18, 1992, Proceedings, pp. 147-161, 1992, Springer, 3-540-55599-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
intermediate level of image processing, VHDL system simulation, parallel processing, interconnection networks, SIMD |
21 | Kenneth P. Parker, Stig Oresjo |
A language for describing boundary scan devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(1), pp. 43-75, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
boundary scan testability, VHDL |
15 | Camel Tanougast, Michael Janiaut, Yves Berviller, Hassan Rabah, Serge Weber, Ahmed Bouridane |
An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 19(2), pp. 237-249, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Raphael Weber, Achim Rettberg |
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 330-335, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Levent Erkök, Magnus Carlsson, Adam Wick |
Hardware/software co-verification of cryptographic algorithms using Cryptol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 188-191, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Bernhard Peischl, Naveed Riaz, Franz Wotawa |
Advances in Automated Source-Level Debugging of Verilog Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
New Challenges in Applied Intelligence Technologies ![In: New Challenges in Applied Intelligence Technologies, pp. 363-372, 2008, Springer, 978-3-540-79354-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
debugging of hardware designs, multiple testcases, model-based diagnosis, software debugging |
15 | Boyan Valtchanov, Alain Aubert, Florent Bernard, Viktor Fischer |
Modeling and observing the jitter in ring oscillators implemented in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 158-163, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Joaquin Gracia, Luis J. Saiz, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil |
Analysis of the influence of intermittent faults in a microcontroller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 80-85, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Ahmad Sghaier, Shawki Areibi, Robert D. Dony |
IEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 519-522, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Youssef Serrestou, Vincent Beroulle, Chantal Robach |
Impact of hardware emulation on the verification quality improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 218-223, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull |
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 767-772, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni |
An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1424-1429, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | David Walter, Scott Little, Chris J. Myers |
Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATVA ![In: Automated Technology for Verification and Analysis, 5th International Symposium, ATVA 2007, Tokyo, Japan, October 22-25, 2007, Proceedings, pp. 66-81, 2007, Springer, 978-3-540-75595-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis |
A Quantitative Prediction Model for Hardware/Software Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 735-739, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Walid A. Najjar |
Compiling code accelerators for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 1-2, 2007, ACM. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FPGA code acceleration |
15 | Ales Smrcka, Tomás Vojnar |
Verifying Parametrised Hardware Designs Via Counter Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 51-68, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Vincent Brost, Fan Yang 0019, Michel Paindavoine |
A modular VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3968-3971, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Weidong Kuang, Casto Manuel Ibarra, Peiyi Zhao |
Soft Error Hardening for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 273-281, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Klaas L. Hofstra, Sabih H. Gerez |
Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, pp. 215-226, 2007, Springer, 978-3-540-69337-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Douglas R. Hickey, Philip A. Wilsey, Robert J. Hoekstra, Eric R. Keiter, Scott A. Hutchinson, Thomas V. Russo |
Mixed-Signal Simulation with the Simbus Backplane. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 39th Annual Simulation Symposium (ANSS-39 2006), 2-6 April 2006, Huntsville, Alabama, USA, pp. 223-229, 2006, IEEE Computer Society, 0-7695-2559-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Dae-Sung Ku, Phil-Jung Kim, Jung-Hyun Yun, Jong-Bin Kim |
A Design on the Digital Audio Synthesis Filter by DALUT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNC (2) ![In: Advances in Natural Computation, Second International Conference, ICNC 2006, Xi'an, China, September 24-28, 2006. Proceedings, Part II, pp. 861-869, 2006, Springer, 3-540-45907-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Jae-Jin Lee, Gi-Yong Song |
High-Level Synthesis Using SPARK and Systolic Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 455-460, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Kaiping Zeng, Sorin A. Huss |
Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 225-230, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Abdul-Rafeeq Abdul-Shakoor, Valek Szwarc |
A High Performance Soft Decision Viterbi Decoder for Wlan and Broadband Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 2468-2471, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Dan Cyca, Laurence E. Turner |
Bit-Serial Digital Filter Implementation using a Custom C Compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 534-537, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Robert Bogdan Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, Kenneth Maggio, Poras T. Balsara |
SoC with an integrated DSP and a 2.4-GHz RF transmitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1253-1265, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Jerker Hammarberg, Simin Nadjm-Tehrani |
Formal verification of fault tolerance in safety-critical reconfigurable modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 7(3), pp. 268-279, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Fault tolerance, FPGA, Formal verification, Safety analysis, Esterel |
15 | Damien Baumann, Jacques Tinembart |
Designing Mathematical Morphology Algorithms on FPGAs: An Application to Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAIP ![In: Computer Analysis of Images and Patterns, 11th International Conference, CAIP 2005, Versailles, France, September 5-8, 2005, Proceedings, pp. 562-569, 2005, Springer, 3-540-28969-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matús, Marcus Bronzel, Gerhard P. Fettweis |
Synchronous Transfer Architecture (STA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 343-352, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui |
Control and Data Flow Graph Extraction for High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 187-192, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006 |
Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 247, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | César Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin |
RASoC: A Router Soft-Core for Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 198-205, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, Systems-on-Chip, On-Chip Networks |
15 | Nico Bannow, Karsten Haug |
Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 268-273, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran |
Dual-pipeline heterogeneous ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 12-17, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dual-pipeline, instruction set generation, ASIP, superscalar |
15 | Miguel Morales-Sandoval, Claudia Feregrino Uribe |
On the Hardware Design of an Elliptic Curve Cryptosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ENC ![In: 5th Mexican International Conference on Computer Science (ENC 2004), 20-24 September 2004, Colima, Mexico, pp. 64-70, 2004, IEEE Computer Society, 0-7695-2160-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Heinz Mattes, Claus Dworski, Sebastian Sattler |
Controlled Sine Wave Fitting for ADC Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 963-971, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Jeremy Chan, Sri Parameswaran |
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 717-720, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Diana Toma, Dominique Borrione, Ghiath Al Sammane |
Combining Several Paradigms for Circuit Validation and Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASSIS ![In: Construction and Analysis of Safe, Secure, and Interoperable Smart Devices, International Workshop, CASSIS 2004, Marseille, France, March 10-14, 2004, Revised Selected Papers, pp. 229-249, 2004, Springer, 3-540-24287-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Kerstin Buchacker, Mario Dal Cin, Hans-Jörg Höxer, Roland Karch, Volkmar Sieh, Oliver Tschäche |
Reproducible Dependability Benchmarking Experiments Based on Unambiguous Benchmark Setup Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2003 International Conference on Dependable Systems and Networks (DSN 2003), 22-25 June 2003, San Francisco, CA, USA, Proceedings, pp. 469-478, 2003, IEEE Computer Society, 0-7695-1952-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Jean Oudinot |
The Most Complete Mixed-Signal Simulation Solution with ADVance MS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 193, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson |
Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 237, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Khaled Benkrid, Samir Belkacemi, Danny Crookes |
A logic based approach to hardware abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 238, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Pierluigi Daglio, Carlo Roma |
A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 20274-20279, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Claudiu Zissulescu, Todor P. Stefanov, Bart Kienhuis, Ed F. Deprettere |
Laura: Leiden Architecture Research and Exploration Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 911-920, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Paul Gardner-Stephen, Greg Knowles |
A Novel Architecture for Genomic Sequence Searching and Alignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 180-192, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Amr T. Abdel-Hamid, Sofiène Tahar, John Harrison 0001 |
Enabling Hardware Verification through Design Changes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 4th International Conference on Formal Engineering Methods, ICFEM 2002 Shanghai, China, October 21-25, 2002, Proceedings, pp. 459-470, 2002, Springer, 3-540-00029-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Richard Sharp |
Functional Design Using Behavioural and Structural Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, 4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings, pp. 324-341, 2002, Springer, 3-540-00116-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita |
Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 92-98, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Clock-delayed domino circuit, Fault simulation, crosstalk fault |
15 | Tomás Bautista, Antonio Núñez |
Quantitative study of the impact of design and synthesis options on processor core performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(3), pp. 461-473, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm |
An automated process for compiling dataflow graphs into reconfigurable hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(1), pp. 130-139, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Janette Frigo, Maya B. Gokhale, Dominique Lavenier |
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 134-140, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler |
15 | Andrew P. Paplinski, Nandita Bhattacharjee, Charles Greif |
Rotating Ultrasonic Signal Vectors with a Word-Parallel CORDIC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 254-261, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Andrew Stone, Elias S. Manolakos |
DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 24(1), pp. 99-120, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon |
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, pp. 3-13, 2000, Springer, 3-540-41068-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Eric K. Pauer, Paul D. Fiore, John M. Smith, Cory S. Myers |
Algorithm analysis and mapping environment for adaptive computing systems (poster abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 217, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Mohammad A. Mikki, Kangbin Yim, Gihyun Jung |
Popularity-Independent Multimedia-on-Demand Server Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC ![In: 24th International Computer Software and Applications Conference (COMPSAC 2000), 25-28 October 2000, Taipei, Taiwan, pp. 575-580, 2000, IEEE Computer Society, 0-7695-0792-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper |
Compiling Image Processing Applications to Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 56-65, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
compilers, Configurable computing, image processing applications |
15 | Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar |
Simulation of a Digital Neuro-Chip for Spiking Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN (4) ![In: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, IJCNN 2000, Neural Computing: New Challenges and Perspectives for the New Millennium, Como, Italy, July 24-27, 2000, Volume 4, pp. 490-498, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Robert L. Ewing |
Technology Road Map to Methodologies for Mixed-Signal System Design and Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 22(2), pp. 123-134, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Katriina Heikkinen, Petri Vuorimaa |
Computation of Two Texture Features in Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIAP ![In: 1oth International Conference on Image Analysis and Processing (ICIAP 1999), 27-29 September 1999, Venice, Italy, pp. 125-129, 1999, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Matthias Dörfel, Frank Slomka, Richard Hofmann |
A Scalable Hardware Library for the Rapid Prototyping of SDL Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), Clearwater, Florida, USA, June 16-18, 1999, pp. 120-, 1999, IEEE Computer Society, 0-7695-0246-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Interface Selection, High-Level Synthesis, Rapid Prototyping, SDL, Codesign, Communication Systems |
15 | Tomás Bautista, Antonio Núñez |
Design of Efficient SPARC Cores for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1236-1239, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Gregor Polansek, Andrej Zemva, Andrej Trost |
HW/SW Co-Simulation of Target C++ Applications and Synthesizable HDL with Performance Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1468-1471, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
15 | E. Lago, Carlos Jesús Jiménez-Fernández, Diego R. López, Santiago Sánchez-Solano, Angel Barriga |
XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 102-107, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Jean Paul Calvez, Dominique Heller, F. Muller, Olivier Pasquier |
A Programmable Multi-Language Generator for CoDesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 927-928, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
meta-generator, code generator, CoDesign |
15 | Guido Post, Andrea Müller, Thorsten Grötker |
A System-Level Co-Verification Environment for ATM Hardware Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 424-428, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
test bench design and reuse, ATM hardware design, system design methodology, co-simulation, interface modeling, co-verification |
15 | Wayne Luk, Steve McKeever |
Pebble: A Language for Parametrised and Reconfigurable Hardware Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 9-18, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Robert Macketanz, Wolfgang Karl |
JVX - A Rapid Prototyping System Based on Java and FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 99-108, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Peter T. Breuer, Natividad Martínez Madrid, Carlos Delgado Kloos |
The Computational Description of Analogue System Behaviour. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Prospects for Hardware Foundations ![In: Prospects for Hardware Foundations, ESPRIT Working Group 8533, NADA - New Hardware Design Methods, Survey Chapters, pp. 309-332, 1998, Springer, 3-540-65461-5. The full citation details ...](Pics/full.jpeg) |
1998 |
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15 | Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch |
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 56-61, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
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