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Found 2136 publication records. Showing 2136 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
21 | Marco Ottavi, Gian Carlo Cardarilli, D. Cellitti, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines. |
DFT |
2001 |
DBLP DOI BibTeX RDF |
SSMM, fault tolerance, finite state machine, VHDL, signature analysis, self checking |
21 | Roberto A. Reyna, Daniel Esteve, Dominique Houzet, Marie-France Albenge |
Implementation of the SVM Neural Network Generalization Function for Image Processing. |
CAMP |
2000 |
DBLP DOI BibTeX RDF |
SVM neural network generalization function, optimal decision hyperplane, training database, FPGA, Support Vector Machines, image processing, localization, VHDL, image classification, image classification, object detection, weights, learning process, statistical learning theory |
21 | Nalini K. Ratha, Anil K. Jain 0001, Diane T. Rover |
FPGA-Based Coprocessor for Text String Extraction. |
CAMP |
2000 |
DBLP DOI BibTeX RDF |
FPGA-based coprocessor, text string extraction, image morphology based algorithms, high-performance coprocessor, Splash 2, Sun hosts, VHDL behavioral modeling, SPARC station 20, design patterns, coprocessors, document understanding, visual effects |
21 | Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins |
Compiling and Optimizing Image Processing Algorithms for FPGAs. |
CAMP |
2000 |
DBLP DOI BibTeX RDF |
SA-C, language features, SA-C algorithms, performance numbers, image processing routines, Annapolis Microsystems WildForce board, Xilinx 4036XL FPGAs, FPGAs, VHDL, optimizing compiler, high-level language, data flow graphs, data flow graphs, image processing algorithms |
21 | Basant Rajan, R. K. Shyamasundar |
Multiclock Esterel: A Reactive Framework for Asynchronous Design. |
IPDPS |
2000 |
DBLP DOI BibTeX RDF |
VHDL, Reactive Systems, Asynchronous System, Synchrony, Esterel |
21 | Nicolau Cañellas, J. M. Moreno |
Speeding up Hardware Prototyping by Incremental Simulation/Emulation. |
IEEE International Workshop on Rapid System Prototyping |
2000 |
DBLP DOI BibTeX RDF |
logic simulation/emulation, FPGAs, VHDL, rapid prototyping |
21 | Annette Muth, Thomas Kolloch, Thomas Maier-Komor, Georg Färber |
An Evaluation of Code Generation Strategies Targeting Hardware for the Rapid Prototyping of SDL-Specifications. |
IEEE International Workshop on Rapid System Prototyping |
2000 |
DBLP DOI BibTeX RDF |
asynchronous modeling language, decomposition strategies, level of concurrency, code generation, VHDL, rapid prototyping, SDL, implementation model, application specific hardware |
21 | Andrew Stone, Elias S. Manolakos |
Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
Optimal VHDL, DG2VHDL, Hierarchical CDFG, High Level Synthesis, Dependence Graph, Signal Flow Graph, Design Complexity |
21 | Marco Antonio Dal Poz, Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo |
A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
FPGA, VHDL, Reconfigurable Computing, Microprocessor, MPEG, RISC, Co-Design, Instruction Set, HDTV, Set-Top-Box, iDCT, cable TV |
21 | Dave Protheroe, Francesco Pessolano |
An Objective Measure of Digital System Design Quality. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
Design, Specification, Metrics, Quality, VHDL, Digital, Circuit, HDL |
21 | Ghassan Al Hayek, Chantal Robach |
From Design Validation to Hardware Testing: A Unified Approach. |
J. Electron. Test. |
1999 |
DBLP DOI BibTeX RDF |
VHDL, mutation testing, design validation |
21 | Massimo Buzzoni, Dario Cardini, Roberto Gallino, Roberto Romagnese |
ATM Traffic Management Systems: ASIC Fast Prototyping. |
IEEE International Workshop on Rapid System Prototyping |
1999 |
DBLP DOI BibTeX RDF |
VHDL macrocells, FPGAs, Prototyping, ATM, Traffic Management |
21 | Valentina Salapura, Michael Gschwind |
Hardware/Software Co-Design of a Fuzzy RISC Processor. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
hardware/software co-evaluation, processor core, MIPS RISC processor, fuzzy processing, fuzzy rule evaluation, instruction set definition, performance evaluation, VHDL, logic synthesis, application specific instruction set processor (ASIP), hardware/software co-design, instruction set architecture, subword parallelism |
21 | Guido Schumacher, Wolfgang Nebel |
Object-Oriented Modelling of Parallel Hardware Systems. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
Language Issues, VHDL, Inheritance Anomaly |
21 | Thomas Müller-Wipperfürth, Richard Hagelauer |
Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
FSMD, VHDL, Statecharts, Graphical Modelling |
21 | Teresa Riesgo, Yago Torroja, Eduardo de la Torre, Javier Uceda |
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
VHDL, Fault modelling, Design validation, Design errors |
21 | Frank Vahid, Linus Tauro |
An Object-Oriented Communication Library for Hardware-Software CoDesign. |
CODES |
1997 |
DBLP DOI BibTeX RDF |
Communication, Object-Oriented, C, VHDL, Libraries, Codesign |
21 | Karlheinz Agsteiner, Dieter Monjau, Sören Schulze |
Automating system construction by domain based approaches. |
EUROMICRO |
1997 |
DBLP DOI BibTeX RDF |
system construction, domain based approaches, target system, abstract system specification, formal specification, specification, requirements, VHDL, digital systems, object-oriented approach, RISC processors |
21 | Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele |
A flexible VLSI architecture for variable block size segment matching with luminance correction. |
ASAP |
1997 |
DBLP DOI BibTeX RDF |
flexible VLSI architecture, variable block size segment matching, luminance correction, segment matching VLSI architecture, evolving motion estimation algorithms, preprocessing unit, halfpel interpolation, pixel decimation, VHDL synthesis, VLSI, CMOS technology, motion vectors, RAM, block matching algorithms, video coding standards |
21 | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar |
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. |
DFT |
1997 |
DBLP DOI BibTeX RDF |
Alternative Graphs, Malicious Fault List, VHDL, Fault Injection |
21 | Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri |
On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model |
21 | D. Sinclair, Ludo Cuypers, Kurt Verschaeve, E. Holz, Alexios N. Birbas, V. Mariatos, N. Kyrloglou, J.-L. Roux |
A formal approach to HW/SW co-design: the INSYDE project. |
ECBS |
1996 |
DBLP DOI BibTeX RDF |
INSYDE project, hybrid system co-design, formal description languages, requirements capture, formal verification, software tools, validation, VHDL, object-oriented design, object-oriented methods, SDL, hardware description languages, object-oriented analysis, hardware/software co-design, formal approach |
21 | Fred Rose, Todd Carpenter, Sanjaya Kumar, John Shackleton, Todd Steeves Honeywell |
A Model for the Coanalysis of Hardware and Software Architectures. |
CODES |
1996 |
DBLP DOI BibTeX RDF |
RASSP, performance modeling, VHDL, hardware/software codesign |
21 | Stefan Fischer 0001, Jacek Wytrebowicz, Stanislaw Budkowski |
Hardware/Software Co-Design of Communication Protocols. |
EUROMICRO |
1996 |
DBLP DOI BibTeX RDF |
high performance distributed systems, system design techniques, standardized formal language Estelle, VHDL code, video-on-demand example, multimedia systems, multimedia systems, communication protocols, hardware/software codesign, C code |
21 | Rajesh K. Gupta 0001, Daniel Gajski, Randy Allen, Yatin Trivedi |
Opportunities and pitfalls in HDL-based system design. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
textual Hardware Description Languages, system designs, VHDL, modeling language, hardware description languages, Verilog, HDLs, hardware systems |
21 | Gerald G. Pechanek, M. Stojancic, Stamatis Vassiliadis, C. John Glossner |
MFAST: a single chip highly parallel image processing architecture. |
ICIP |
1995 |
DBLP DOI BibTeX RDF |
MFAST, single chip highly parallel image processing architecture, IBM Mwave, graphics processing, scalable array of processing elements, folded array, transpose operations, Mwave Folded Array Signal Transform processor, scalable DSP, algorithm execution, 2D DCT program, functional simulator models, 16 bit/s, 50 MHz, real-time systems, parallel architectures, VHDL, discrete cosine transforms, discrete cosine transform, hardware description languages, video signal processing, digital signal processing chips, matrix operations, real-time video processing |
21 | Timothy J. McBrayer, Philip A. Wilsey |
Process combination to increase event granularity in parallel logic simulation. |
IPPS |
1995 |
DBLP DOI BibTeX RDF |
event granularity, VHDL description, parallel processing, logic CAD, circuit analysis computing, logic circuits, logic circuits, symmetric multiprocessors, logic simulation, digital system design, parallel logic simulation, parallel logic simulators |
21 | Franco Fummi, Donatella Sciuto, M. Serro |
Synthesis for testability of large complexity controllers. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
large complexity controllers, industrial design environments, top-down methodology, hierarchical descriptions, irredundant circuits, optimized gate-level descriptions, testable descriptions, specification, high level synthesis, finite state machines, finite state machines, design for testability, design for testability, VHDL, automatic testing, logic CAD, hardware description languages, FSM, synthesis for testability, logic gates |
21 | Anne-Lise Courbis, Jean François Santucci |
Pseudo-random behavioral ATPG. |
Great Lakes Symposium on VLSI |
1995 |
DBLP DOI BibTeX RDF |
pseudo-random behavioral ATPG, fault diagnosis, logic testing, VHDL, automatic testing, hardware description languages |
21 | Luca Penzo, Donatella Sciuto, Cristina Silvano |
VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
odd-weight-column byte error detection, SEC-DED codes, single error correction, double error detection, single byte error detection, SEC-DED-SBD codes, high performances VLSI implementations, high speed encoding/decoding circuits, parallel data manipulation, VHSIC Hardware Description Language, VHDL description, parallel processing, VLSI, software tool, error correction codes, application specific integrated circuits, logic CAD, decoding, VLSI design, error detection codes, hardware description languages, integrated logic circuits, digital integrated circuits |
21 | T. Collette, Hassane Essafi, Didier Juvin, J. Kaiser |
SYMPATIX: a SIMD computer performing the low and intermediate levels of image processing. |
PARLE |
1992 |
DBLP DOI BibTeX RDF |
intermediate level of image processing, VHDL system simulation, parallel processing, interconnection networks, SIMD |
21 | Kenneth P. Parker, Stig Oresjo |
A language for describing boundary scan devices. |
J. Electron. Test. |
1991 |
DBLP DOI BibTeX RDF |
boundary scan testability, VHDL |
15 | Camel Tanougast, Michael Janiaut, Yves Berviller, Hassan Rabah, Serge Weber, Ahmed Bouridane |
An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis. |
IEEE Trans. Circuits Syst. Video Technol. |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Raphael Weber, Achim Rettberg |
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Levent Erkök, Magnus Carlsson, Adam Wick |
Hardware/software co-verification of cryptographic algorithms using Cryptol. |
FMCAD |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Bernhard Peischl, Naveed Riaz, Franz Wotawa |
Advances in Automated Source-Level Debugging of Verilog Designs. |
New Challenges in Applied Intelligence Technologies |
2008 |
DBLP DOI BibTeX RDF |
debugging of hardware designs, multiple testcases, model-based diagnosis, software debugging |
15 | Boyan Valtchanov, Alain Aubert, Florent Bernard, Viktor Fischer |
Modeling and observing the jitter in ring oscillators implemented in FPGAs. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Joaquin Gracia, Luis J. Saiz, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil |
Analysis of the influence of intermittent faults in a microcontroller. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Ahmad Sghaier, Shawki Areibi, Robert D. Dony |
IEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Youssef Serrestou, Vincent Beroulle, Chantal Robach |
Impact of hardware emulation on the verification quality improvement. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull |
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni |
An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
15 | David Walter, Scott Little, Chris J. Myers |
Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. |
ATVA |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis |
A Quantitative Prediction Model for Hardware/Software Partitioning. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Walid A. Najjar |
Compiling code accelerators for FPGAs. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
FPGA code acceleration |
15 | Ales Smrcka, Tomás Vojnar |
Verifying Parametrised Hardware Designs Via Counter Automata. |
Haifa Verification Conference |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Vincent Brost, Fan Yang 0019, Michel Paindavoine |
A modular VLIW Processor. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Weidong Kuang, Casto Manuel Ibarra, Peiyi Zhao |
Soft Error Hardening for Asynchronous Circuits. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Klaas L. Hofstra, Sabih H. Gerez |
Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms. |
HiPEAC |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Douglas R. Hickey, Philip A. Wilsey, Robert J. Hoekstra, Eric R. Keiter, Scott A. Hutchinson, Thomas V. Russo |
Mixed-Signal Simulation with the Simbus Backplane. |
Annual Simulation Symposium |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Dae-Sung Ku, Phil-Jung Kim, Jung-Hyun Yun, Jong-Bin Kim |
A Design on the Digital Audio Synthesis Filter by DALUT. |
ICNC (2) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Jae-Jin Lee, Gi-Yong Song |
High-Level Synthesis Using SPARK and Systolic Array. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Kaiping Zeng, Sorin A. Huss |
Structure Synthesis of Analog and Mixed-Signal Circuits using Partition Techniques. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Abdul-Rafeeq Abdul-Shakoor, Valek Szwarc |
A High Performance Soft Decision Viterbi Decoder for Wlan and Broadband Applications. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Dan Cyca, Laurence E. Turner |
Bit-Serial Digital Filter Implementation using a Custom C Compiler. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Robert Bogdan Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, Kenneth Maggio, Poras T. Balsara |
SoC with an integrated DSP and a 2.4-GHz RF transmitter. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Jerker Hammarberg, Simin Nadjm-Tehrani |
Formal verification of fault tolerance in safety-critical reconfigurable modules. |
Int. J. Softw. Tools Technol. Transf. |
2005 |
DBLP DOI BibTeX RDF |
Fault tolerance, FPGA, Formal verification, Safety analysis, Esterel |
15 | Damien Baumann, Jacques Tinembart |
Designing Mathematical Morphology Algorithms on FPGAs: An Application to Image Processing. |
CAIP |
2005 |
DBLP DOI BibTeX RDF |
|
15 | Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matús, Marcus Bronzel, Gerhard P. Fettweis |
Synchronous Transfer Architecture (STA). |
SAMOS |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui |
Control and Data Flow Graph Extraction for High-Level Synthesis. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller 0006 |
Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
15 | César Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin |
RASoC: A Router Soft-Core for Networks-on-Chip. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
FPGA, Systems-on-Chip, On-Chip Networks |
15 | Nico Bannow, Karsten Haug |
Evaluation of an Object-Oriented Hardware Design Methodology for Automotive Applications. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Swarnalatha Radhakrishnan, Hui Guo 0001, Sri Parameswaran |
Dual-pipeline heterogeneous ASIP design. |
CODES+ISSS |
2004 |
DBLP DOI BibTeX RDF |
dual-pipeline, instruction set generation, ASIP, superscalar |
15 | Miguel Morales-Sandoval, Claudia Feregrino Uribe |
On the Hardware Design of an Elliptic Curve Cryptosystem. |
ENC |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Heinz Mattes, Claus Dworski, Sebastian Sattler |
Controlled Sine Wave Fitting for ADC Test. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Jeremy Chan, Sri Parameswaran |
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Diana Toma, Dominique Borrione, Ghiath Al Sammane |
Combining Several Paradigms for Circuit Validation and Verification. |
CASSIS |
2004 |
DBLP DOI BibTeX RDF |
|
15 | Kerstin Buchacker, Mario Dal Cin, Hans-Jörg Höxer, Roland Karch, Volkmar Sieh, Oliver Tschäche |
Reproducible Dependability Benchmarking Experiments Based on Unambiguous Benchmark Setup Descriptions. |
DSN |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Jean Oudinot |
The Most Complete Mixed-Signal Simulation Solution with ADVance MS. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson |
Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Khaled Benkrid, Samir Belkacemi, Danny Crookes |
A logic based approach to hardware abstraction. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Pierluigi Daglio, Carlo Roma |
A Fully Qualified Top-Down and Bottom-Up Mixed-Signal Design Flow for Non Volatile Memories Technologies. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Claudiu Zissulescu, Todor P. Stefanov, Bart Kienhuis, Ed F. Deprettere |
Laura: Leiden Architecture Research and Exploration Tool. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Paul Gardner-Stephen, Greg Knowles |
A Novel Architecture for Genomic Sequence Searching and Alignment. |
Asia-Pacific Computer Systems Architecture Conference |
2003 |
DBLP DOI BibTeX RDF |
|
15 | Amr T. Abdel-Hamid, Sofiène Tahar, John Harrison 0001 |
Enabling Hardware Verification through Design Changes. |
ICFEM |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Richard Sharp |
Functional Design Using Behavioural and Structural Components. |
FMCAD |
2002 |
DBLP DOI BibTeX RDF |
|
15 | Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita |
Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
Clock-delayed domino circuit, Fault simulation, crosstalk fault |
15 | Tomás Bautista, Antonio Núñez |
Quantitative study of the impact of design and synthesis options on processor core performance. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm |
An automated process for compiling dataflow graphs into reconfigurable hardware. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Janette Frigo, Maya B. Gokhale, Dominique Lavenier |
Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler |
15 | Andrew P. Paplinski, Nandita Bhattacharjee, Charles Greif |
Rotating Ultrasonic Signal Vectors with a Word-Parallel CORDIC Processor. |
DSD |
2001 |
DBLP DOI BibTeX RDF |
|
15 | Andrew Stone, Elias S. Manolakos |
DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures. |
J. VLSI Signal Process. |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Manuela Anton, Mauro Chinosi, Daniele Sirtori, Roberto Zafalon |
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Eric K. Pauer, Paul D. Fiore, John M. Smith, Cory S. Myers |
Algorithm analysis and mapping environment for adaptive computing systems (poster abstract). |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Mohammad A. Mikki, Kangbin Yim, Gihyun Jung |
Popularity-Independent Multimedia-on-Demand Server Model. |
COMPSAC |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper |
Compiling Image Processing Applications to Reconfigurable Hardware. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
compilers, Configurable computing, image processing applications |
15 | Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar |
Simulation of a Digital Neuro-Chip for Spiking Neural Networks. |
IJCNN (4) |
2000 |
DBLP DOI BibTeX RDF |
|
15 | Robert L. Ewing |
Technology Road Map to Methodologies for Mixed-Signal System Design and Simulation. |
J. VLSI Signal Process. |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Katriina Heikkinen, Petri Vuorimaa |
Computation of Two Texture Features in Hardware. |
ICIAP |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Matthias Dörfel, Frank Slomka, Richard Hofmann |
A Scalable Hardware Library for the Rapid Prototyping of SDL Specifications. |
IEEE International Workshop on Rapid System Prototyping |
1999 |
DBLP DOI BibTeX RDF |
Interface Selection, High-Level Synthesis, Rapid Prototyping, SDL, Codesign, Communication Systems |
15 | Tomás Bautista, Antonio Núñez |
Design of Efficient SPARC Cores for Embedded Systems. |
EUROMICRO |
1999 |
DBLP DOI BibTeX RDF |
|
15 | Gregor Polansek, Andrej Zemva, Andrej Trost |
HW/SW Co-Simulation of Target C++ Applications and Synthesizable HDL with Performance Estimation. |
EUROMICRO |
1999 |
DBLP DOI BibTeX RDF |
|
15 | E. Lago, Carlos Jesús Jiménez-Fernández, Diego R. López, Santiago Sánchez-Solano, Angel Barriga |
XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Jean Paul Calvez, Dominique Heller, F. Muller, Olivier Pasquier |
A Programmable Multi-Language Generator for CoDesign. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
meta-generator, code generator, CoDesign |
15 | Guido Post, Andrea Müller, Thorsten Grötker |
A System-Level Co-Verification Environment for ATM Hardware Design. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
test bench design and reuse, ATM hardware design, system design methodology, co-simulation, interface modeling, co-verification |
15 | Wayne Luk, Steve McKeever |
Pebble: A Language for Parametrised and Reconfigurable Hardware Design. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Robert Macketanz, Wolfgang Karl |
JVX - A Rapid Prototyping System Based on Java and FPGAs. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Peter T. Breuer, Natividad Martínez Madrid, Carlos Delgado Kloos |
The Computational Description of Analogue System Behaviour. |
Prospects for Hardware Foundations |
1998 |
DBLP DOI BibTeX RDF |
|
15 | Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch |
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
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